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aarch64: Add basic support for armv8.7-a architecture

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This patch adds support for AArch64 -march=armv8.7-a command line option
in GAS.

Please note that this change ONLY extends -march= command line interface
with a new "armv8.7-a" option. Architectural changes like new instructions
will be added in following patches.

gas/ChangeLog:

2020-10-16  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>

	* NEWS: Docs update.
	* config/tc-aarch64.c (armv8.7-a): New arch.
	* doc/c-aarch64.texi (-march=armv8.7-a): Update docs.

include/ChangeLog:

2020-10-16  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>

	* opcode/aarch64.h (AARCH64_FEATURE_V8_7): New feature bitmask.
	(AARCH64_ARCH_V8_7): New arch feature set.

opcodes/ChangeLog:

2020-10-16  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>

	* aarch64-tbl.h (ARMV8_7): New macro.
This commit is contained in:
Przemyslaw Wirkus 2020-10-28 13:58:17 +00:00
parent 2aec1123f9
commit 8926e54e3a
5 changed files with 9 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
gas/NEWS
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@ -19,7 +19,7 @@
Extension) and BRBE (Branch Record Buffer Extension) system registers for
AArch64.
* Add support for Armv8-R AArch64.
* Add support for Armv8-R and Armv8.7-A AArch64.
* Add support for Intel TDX instructions.

1
gas/config/tc-aarch64.c
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@ -9033,6 +9033,7 @@ static const struct aarch64_arch_option_table aarch64_archs[] = {
{"armv8.4-a", AARCH64_ARCH_V8_4},
{"armv8.5-a", AARCH64_ARCH_V8_5},
{"armv8.6-a", AARCH64_ARCH_V8_6},
{"armv8.7-a", AARCH64_ARCH_V8_7},
{"armv8-r", AARCH64_ARCH_V8_R},
{NULL, AARCH64_ARCH_NONE}
};

2
gas/doc/c-aarch64.texi
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@ -106,7 +106,7 @@ issue an error message if an attempt is made to assemble an
instruction which will not execute on the target architecture. The
following architecture names are recognized: @code{armv8-a},
@code{armv8.1-a}, @code{armv8.2-a}, @code{armv8.3-a}, @code{armv8.4-a}
@code{armv8.5-a}, @code{armv8.6-a}, and @code{armv8-r}.
@code{armv8.5-a}, @code{armv8.6-a}, @code{armv8.7-a}, and @code{armv8-r}.
If both @option{-mcpu} and @option{-march} are specified, the
assembler will use the setting for @option{-mcpu}. If neither are

3
include/opcode/aarch64.h
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@ -50,6 +50,7 @@ typedef uint32_t aarch64_insn;
#define AARCH64_FEATURE_SVE2_SHA3 (1ULL << 10)
#define AARCH64_FEATURE_V8_4 (1ULL << 11) /* ARMv8.4 processors. */
#define AARCH64_FEATURE_V8_R (1ULL << 12) /* Armv8-R processors. */
#define AARCH64_FEATURE_V8_7 (1ULL << 13) /* Armv8.7 processors. */
#define AARCH64_FEATURE_FP (1ULL << 17) /* FP instructions. */
#define AARCH64_FEATURE_SIMD (1ULL << 18) /* SIMD instructions. */
#define AARCH64_FEATURE_CRC (1ULL << 19) /* CRC instructions. */
@ -128,6 +129,8 @@ typedef uint32_t aarch64_insn;
AARCH64_FEATURE_V8_6 \
| AARCH64_FEATURE_BFLOAT16 \
| AARCH64_FEATURE_I8MM)
#define AARCH64_ARCH_V8_7 AARCH64_FEATURE (AARCH64_ARCH_V8_6, \
AARCH64_FEATURE_V8_7)
#define AARCH64_ARCH_V8_R (AARCH64_FEATURE (AARCH64_ARCH_V8_4, \
AARCH64_FEATURE_V8_R) \
& ~(AARCH64_FEATURE_V8_A | AARCH64_FEATURE_LOR))

3
opcodes/aarch64-tbl.h
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@ -2395,6 +2395,8 @@ static const aarch64_feature_set aarch64_feature_sve2bitperm =
AARCH64_FEATURE (AARCH64_FEATURE_SVE2 | AARCH64_FEATURE_SVE2_BITPERM, 0);
static const aarch64_feature_set aarch64_feature_v8_6 =
AARCH64_FEATURE (AARCH64_FEATURE_V8_6, 0);
static const aarch64_feature_set aarch64_feature_v8_7 =
AARCH64_FEATURE (AARCH64_FEATURE_V8_7, 0);
static const aarch64_feature_set aarch64_feature_i8mm =
AARCH64_FEATURE (AARCH64_FEATURE_V8_2 | AARCH64_FEATURE_I8MM, 0);
static const aarch64_feature_set aarch64_feature_i8mm_sve =
@ -2453,6 +2455,7 @@ static const aarch64_feature_set aarch64_feature_v8_r =
#define F64MM_SVE &aarch64_feature_f64mm_sve
#define I8MM &aarch64_feature_i8mm
#define ARMV8_R &aarch64_feature_v8_r
#define ARMV8_7 &aarch64_feature_v8_7
#define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL }