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RISC-V: Support Zacas extension.
https://github.com/riscvarchive/riscv-zacas/releases/tag/v1.0 The Zacas extension introduce compare-and-swap instructions to operate on 32-bit, 64-bit and 128-bit (RV64 only) data values. It introduces three new instructions: - amocas.w (32-bit CAS) - amocas.d (64-bit CAS) - amocas.q (128-bit CAS, RV64 only) Like other AMOs in the A extension, Zacas instructions have '.aq', '.rl' and '.aqrl' variations. bfd/ChangeLog: * elfxx-riscv.c (riscv_implicit_subsets): 'A' implied by 'Zacas'. (riscv_supported_std_z_ext): Add 'Zacas' extension. (riscv_multi_subset_supports, riscv_multi_subset_supports_ext): Handle INSN_CLASS_ZACAS case. gas/ChangeLog: * NEWS: Updated. * testsuite/gas/riscv/march-help.l: Updated. * testsuite/gas/riscv/zacas-32.d: New test (RV32). * testsuite/gas/riscv/zacas-fail-32.d: Likewise. * testsuite/gas/riscv/zacas-64.d: New test (RV64). * testsuite/gas/riscv/zacas-fail-64.d: Likewise. * testsuite/gas/riscv/zacas.s: New test source. * testsuite/gas/riscv/zacas-fail.s: Likewise. * testsuite/gas/riscv/zacas-fail-32.l: New file. * testsuite/gas/riscv/zacas-fail-64.l: Likewise. include/ChangeLog: * include/opcode/riscv.h (INSN_CLASS_ZACAS): New definition. * include/opcode/riscv-opc.h (MATCH_AMOCAS_W, MASK_AMOCAS_W) (MATCH_AMOCAS_D, MASK_AMOCAS_D, MATCH_AMOCAS_Q, MASK_AMOCAS_Q): Likewise. (amocas_w, amocas_d, amocas_q): Declare instructions. opcodes/ChangeLog: * riscv-opc.c (match_rs2_rd_even): New function. (amocas_w, amocas_d, amocas_q, amocas_w.aq) (amocas_d.aq, amocas_q.aq, amocas_w.rl, amocas_d.rl, amocas_q.rl) (amocas_w.aqrl, amocas_d.aqrl, amocas_q.aqrl): Add instructions.
This commit is contained in:
Gianluca Guida
Nelson Chu
parent
0915235d34
commit
88729e9616
@ -1192,6 +1192,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
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{"v", "zve64d", check_implicit_always},
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{"v", "zvl128b", check_implicit_always},
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{"zabha", "a", check_implicit_always},
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{"zacas", "a", check_implicit_always},
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{"zvfbfmin", "zve32f", check_implicit_always},
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{"zvfbfwma", "zve32f", check_implicit_always},
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{"zvfbfwma", "zfbfmin", check_implicit_always},
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@ -1363,6 +1364,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
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{"zmmul", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
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{"zaamo", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
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{"zabha", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
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{"zacas", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
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{"zalrsc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
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{"zawrs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
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{"zfbfmin", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
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@ -2545,6 +2547,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
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return riscv_subset_supports (rps, "zaamo");
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case INSN_CLASS_ZABHA:
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return riscv_subset_supports (rps, "zabha");
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case INSN_CLASS_ZACAS:
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return riscv_subset_supports (rps, "zacas");
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case INSN_CLASS_ZALRSC:
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return riscv_subset_supports (rps, "zalrsc");
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case INSN_CLASS_ZAWRS:
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@ -2785,6 +2789,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
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return "zaamo";
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case INSN_CLASS_ZABHA:
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return "zabha";
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case INSN_CLASS_ZACAS:
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return "zacas";
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case INSN_CLASS_ZALRSC:
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return "zalrsc";
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case INSN_CLASS_ZAWRS:
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2
gas/NEWS
2
gas/NEWS
@ -19,6 +19,8 @@
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* Remove support for RISC-V privileged spec 1.9.1, but linker can still
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recognize it in case of linking old objects.
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* Add support for RISC-V Zacas extension with version 1.0.
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* Add support for RISC-V Zcmp extension with version 1.0.
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* Add support for RISC-V Zfbfmin extension with version 1.0.
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@ -23,6 +23,7 @@ All available -march extensions for RISC-V:
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zmmul 1.0
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zaamo 1.0
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zabha 1.0
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zacas 1.0
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zalrsc 1.0
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zawrs 1.0
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zfbfmin 1.0
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26
gas/testsuite/gas/riscv/zacas-32.d
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26
gas/testsuite/gas/riscv/zacas-32.d
Normal file
@ -0,0 +1,26 @@
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#as: -march=rv32ia_zacas
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#source: zacas.s
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#objdump: -d
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.*:[ ]+file format .*
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Disassembly of section .text:
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0+000 <target>:
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[ ]+[0-9a-f]+:[ ]+28a5252f[ ]+amocas.w[ ]+a0,a0,\(a0\)
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[ ]+[0-9a-f]+:[ ]+28a5252f[ ]+amocas.w[ ]+a0,a0,\(a0\)
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[ ]+[0-9a-f]+:[ ]+2ca5252f[ ]+amocas.w.aq[ ]+a0,a0,\(a0\)
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[ ]+[0-9a-f]+:[ ]+2ca5252f[ ]+amocas.w.aq[ ]+a0,a0,\(a0\)
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[ ]+[0-9a-f]+:[ ]+2aa5252f[ ]+amocas.w.rl[ ]+a0,a0,\(a0\)
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[ ]+[0-9a-f]+:[ ]+2aa5252f[ ]+amocas.w.rl[ ]+a0,a0,\(a0\)
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[ ]+[0-9a-f]+:[ ]+2ea5252f[ ]+amocas.w.aqrl[ ]+a0,a0,\(a0\)
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[ ]+[0-9a-f]+:[ ]+2ea5252f[ ]+amocas.w.aqrl[ ]+a0,a0,\(a0\)
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[ ]+[0-9a-f]+:[ ]+28a5352f[ ]+amocas.d[ ]+a0,a0,\(a0\)
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[ ]+[0-9a-f]+:[ ]+28a5352f[ ]+amocas.d[ ]+a0,a0,\(a0\)
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[ ]+[0-9a-f]+:[ ]+2ca5352f[ ]+amocas.d.aq[ ]+a0,a0,\(a0\)
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[ ]+[0-9a-f]+:[ ]+2ca5352f[ ]+amocas.d.aq[ ]+a0,a0,\(a0\)
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[ ]+[0-9a-f]+:[ ]+2aa5352f[ ]+amocas.d.rl[ ]+a0,a0,\(a0\)
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[ ]+[0-9a-f]+:[ ]+2aa5352f[ ]+amocas.d.rl[ ]+a0,a0,\(a0\)
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[ ]+[0-9a-f]+:[ ]+2ea5352f[ ]+amocas.d.aqrl[ ]+a0,a0,\(a0\)
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[ ]+[0-9a-f]+:[ ]+2ea5352f[ ]+amocas.d.aqrl[ ]+a0,a0,\(a0\)
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34
gas/testsuite/gas/riscv/zacas-64.d
Normal file
34
gas/testsuite/gas/riscv/zacas-64.d
Normal file
@ -0,0 +1,34 @@
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#as: -march=rv64ia_zacas -defsym rv64=1
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#source: zacas.s
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#objdump: -d
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.*:[ ]+file format .*
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Disassembly of section .text:
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0+000 <target>:
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[ ]+[0-9a-f]+:[ ]+28a5252f[ ]+amocas.w[ ]+a0,a0,\(a0\)
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[ ]+[0-9a-f]+:[ ]+28a5252f[ ]+amocas.w[ ]+a0,a0,\(a0\)
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[ ]+[0-9a-f]+:[ ]+2ca5252f[ ]+amocas.w.aq[ ]+a0,a0,\(a0\)
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[ ]+[0-9a-f]+:[ ]+2ca5252f[ ]+amocas.w.aq[ ]+a0,a0,\(a0\)
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[ ]+[0-9a-f]+:[ ]+2aa5252f[ ]+amocas.w.rl[ ]+a0,a0,\(a0\)
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[ ]+[0-9a-f]+:[ ]+2aa5252f[ ]+amocas.w.rl[ ]+a0,a0,\(a0\)
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[ ]+[0-9a-f]+:[ ]+2ea5252f[ ]+amocas.w.aqrl[ ]+a0,a0,\(a0\)
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[ ]+[0-9a-f]+:[ ]+2ea5252f[ ]+amocas.w.aqrl[ ]+a0,a0,\(a0\)
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[ ]+[0-9a-f]+:[ ]+28a5352f[ ]+amocas.d[ ]+a0,a0,\(a0\)
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[ ]+[0-9a-f]+:[ ]+28a5352f[ ]+amocas.d[ ]+a0,a0,\(a0\)
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[ ]+[0-9a-f]+:[ ]+2ca5352f[ ]+amocas.d.aq[ ]+a0,a0,\(a0\)
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[ ]+[0-9a-f]+:[ ]+2ca5352f[ ]+amocas.d.aq[ ]+a0,a0,\(a0\)
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[ ]+[0-9a-f]+:[ ]+2aa5352f[ ]+amocas.d.rl[ ]+a0,a0,\(a0\)
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[ ]+[0-9a-f]+:[ ]+2aa5352f[ ]+amocas.d.rl[ ]+a0,a0,\(a0\)
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[ ]+[0-9a-f]+:[ ]+2ea5352f[ ]+amocas.d.aqrl[ ]+a0,a0,\(a0\)
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[ ]+[0-9a-f]+:[ ]+2ea5352f[ ]+amocas.d.aqrl[ ]+a0,a0,\(a0\)
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[ ]+[0-9a-f]+:[ ]+28a5452f[ ]+amocas.q[ ]+a0,a0,\(a0\)
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[ ]+[0-9a-f]+:[ ]+28a5452f[ ]+amocas.q[ ]+a0,a0,\(a0\)
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[ ]+[0-9a-f]+:[ ]+2ca5452f[ ]+amocas.q.aq[ ]+a0,a0,\(a0\)
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[ ]+[0-9a-f]+:[ ]+2ca5452f[ ]+amocas.q.aq[ ]+a0,a0,\(a0\)
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[ ]+[0-9a-f]+:[ ]+2aa5452f[ ]+amocas.q.rl[ ]+a0,a0,\(a0\)
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[ ]+[0-9a-f]+:[ ]+2aa5452f[ ]+amocas.q.rl[ ]+a0,a0,\(a0\)
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[ ]+[0-9a-f]+:[ ]+2ea5452f[ ]+amocas.q.aqrl[ ]+a0,a0,\(a0\)
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[ ]+[0-9a-f]+:[ ]+2ea5452f[ ]+amocas.q.aqrl[ ]+a0,a0,\(a0\)
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3
gas/testsuite/gas/riscv/zacas-fail-32.d
Normal file
3
gas/testsuite/gas/riscv/zacas-fail-32.d
Normal file
@ -0,0 +1,3 @@
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#as: -march=rv32ia_zacas
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#source: zacas-fail.s
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#error_output: zacas-fail-32.l
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17
gas/testsuite/gas/riscv/zacas-fail-32.l
Normal file
17
gas/testsuite/gas/riscv/zacas-fail-32.l
Normal file
@ -0,0 +1,17 @@
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.*: Assembler messages:
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.*: Error: illegal operands `amocas.d a1,a0,\(a0\)'
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.*: Error: illegal operands `amocas.d a0,a1,\(a0\)'
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.*: Error: illegal operands `amocas.d.aq a1,a0,\(a0\)'
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.*: Error: illegal operands `amocas.d.aq a0,a1,\(a0\)'
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.*: Error: illegal operands `amocas.d.rl a1,a0,\(a0\)'
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.*: Error: illegal operands `amocas.d.rl a0,a1,\(a0\)'
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.*: Error: illegal operands `amocas.d.aqrl a1,a0,\(a0\)'
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.*: Error: illegal operands `amocas.d.aqrl a0,a1,\(a0\)'
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.*: Error: unrecognized opcode `amocas.q a1,a0,\(a0\)'
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.*: Error: unrecognized opcode `amocas.q a0,a1,\(a0\)'
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.*: Error: unrecognized opcode `amocas.q.aq a1,a0,\(a0\)'
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.*: Error: unrecognized opcode `amocas.q.aq a0,a1,\(a0\)'
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.*: Error: unrecognized opcode `amocas.q.rl a1,a0,\(a0\)'
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.*: Error: unrecognized opcode `amocas.q.rl a0,a1,\(a0\)'
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.*: Error: unrecognized opcode `amocas.q.aqrl a1,a0,\(a0\)'
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.*: Error: unrecognized opcode `amocas.q.aqrl a0,a1,\(a0\)'
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3
gas/testsuite/gas/riscv/zacas-fail-64.d
Normal file
3
gas/testsuite/gas/riscv/zacas-fail-64.d
Normal file
@ -0,0 +1,3 @@
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#as: -march=rv64ia_zacas
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#source: zacas-fail.s
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#error_output: zacas-fail-64.l
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9
gas/testsuite/gas/riscv/zacas-fail-64.l
Normal file
9
gas/testsuite/gas/riscv/zacas-fail-64.l
Normal file
@ -0,0 +1,9 @@
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.*: Assembler messages:
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.*: Error: illegal operands `amocas.q a1,a0,\(a0\)'
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.*: Error: illegal operands `amocas.q a0,a1,\(a0\)'
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.*: Error: illegal operands `amocas.q.aq a1,a0,\(a0\)'
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.*: Error: illegal operands `amocas.q.aq a0,a1,\(a0\)'
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.*: Error: illegal operands `amocas.q.rl a1,a0,\(a0\)'
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.*: Error: illegal operands `amocas.q.rl a0,a1,\(a0\)'
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.*: Error: illegal operands `amocas.q.aqrl a1,a0,\(a0\)'
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.*: Error: illegal operands `amocas.q.aqrl a0,a1,\(a0\)'
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17
gas/testsuite/gas/riscv/zacas-fail.s
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17
gas/testsuite/gas/riscv/zacas-fail.s
Normal file
@ -0,0 +1,17 @@
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# rd and rs2 must be even
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amocas.d a1, a0, (a0)
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amocas.d a0, a1, (a0)
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amocas.d.aq a1, a0, (a0)
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amocas.d.aq a0, a1, (a0)
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amocas.d.rl a1, a0, (a0)
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amocas.d.rl a0, a1, (a0)
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amocas.d.aqrl a1, a0, (a0)
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amocas.d.aqrl a0, a1, (a0)
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amocas.q a1, a0, (a0)
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amocas.q a0, a1, (a0)
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amocas.q.aq a1, a0, (a0)
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amocas.q.aq a0, a1, (a0)
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amocas.q.rl a1, a0, (a0)
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amocas.q.rl a0, a1, (a0)
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amocas.q.aqrl a1, a0, (a0)
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amocas.q.aqrl a0, a1, (a0)
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27
gas/testsuite/gas/riscv/zacas.s
Normal file
27
gas/testsuite/gas/riscv/zacas.s
Normal file
@ -0,0 +1,27 @@
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target:
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amocas.w a0, a0, 0(a0)
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amocas.w a0, a0, (a0)
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amocas.w.aq a0, a0, 0(a0)
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amocas.w.aq a0, a0, (a0)
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amocas.w.rl a0, a0, 0(a0)
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amocas.w.rl a0, a0, (a0)
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amocas.w.aqrl a0, a0, 0(a0)
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amocas.w.aqrl a0, a0, (a0)
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amocas.d a0, a0, 0(a0)
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amocas.d a0, a0, (a0)
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amocas.d.aq a0, a0, 0(a0)
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amocas.d.aq a0, a0, (a0)
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amocas.d.rl a0, a0, 0(a0)
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amocas.d.rl a0, a0, (a0)
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amocas.d.aqrl a0, a0, 0(a0)
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amocas.d.aqrl a0, a0, (a0)
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.ifdef rv64
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amocas.q a0, a0, 0(a0)
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amocas.q a0, a0, (a0)
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amocas.q.aq a0, a0, 0(a0)
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amocas.q.aq a0, a0, (a0)
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amocas.q.rl a0, a0, 0(a0)
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amocas.q.rl a0, a0, (a0)
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amocas.q.aqrl a0, a0, 0(a0)
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amocas.q.aqrl a0, a0, (a0)
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.endif
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@ -2360,6 +2360,13 @@
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#define MASK_C_NTL_S1 0xffff
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#define MATCH_C_NTL_ALL 0x9016
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#define MASK_C_NTL_ALL 0xffff
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/* Zacas instructions. */
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#define MATCH_AMOCAS_W 0x2800202f
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#define MASK_AMOCAS_W 0xf800707f
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#define MATCH_AMOCAS_D 0x2800302f
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#define MASK_AMOCAS_D 0xf800707f
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#define MATCH_AMOCAS_Q 0x2800402f
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#define MASK_AMOCAS_Q 0xf800707f
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/* Zawrs instructions. */
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#define MATCH_WRS_NTO 0x00d00073
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#define MASK_WRS_NTO 0xffffffff
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@ -3998,6 +4005,10 @@ DECLARE_INSN(c_ntl_p1, MATCH_C_NTL_P1, MASK_C_NTL_P1)
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DECLARE_INSN(c_ntl_pall, MATCH_C_NTL_PALL, MASK_C_NTL_PALL)
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DECLARE_INSN(c_ntl_s1, MATCH_C_NTL_S1, MASK_C_NTL_S1)
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DECLARE_INSN(c_ntl_all, MATCH_C_NTL_ALL, MASK_C_NTL_ALL)
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/* Zacas instructions. */
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DECLARE_INSN(amocas_w, MATCH_AMOCAS_W, MASK_AMOCAS_W)
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DECLARE_INSN(amocas_d, MATCH_AMOCAS_D, MASK_AMOCAS_D)
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DECLARE_INSN(amocas_q, MATCH_AMOCAS_Q, MASK_AMOCAS_Q)
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/* Zawrs instructions. */
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DECLARE_INSN(wrs_nto, MATCH_WRS_NTO, MASK_WRS_NTO)
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DECLARE_INSN(wrs_sto, MATCH_WRS_STO, MASK_WRS_STO)
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@ -492,6 +492,7 @@ enum riscv_insn_class
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INSN_CLASS_ZICBOP,
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INSN_CLASS_ZICBOZ,
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INSN_CLASS_ZABHA,
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INSN_CLASS_ZACAS,
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INSN_CLASS_H,
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INSN_CLASS_XCVMAC,
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INSN_CLASS_XCVALU,
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@ -197,6 +197,14 @@ match_rs1_eq_rs2 (const struct riscv_opcode *op, insn_t insn)
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return match_opcode (op, insn) && rs1 == rs2;
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}
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static int
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match_rs2_rd_even (const struct riscv_opcode *op, insn_t insn)
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{
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int rs2 = (insn & MASK_RS2) >> OP_SH_RS2;
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int rd = (insn & MASK_RD) >> OP_SH_RD;
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return ((rs2 & 1) == 0) && ((rd & 1) == 0) && match_opcode (op, insn);
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}
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static int
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match_rd_nonzero (const struct riscv_opcode *op, insn_t insn)
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{
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@ -748,6 +756,24 @@ const struct riscv_opcode riscv_opcodes[] =
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{"amomin.h.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMIN_H|MASK_AQRL, MASK_AMOMIN_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE },
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{"amominu.h.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMINU_H|MASK_AQRL, MASK_AMOMINU_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE },
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/* Zacas instruction subset. */
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{"amocas.w", 0, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_AMOCAS_W, MASK_AMOCAS_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
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{"amocas.d", 32, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_AMOCAS_D, MASK_AMOCAS_D|MASK_AQRL, match_rs2_rd_even, INSN_DREF|INSN_8_BYTE },
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{"amocas.d", 64, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_AMOCAS_D, MASK_AMOCAS_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
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{"amocas.q", 64, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_AMOCAS_Q, MASK_AMOCAS_Q|MASK_AQRL, match_rs2_rd_even, INSN_DREF|INSN_16_BYTE },
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{"amocas.w.aq", 0, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_AMOCAS_W|MASK_AQ, MASK_AMOCAS_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
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{"amocas.d.aq", 32, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_AMOCAS_D|MASK_AQ, MASK_AMOCAS_D|MASK_AQRL, match_rs2_rd_even, INSN_DREF|INSN_8_BYTE },
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{"amocas.d.aq", 64, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_AMOCAS_D|MASK_AQ, MASK_AMOCAS_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
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{"amocas.q.aq", 64, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_AMOCAS_Q|MASK_AQ, MASK_AMOCAS_Q|MASK_AQRL, match_rs2_rd_even, INSN_DREF|INSN_16_BYTE },
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{"amocas.w.rl", 0, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_AMOCAS_W|MASK_RL, MASK_AMOCAS_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
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||||
{"amocas.d.rl", 32, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_AMOCAS_D|MASK_RL, MASK_AMOCAS_D|MASK_AQRL, match_rs2_rd_even, INSN_DREF|INSN_8_BYTE },
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||||
{"amocas.d.rl", 64, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_AMOCAS_D|MASK_RL, MASK_AMOCAS_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
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||||
{"amocas.q.rl", 64, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_AMOCAS_Q|MASK_RL, MASK_AMOCAS_Q|MASK_AQRL, match_rs2_rd_even, INSN_DREF|INSN_16_BYTE },
|
||||
{"amocas.w.aqrl", 0, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_AMOCAS_W|MASK_AQRL, MASK_AMOCAS_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
|
||||
{"amocas.d.aqrl", 32, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_AMOCAS_D|MASK_AQRL, MASK_AMOCAS_D|MASK_AQRL, match_rs2_rd_even, INSN_DREF|INSN_8_BYTE },
|
||||
{"amocas.d.aqrl", 64, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_AMOCAS_D|MASK_AQRL, MASK_AMOCAS_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
|
||||
{"amocas.q.aqrl", 64, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_AMOCAS_Q|MASK_AQRL, MASK_AMOCAS_Q|MASK_AQRL, match_rs2_rd_even, INSN_DREF|INSN_16_BYTE },
|
||||
|
||||
/* Multiply/Divide instruction subset. */
|
||||
{"mul", 0, INSN_CLASS_ZCB_AND_ZMMUL, "Cs,Cw,Ct", MATCH_C_MUL, MASK_C_MUL, match_opcode, INSN_ALIAS },
|
||||
{"mul", 0, INSN_CLASS_ZMMUL, "d,s,t", MATCH_MUL, MASK_MUL, match_opcode, 0 },
|
||||
|
||||
Loading…
Reference in New Issue
Block a user