mirror/binutils-gdb
2
0
Fork 0
mirror of https://sourceware.org/git/binutils-gdb.git synced 2024-11-27 03:51:15 +08:00
Code Issues Packages Projects Releases Wiki Activity

New ARC implementation.

Browse Source 
bfd	* archures.c: Remove support for older ARC. Added support for new
	ARC cpus (ARC600, ARC601, ARC700, ARCV2).
	* bfd-in2.h: Likewise.
	* config.bfd: Likewise.
	* cpu-arc.c: Likewise.
	* elf32-arc.c: Totally changed file with a refactored
	inplementation of the ARC port.
	* libbfd.h: Added ARC specific relocation types.
	* reloc.c: Likewise.

gas     * config/tc-arc.c: Revamped file for ARC support.
        * config/tc-arc.h: Likewise.
        * doc/as.texinfo: Add new ARC options.
        * doc/c-arc.texi: Likewise.

ld	* configure.tgt: Added target arc-*-elf* and arc*-*-linux-uclibc*.
	* emulparams/arcebelf_prof.sh: New file
	* emulparams/arcebelf.sh: Likewise.
	* emulparams/arceblinux_prof.sh: Likewise.
	* emulparams/arceblinux.sh: Likewise.
	* emulparams/arcelf_prof.sh: Likewise.
	* emulparams/arcelf.sh: Likewise.
	* emulparams/arclinux_prof.sh: Likewise.
	* emulparams/arclinux.sh: Likewise.
	* emulparams/arcv2elfx.sh: Likewise.
	* emulparams/arcv2elf.sh: Likewise.
	* emultempl/arclinux.em: Likewise.
	* scripttempl/arclinux.sc: Likewise.
	* scripttempl/elfarc.sc: Likewise.
	* scripttempl/elfarcv2.sc: Likewise
	* Makefile.am: Add new ARC emulations.
	* Makefile.in: Regenerate.
	* NEWS: Mention the new feature.

opcodes * arc-dis.c: Revamped file for ARC support
	* arc-dis.h: Likewise.
	* arc-ext.c: Likewise.
	* arc-ext.h: Likewise.
	* arc-opc.c: Likewise.
	* arc-fxi.h: New file.
	* arc-regs.h: Likewise.
	* arc-tbl.h: Likewise.

binutils * readelf.c (get_machine_name): Remove A5 reference. Add ARCompact
	and ARCv2.
	(get_machine_flags): Handle EM_ARCV2 and EM_ARCOMPACT.
	(guess_is_rela): Likewise.
	(dump_relocations): Likewise.
	(is_32bit_abs_reloc): Likewise.
	(is_16bit_abs_reloc): Likewise.
	(is_none_reloc): Likewise.
	* NEWS: Mention the new feature.

include	* dis-asm.h (arc_get_disassembler): Correct declaration.
	* arc-reloc.def: Macro file with definition of all relocation
	types.
	* arc.h: Changed macros for the newly supported ARC cpus.  Altered
	enum defining the supported relocations.
	* common.h: Changed EM_ARC_A5 definition to EM_ARC_COMPACT. Added
	macro for EM_ARC_COMPACT2.
        * arc-func.h: New file.
        * arc.h: Likewise.
This commit is contained in:
Nick Clifton 2015-10-07 14:20:19 +01:00
parent 3b0357dada
commit 886a250647
140 changed files with 31995 additions and 8458 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
bfd/ChangeLog
View File

@ -1,3 +1,15 @@
2015-10-07 Cupertino Miranda <cmiranda@synopsys.com>
* archures.c: Remove support for older ARC. Added support for new
ARC cpus (ARC600, ARC601, ARC700, ARCV2).
* bfd-in2.h: Likewise.
* config.bfd: Likewise.
* cpu-arc.c: Likewise.
* elf32-arc.c: Totally changed file with a refactored
inplementation of the ARC port.
* libbfd.h: Added ARC specific relocation types.
* reloc.c: Likewise.
2015-10-06 H.J. Lu <hongjiu.lu@intel.com>
* bfd.c (bfd_update_compression_header): Clear the ch_reserved

10
bfd/archures.c
View File

@ -353,10 +353,12 @@ DESCRIPTION
.#define bfd_mach_v850e2v3 0x45325633
.#define bfd_mach_v850e3v5 0x45335635 {* ('E'|'3'|'V'|'5') *}
. bfd_arch_arc, {* ARC Cores *}
.#define bfd_mach_arc_5 5
.#define bfd_mach_arc_6 6
.#define bfd_mach_arc_7 7
.#define bfd_mach_arc_8 8
.#define bfd_mach_arc_a4 0
.#define bfd_mach_arc_a5 1
.#define bfd_mach_arc_arc600 2
.#define bfd_mach_arc_arc601 4
.#define bfd_mach_arc_arc700 3
.#define bfd_mach_arc_arcv2 5
. bfd_arch_m32c, {* Renesas M16C/M32C. *}
.#define bfd_mach_m16c 0x75
.#define bfd_mach_m32c 0x78

86
bfd/bfd-in2.h
View File

@ -2148,10 +2148,12 @@ enum bfd_architecture
#define bfd_mach_v850e2v3 0x45325633
#define bfd_mach_v850e3v5 0x45335635 /* ('E'|'3'|'V'|'5') */
bfd_arch_arc, /* ARC Cores */
#define bfd_mach_arc_5 5
#define bfd_mach_arc_6 6
#define bfd_mach_arc_7 7
#define bfd_mach_arc_8 8
#define bfd_mach_arc_a4 0
#define bfd_mach_arc_a5 1
#define bfd_mach_arc_arc600 2
#define bfd_mach_arc_arc601 4
#define bfd_mach_arc_arc700 3
#define bfd_mach_arc_arcv2 5
bfd_arch_m32c, /* Renesas M16C/M32C. */
#define bfd_mach_m16c 0x75
#define bfd_mach_m32c 0x78
@ -3620,16 +3622,72 @@ pc-relative or some form of GOT-indirect relocation. */
BFD_RELOC_SH_GOTOFFFUNCDESC20,
BFD_RELOC_SH_FUNCDESC,
/* ARC Cores relocs.
ARC 22 bit pc-relative branch. The lowest two bits must be zero and are
not stored in the instruction. The high 20 bits are installed in bits 26
through 7 of the instruction. */
BFD_RELOC_ARC_B22_PCREL,
/* ARC 26 bit absolute branch. The lowest two bits must be zero and are not
stored in the instruction. The high 24 bits are installed in bits 23
through 0. */
BFD_RELOC_ARC_B26,
/* ARC relocs. */
BFD_RELOC_ARC_NONE,
BFD_RELOC_ARC_8,
BFD_RELOC_ARC_16,
BFD_RELOC_ARC_24,
BFD_RELOC_ARC_32,
BFD_RELOC_ARC_N8,
BFD_RELOC_ARC_N16,
BFD_RELOC_ARC_N24,
BFD_RELOC_ARC_N32,
BFD_RELOC_ARC_SDA,
BFD_RELOC_ARC_SECTOFF,
BFD_RELOC_ARC_S21H_PCREL,
BFD_RELOC_ARC_S21W_PCREL,
BFD_RELOC_ARC_S25H_PCREL,
BFD_RELOC_ARC_S25W_PCREL,
BFD_RELOC_ARC_SDA32,
BFD_RELOC_ARC_SDA_LDST,
BFD_RELOC_ARC_SDA_LDST1,
BFD_RELOC_ARC_SDA_LDST2,
BFD_RELOC_ARC_SDA16_LD,
BFD_RELOC_ARC_SDA16_LD1,
BFD_RELOC_ARC_SDA16_LD2,
BFD_RELOC_ARC_S13_PCREL,
BFD_RELOC_ARC_W,
BFD_RELOC_ARC_32_ME,
BFD_RELOC_ARC_32_ME_S,
BFD_RELOC_ARC_N32_ME,
BFD_RELOC_ARC_SECTOFF_ME,
BFD_RELOC_ARC_SDA32_ME,
BFD_RELOC_ARC_W_ME,
BFD_RELOC_AC_SECTOFF_U8,
BFD_RELOC_AC_SECTOFF_U8_1,
BFD_RELOC_AC_SECTOFF_U8_2,
BFD_RELOC_AC_SECTFOFF_S9,
BFD_RELOC_AC_SECTFOFF_S9_1,
BFD_RELOC_AC_SECTFOFF_S9_2,
BFD_RELOC_ARC_SECTOFF_ME_1,
BFD_RELOC_ARC_SECTOFF_ME_2,
BFD_RELOC_ARC_SECTOFF_1,
BFD_RELOC_ARC_SECTOFF_2,
BFD_RELOC_ARC_SDA16_ST2,
BFD_RELOC_ARC_PC32,
BFD_RELOC_ARC_GOT32,
BFD_RELOC_ARC_GOTPC32,
BFD_RELOC_ARC_PLT32,
BFD_RELOC_ARC_COPY,
BFD_RELOC_ARC_GLOB_DAT,
BFD_RELOC_ARC_JMP_SLOT,
BFD_RELOC_ARC_RELATIVE,
BFD_RELOC_ARC_GOTOFF,
BFD_RELOC_ARC_GOTPC,
BFD_RELOC_ARC_S21W_PCREL_PLT,
BFD_RELOC_ARC_S25H_PCREL_PLT,
BFD_RELOC_ARC_TLS_DTPMOD,
BFD_RELOC_ARC_TLS_TPOFF,
BFD_RELOC_ARC_TLS_GD_GOT,
BFD_RELOC_ARC_TLS_GD_LD,
BFD_RELOC_ARC_TLS_GD_CALL,
BFD_RELOC_ARC_TLS_IE_GOT,
BFD_RELOC_ARC_TLS_DTPOFF,
BFD_RELOC_ARC_TLS_DTPOFF_S9,
BFD_RELOC_ARC_TLS_LE_S9,
BFD_RELOC_ARC_TLS_LE_32,
BFD_RELOC_ARC_S25W_PCREL_PLT,
BFD_RELOC_ARC_S21H_PCREL_PLT,
/* ADI Blackfin 16 bit immediate absolute reloc. */
BFD_RELOC_BFIN_16_IMM,

3
bfd/config.bfd
View File

@ -93,6 +93,7 @@ case "${targ_cpu}" in
aarch64*) targ_archs="bfd_aarch64_arch bfd_arm_arch";;
alpha*) targ_archs=bfd_alpha_arch ;;
am34*|am33_2.0*) targ_archs=bfd_mn10300_arch ;;
arc*) targ_archs=bfd_arc_arch ;;
arm*) targ_archs=bfd_arm_arch ;;
bfin*) targ_archs=bfd_bfin_arch ;;
c30*) targ_archs=bfd_tic30_arch ;;
@ -262,7 +263,7 @@ case "${targ}" in
targ_defvec=am33_elf32_linux_vec
;;
arc-*-elf*)
arc*-*-elf* | arc*-*-linux-uclibc*)
targ_defvec=arc_elf32_le_vec
targ_selvecs=arc_elf32_be_vec
;;

18
bfd/cpu-arc.c
View File

@ -42,22 +42,24 @@
static const bfd_arch_info_type arch_info_struct[] =
{
ARC ( bfd_mach_arc_5, "arc5", FALSE, &arch_info_struct[1] ),
ARC ( bfd_mach_arc_5, "base", FALSE, &arch_info_struct[2] ),
ARC ( bfd_mach_arc_6, "arc6", FALSE, &arch_info_struct[3] ),
ARC ( bfd_mach_arc_7, "arc7", FALSE, &arch_info_struct[4] ),
ARC ( bfd_mach_arc_8, "arc8", FALSE, NULL ),
ARC (bfd_mach_arc_arc600, "ARC600", FALSE, &arch_info_struct[1]),
ARC (bfd_mach_arc_arc600, "A6" , FALSE, &arch_info_struct[2]),
ARC (bfd_mach_arc_arc601, "ARC601", FALSE, &arch_info_struct[3]),
ARC (bfd_mach_arc_arc700, "ARC700", FALSE, &arch_info_struct[4]),
ARC (bfd_mach_arc_arc700, "A7", FALSE, &arch_info_struct[5]),
ARC (bfd_mach_arc_arcv2, "ARCv2", FALSE, &arch_info_struct[6]),
ARC (bfd_mach_arc_arcv2, "EM", FALSE, &arch_info_struct[7]),
ARC (bfd_mach_arc_arcv2, "HS", FALSE, NULL),
};
const bfd_arch_info_type bfd_arc_arch =
ARC ( bfd_mach_arc_6, "arc", TRUE, &arch_info_struct[0] );
ARC (bfd_mach_arc_arcv2, "HS", TRUE, &arch_info_struct[0]);
/* Utility routines. */
/* Given cpu type NAME, return its bfd_mach_arc_xxx value.
Returns -1 if not found. */
int arc_get_mach (char *);
int arc_get_mach (char *name);
int
arc_get_mach (char *name)

1728
bfd/elf32-arc.c
View File

File diff suppressed because it is too large Load Diff

6
bfd/elfxx-sparc.c
View File

@ -3468,9 +3468,9 @@ _bfd_sparc_elf_relocate_section (bfd *output_bfd,
memset (&outrel, 0, sizeof outrel);
/* h->dynindx may be -1 if the symbol was marked to
become local. */
else if (h != NULL &&
h->dynindx != -1
&& (! is_plt
else if (h != NULL
&& h->dynindx != -1
&& (_bfd_sparc_elf_howto_table[r_type].pc_relative
|| !bfd_link_pic (info)
|| !SYMBOLIC_BIND (info, h)
|| !h->def_regular))

67
bfd/libbfd.h
View File

@ -1663,8 +1663,71 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
"BFD_RELOC_SH_GOTOFFFUNCDESC",
"BFD_RELOC_SH_GOTOFFFUNCDESC20",
"BFD_RELOC_SH_FUNCDESC",
"BFD_RELOC_ARC_B22_PCREL",
"BFD_RELOC_ARC_B26",
"BFD_RELOC_ARC_NONE",
"BFD_RELOC_ARC_8",
"BFD_RELOC_ARC_16",
"BFD_RELOC_ARC_24",
"BFD_RELOC_ARC_32",
"BFD_RELOC_ARC_N8",
"BFD_RELOC_ARC_N16",
"BFD_RELOC_ARC_N24",
"BFD_RELOC_ARC_N32",
"BFD_RELOC_ARC_SDA",
"BFD_RELOC_ARC_SECTOFF",
"BFD_RELOC_ARC_S21H_PCREL",
"BFD_RELOC_ARC_S21W_PCREL",
"BFD_RELOC_ARC_S25H_PCREL",
"BFD_RELOC_ARC_S25W_PCREL",
"BFD_RELOC_ARC_SDA32",
"BFD_RELOC_ARC_SDA_LDST",
"BFD_RELOC_ARC_SDA_LDST1",
"BFD_RELOC_ARC_SDA_LDST2",
"BFD_RELOC_ARC_SDA16_LD",
"BFD_RELOC_ARC_SDA16_LD1",
"BFD_RELOC_ARC_SDA16_LD2",
"BFD_RELOC_ARC_S13_PCREL",
"BFD_RELOC_ARC_W",
"BFD_RELOC_ARC_32_ME",
"BFD_RELOC_ARC_32_ME_S",
"BFD_RELOC_ARC_N32_ME",
"BFD_RELOC_ARC_SECTOFF_ME",
"BFD_RELOC_ARC_SDA32_ME",
"BFD_RELOC_ARC_W_ME",
"BFD_RELOC_AC_SECTOFF_U8",
"BFD_RELOC_AC_SECTOFF_U8_1",
"BFD_RELOC_AC_SECTOFF_U8_2",
"BFD_RELOC_AC_SECTFOFF_S9",
"BFD_RELOC_AC_SECTFOFF_S9_1",
"BFD_RELOC_AC_SECTFOFF_S9_2",
"BFD_RELOC_ARC_SECTOFF_ME_1",
"BFD_RELOC_ARC_SECTOFF_ME_2",
"BFD_RELOC_ARC_SECTOFF_1",
"BFD_RELOC_ARC_SECTOFF_2",
"BFD_RELOC_ARC_SDA16_ST2",
"BFD_RELOC_ARC_PC32",
"BFD_RELOC_ARC_GOT32",
"BFD_RELOC_ARC_GOTPC32",
"BFD_RELOC_ARC_PLT32",
"BFD_RELOC_ARC_COPY",
"BFD_RELOC_ARC_GLOB_DAT",
"BFD_RELOC_ARC_JMP_SLOT",
"BFD_RELOC_ARC_RELATIVE",
"BFD_RELOC_ARC_GOTOFF",
"BFD_RELOC_ARC_GOTPC",
"BFD_RELOC_ARC_S21W_PCREL_PLT",
"BFD_RELOC_ARC_S25H_PCREL_PLT",
"BFD_RELOC_ARC_TLS_DTPMOD",
"BFD_RELOC_ARC_TLS_TPOFF",
"BFD_RELOC_ARC_TLS_GD_GOT",
"BFD_RELOC_ARC_TLS_GD_LD",
"BFD_RELOC_ARC_TLS_GD_CALL",
"BFD_RELOC_ARC_TLS_IE_GOT",
"BFD_RELOC_ARC_TLS_DTPOFF",
"BFD_RELOC_ARC_TLS_DTPOFF_S9",
"BFD_RELOC_ARC_TLS_LE_S9",
"BFD_RELOC_ARC_TLS_LE_32",
"BFD_RELOC_ARC_S25W_PCREL_PLT",
"BFD_RELOC_ARC_S21H_PCREL_PLT",
"BFD_RELOC_BFIN_16_IMM",
"BFD_RELOC_BFIN_16_HIGH",
"BFD_RELOC_BFIN_4_PCREL",

141
bfd/reloc.c
View File

@ -3515,18 +3515,137 @@ ENUMDOC
Renesas / SuperH SH relocs. Not all of these appear in object files.
ENUM
BFD_RELOC_ARC_B22_PCREL
BFD_RELOC_ARC_NONE
ENUMX
BFD_RELOC_ARC_8
ENUMX
BFD_RELOC_ARC_16
ENUMX
BFD_RELOC_ARC_24
ENUMX
BFD_RELOC_ARC_32
ENUMX
BFD_RELOC_ARC_N8
ENUMX
BFD_RELOC_ARC_N16
ENUMX
BFD_RELOC_ARC_N24
ENUMX
BFD_RELOC_ARC_N32
ENUMX
BFD_RELOC_ARC_SDA
ENUMX
BFD_RELOC_ARC_SECTOFF
ENUMX
BFD_RELOC_ARC_S21H_PCREL
ENUMX
BFD_RELOC_ARC_S21W_PCREL
ENUMX
BFD_RELOC_ARC_S25H_PCREL
ENUMX
BFD_RELOC_ARC_S25W_PCREL
ENUMX
BFD_RELOC_ARC_SDA32
ENUMX
BFD_RELOC_ARC_SDA_LDST
ENUMX
BFD_RELOC_ARC_SDA_LDST1
ENUMX
BFD_RELOC_ARC_SDA_LDST2
ENUMX
BFD_RELOC_ARC_SDA16_LD
ENUMX
BFD_RELOC_ARC_SDA16_LD1
ENUMX
BFD_RELOC_ARC_SDA16_LD2
ENUMX
BFD_RELOC_ARC_S13_PCREL
ENUMX
BFD_RELOC_ARC_W
ENUMX
BFD_RELOC_ARC_32_ME
ENUMX
BFD_RELOC_ARC_32_ME_S
ENUMX
BFD_RELOC_ARC_N32_ME
ENUMX
BFD_RELOC_ARC_SECTOFF_ME
ENUMX
BFD_RELOC_ARC_SDA32_ME
ENUMX
BFD_RELOC_ARC_W_ME
ENUMX
BFD_RELOC_AC_SECTOFF_U8
ENUMX
BFD_RELOC_AC_SECTOFF_U8_1
ENUMX
BFD_RELOC_AC_SECTOFF_U8_2
ENUMX
BFD_RELOC_AC_SECTFOFF_S9
ENUMX
BFD_RELOC_AC_SECTFOFF_S9_1
ENUMX
BFD_RELOC_AC_SECTFOFF_S9_2
ENUMX
BFD_RELOC_ARC_SECTOFF_ME_1
ENUMX
BFD_RELOC_ARC_SECTOFF_ME_2
ENUMX
BFD_RELOC_ARC_SECTOFF_1
ENUMX
BFD_RELOC_ARC_SECTOFF_2
ENUMX
BFD_RELOC_ARC_SDA16_ST2
ENUMX
BFD_RELOC_ARC_PC32
ENUMX
BFD_RELOC_ARC_GOT32
ENUMX
BFD_RELOC_ARC_GOTPC32
ENUMX
BFD_RELOC_ARC_PLT32
ENUMX
BFD_RELOC_ARC_COPY
ENUMX
BFD_RELOC_ARC_GLOB_DAT
ENUMX
BFD_RELOC_ARC_JMP_SLOT
ENUMX
BFD_RELOC_ARC_RELATIVE
ENUMX
BFD_RELOC_ARC_GOTOFF
ENUMX
BFD_RELOC_ARC_GOTPC
ENUMX
BFD_RELOC_ARC_S21W_PCREL_PLT
ENUMX
BFD_RELOC_ARC_S25H_PCREL_PLT
ENUMX
BFD_RELOC_ARC_TLS_DTPMOD
ENUMX
BFD_RELOC_ARC_TLS_TPOFF
ENUMX
BFD_RELOC_ARC_TLS_GD_GOT
ENUMX
BFD_RELOC_ARC_TLS_GD_LD
ENUMX
BFD_RELOC_ARC_TLS_GD_CALL
ENUMX
BFD_RELOC_ARC_TLS_IE_GOT
ENUMX
BFD_RELOC_ARC_TLS_DTPOFF
ENUMX
BFD_RELOC_ARC_TLS_DTPOFF_S9
ENUMX
BFD_RELOC_ARC_TLS_LE_S9
ENUMX
BFD_RELOC_ARC_TLS_LE_32
ENUMX
BFD_RELOC_ARC_S25W_PCREL_PLT
ENUMX
BFD_RELOC_ARC_S21H_PCREL_PLT
ENUMDOC
ARC Cores relocs.
ARC 22 bit pc-relative branch. The lowest two bits must be zero and are
not stored in the instruction. The high 20 bits are installed in bits 26
through 7 of the instruction.
ENUM
BFD_RELOC_ARC_B26
ENUMDOC
ARC 26 bit absolute branch. The lowest two bits must be zero and are not
stored in the instruction. The high 24 bits are installed in bits 23
through 0.
ARC relocs.
ENUM
BFD_RELOC_BFIN_16_IMM

13
binutils/ChangeLog
View File

@ -1,3 +1,16 @@
2015-09-01 Claudiu Zissulescu <claziss@synopsys.com>
Cupertino Miranda <cmiranda@synopsys.com>
* readelf.c (get_machine_name): Remove A5 reference. Add ARCompact
and ARCv2.
(get_machine_flags): Handle EM_ARCV2 and EM_ARCOMPACT.
(guess_is_rela): Likewise.
(dump_relocations): Likewise.
(is_32bit_abs_reloc): Likewise.
(is_16bit_abs_reloc): Likewise.
(is_none_reloc): Likewise.
* NEWS: Mention the new feature.
2015-09-29 Andrew Stubbs <ams@codesourcery.com>
H.J. Lu <hongjiu.lu@intel.com>

2
binutils/NEWS
View File

@ -1,5 +1,7 @@
-*- text -*-
* Add support for the ARC EM/HS, and ARC600/700 architectures.
* Extend objcopy --compress-debug-sections option to support
--compress-debug-sections=[none|zlib|zlib-gnu|zlib-gabi] for ELF
targets.

75
binutils/readelf.c
View File

@ -728,6 +728,9 @@ guess_is_rela (unsigned int e_machine)
case EM_ADAPTEVA_EPIPHANY:
case EM_ALPHA:
case EM_ALTERA_NIOS2:
case EM_ARC:
case EM_ARC_COMPACT:
case EM_ARC_COMPACT2:
case EM_AVR:
case EM_AVR_OLD:
case EM_BLACKFIN:
@ -1315,6 +1318,8 @@ dump_relocations (FILE * file,
break;
case EM_ARC:
case EM_ARC_COMPACT:
case EM_ARC_COMPACT2:
rtype = elf_arc_reloc_type (type);
break;
@ -2115,6 +2120,8 @@ get_machine_name (unsigned e_machine)
case EM_SPARCV9: return "Sparc v9";
case EM_TRICORE: return "Siemens Tricore";
case EM_ARC: return "ARC";
case EM_ARC_COMPACT: return "ARCompact";
case EM_ARC_COMPACT2: return "ARCv2";
case EM_H8_300: return "Renesas H8/300";
case EM_H8_300H: return "Renesas H8/300H";
case EM_H8S: return "Renesas H8S";
@ -2182,7 +2189,6 @@ get_machine_name (unsigned e_machine)
case EM_SCORE: return "SUNPLUS S+Core";
case EM_XSTORMY16: return "Sanyo XStormy16 CPU core";
case EM_OR1K: return "OpenRISC 1000";
case EM_ARC_A5: return "ARC International ARCompact processor";
case EM_CRX: return "National Semiconductor CRX microprocessor";
case EM_ADAPTEVA_EPIPHANY: return "Adapteva EPIPHANY";
case EM_DLX: return "OpenDLX";
@ -2761,6 +2767,63 @@ get_machine_flags (unsigned e_flags, unsigned e_machine)
default:
break;
case EM_ARC_COMPACT2:
switch (e_flags & EF_ARC_MACH_MSK)
{
case EF_ARC_CPU_ARCV2EM:
strcat (buf, ", ARC EM");
break;
case EF_ARC_CPU_ARCV2HS:
strcat (buf, ", ARC HS");
break;
default:
strcat (buf, ", unrecognized flag for ARCv2");
break;
}
switch (e_flags & EF_ARC_OSABI_MSK)
{
/* Only upstream 3.9+ kernels will support ARCv2
ISA. */
case E_ARC_OSABI_V3:
strcat (buf, ", v3 no-legacy-syscalls ABI");
break;
}
break;
case EM_ARC_COMPACT:
switch (e_flags & EF_ARC_MACH_MSK)
{
case E_ARC_MACH_ARC600:
strcat (buf, ", ARC 600");
break;
case E_ARC_MACH_ARC601:
strcat (buf, ", ARC 601");
break;
case E_ARC_MACH_ARC700:
strcat (buf, ", ARC 700");
break;
default:
strcat (buf, ", Generic ARCompact");
break;
}
switch (e_flags & EF_ARC_OSABI_MSK)
{
case E_ARC_OSABI_ORIG:
strcat (buf, ", legacy syscall ABI");
break;
case E_ARC_OSABI_V2:
/* For 3.2+ Linux kernels which use asm-generic
hdrs. */
strcat (buf, ", v2 syscall ABI");
break;
case E_ARC_OSABI_V3:
/* Upstream 3.9+ kernels which don't use any legacy
syscalls. */
strcat (buf, ", v3 no-legacy-syscalls ABI");
break;
}
break;
case EM_ARM:
decode_ARM_machine_flags (e_flags, buf);
break;
@ -11302,6 +11365,9 @@ is_32bit_abs_reloc (unsigned int reloc_type)
return reloc_type == 1; /* R_ALPHA_REFLONG. */
case EM_ARC:
return reloc_type == 1; /* R_ARC_32. */
case EM_ARC_COMPACT:
case EM_ARC_COMPACT2:
return reloc_type == 4; /* R_ARC_32. */
case EM_ARM:
return reloc_type == 2; /* R_ARM_ABS32 */
case EM_AVR_OLD:
@ -11620,6 +11686,10 @@ is_16bit_abs_reloc (unsigned int reloc_type)
{
switch (elf_header.e_machine)
{
case EM_ARC:
case EM_ARC_COMPACT:
case EM_ARC_COMPACT2:
return reloc_type == 2; /* R_ARC_16. */
case EM_AVR_OLD:
case EM_AVR:
return reloc_type == 4; /* R_AVR_16. */
@ -11690,6 +11760,9 @@ is_none_reloc (unsigned int reloc_type)
case EM_ADAPTEVA_EPIPHANY:
case EM_PPC: /* R_PPC_NONE. */
case EM_PPC64: /* R_PPC64_NONE. */
case EM_ARC: /* R_ARC_NONE. */
case EM_ARC_COMPACT: /* R_ARC_NONE. */
case EM_ARC_COMPACT2: /* R_ARC_NONE. */
case EM_ARM: /* R_ARM_NONE. */
case EM_IA_64: /* R_IA64_NONE. */
case EM_SH: /* R_SH_NONE. */

2
binutils/testsuite/binutils-all/objdump.exp
View File

@ -34,7 +34,7 @@ send_user "Version [binutil_version $OBJDUMP]"
set got [binutils_run $OBJDUMP "$OBJDUMPFLAGS -i"]
set cpus_expected [list]
lappend cpus_expected aarch64 alpha arc arm cris
lappend cpus_expected aarch64 alpha arc HS arm cris
lappend cpus_expected d10v d30v fr30 fr500 fr550 h8 hppa i386 i860 i960 iamcu ip2022
lappend cpus_expected m16c m32c m32r m68hc11 m68hc12 m68k m88k MCore mep c5 h1 MicroBlaze
lappend cpus_expected mips mn10200 mn10300 ms1 msp MSP430 nds32 n1h_v3 ns32k

7
gas/ChangeLog
View File

@ -1,3 +1,10 @@
2015-10-07 Claudiu Zissulescu <claziss@synopsys.com>
* config/tc-arc.c: Revamped file for ARC support.
* config/tc-arc.h: Likewise.
* doc/as.texinfo: Add new ARC options.
* doc/c-arc.texi: Likewise.
2015-10-02 Renlin Li <renlin.li@arm.com>
* config/tc-aarch64.c (s_tlsdescadd): New.

3
gas/NEWS
View File

@ -1,5 +1,8 @@
-*- text -*-
* Add support for the ARC EM/HS, and ARC600/700 architectures. Remove
assembler support for Argonaut RISC architectures.
Changes in 2.26:
* Symbol and label names can now be enclosed in double quotes (") which allows

4672
gas/config/tc-arc.c
View File

File diff suppressed because it is too large Load Diff

171
gas/config/tc-arc.h
View File

@ -1,6 +1,7 @@
/* tc-arc.h - Macros and type defines for the ARC.
Copyright (C) 1994-2015 Free Software Foundation, Inc.
Contributed by Doug Evans (dje@cygnus.com).
Copyright 2014 Free Software Foundation, Inc.
Contributed by Claudiu Zissulescu (claziss@synopsys.com)
This file is part of GAS, the GNU Assembler.
@ -19,56 +20,170 @@
Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
02110-1301, USA. */
#define TC_ARC 1
#define TARGET_BYTES_BIG_ENDIAN 0
/* By convention, you should define this macro in the `.h' file. For
example, `tc-m68k.h' defines `TC_M68K'. You might have to use this
if it is necessary to add CPU specific code to the object format
file. */
#define TC_ARC
/* We want local label support. */
#define LOCAL_LABELS_FB 1
/* This macro is the BFD architecture to pass to
`bfd_set_arch_mach'. */
#define TARGET_ARCH bfd_arch_arc
/* The `extsym - .' expressions can be emitted using PC-relative
relocs. */
#define DIFF_EXPR_OK
#define REGISTER_PREFIX '%'
#ifdef LITTLE_ENDIAN
#undef LITTLE_ENDIAN
#endif
#ifdef BIG_ENDIAN
#undef BIG_ENDIAN
#endif
#undef LITTLE_ENDIAN
#define LITTLE_ENDIAN 1234
#undef BIG_ENDIAN
#define BIG_ENDIAN 4321
#ifdef TARGET_BYTES_BIG_ENDIAN
# define DEFAULT_TARGET_FORMAT "elf32-bigarc"
# define DEFAULT_BYTE_ORDER BIG_ENDIAN
#else
/* You should define this macro to be non-zero if the target is big
endian, and zero if the target is little endian. */
# define TARGET_BYTES_BIG_ENDIAN 0
# define DEFAULT_TARGET_FORMAT "elf32-littlearc"
# define DEFAULT_BYTE_ORDER LITTLE_ENDIAN
#endif /* TARGET_BYTES_BIG_ENDIAN. */
/* The endianness of the target format may change based on command
line arguments. */
extern const char * arc_target_format;
extern const char *arc_target_format;
#define DEFAULT_TARGET_FORMAT "elf32-littlearc"
#define TARGET_FORMAT arc_target_format
#define DEFAULT_BYTE_ORDER LITTLE_ENDIAN
/* This macro is the BFD target name to use when creating the output
file. This will normally depend upon the `OBJ_FMT' macro. */
#define TARGET_FORMAT arc_target_format
/* `md_short_jump_size'
`md_long_jump_size'
`md_create_short_jump'
`md_create_long_jump'
If `WORKING_DOT_WORD' is defined, GAS will not do broken word
processing (*note Broken words::.). Otherwise, you should set
`md_short_jump_size' to the size of a short jump (a jump that is
just long enough to jump around a long jmp) and `md_long_jump_size'
to the size of a long jump (a jump that can go anywhere in the
function). You should define `md_create_short_jump' to create a
short jump around a long jump, and define `md_create_long_jump' to
create a long jump. */
#define WORKING_DOT_WORD
#define LISTING_HEADER "ARC GAS "
/* The ARC needs to parse reloc specifiers in .word. */
#define LISTING_HEADER "ARC GAS "
extern bfd_reloc_code_real_type arc_parse_cons_expression (struct expressionS *,
unsigned);
#define TC_PARSE_CONS_EXPRESSION(EXP, NBYTES) \
arc_parse_cons_expression (EXP, NBYTES)
/* The number of bytes to put into a word in a listing. This affects
the way the bytes are clumped together in the listing. For
example, a value of 2 might print `1234 5678' where a value of 1
would print `12 34 56 78'. The default value is 4. */
#define LISTING_WORD_SIZE 2
extern void arc_cons_fix_new (struct frag *, int, int, struct expressionS *,
bfd_reloc_code_real_type);
#define TC_CONS_FIX_NEW(FRAG, WHERE, NBYTES, EXP, RELOC) \
arc_cons_fix_new (FRAG, WHERE, NBYTES, EXP, RELOC)
/* If you define this macro, it should return the position from which
the PC relative adjustment for a PC relative fixup should be made.
On many processors, the base of a PC relative instruction is the
next instruction, so this macro would return the length of an
instruction, plus the address of the PC relative fixup. The latter
can be calculated as fixp->fx_where +
fixp->fx_frag->fr_address. */
extern long md_pcrel_from_section (struct fix *, segT);
#define MD_PCREL_FROM_SECTION(FIX, SEC) md_pcrel_from_section (FIX, SEC)
#define DWARF2_LINE_MIN_INSN_LENGTH 4
/* [ ] is index operator. */
#define NEED_INDEX_OPERATOR
/* Values passed to md_apply_fix don't include the symbol value. */
#define MAX_MEM_FOR_RS_ALIGN_CODE (1+2)
/* HANDLE_ALIGN called after all the assembly has been done,
so we can fill in all the rs_align_code type frags with
nop instructions. */
#define HANDLE_ALIGN(FRAGP) arc_handle_align (FRAGP)
/* Values passed to md_apply_fix3 don't include the symbol value. */
#define MD_APPLY_SYM_VALUE(FIX) 0
/* No shared lib support, so we don't need to ensure externally
visible symbols can be overridden. */
#define EXTERN_FORCE_RELOC 0
/* You may define this macro to generate a fixup for a data allocation
pseudo-op. */
#define TC_CONS_FIX_NEW(FRAG, OFF, LEN, EXP, RELOC) \
arc_cons_fix_new ((FRAG), (OFF), (LEN), (EXP), (RELOC))
/* We don't want gas to fixup the following program memory related
relocations. */
#define TC_VALIDATE_FIX(FIXP,SEG,SKIP) \
if ((FIXP->fx_r_type == BFD_RELOC_ARC_GOTPC32) \
&& FIXP->fx_addsy != NULL \
&& FIXP->fx_subsy == NULL) \
{ \
symbol_mark_used_in_reloc (FIXP->fx_addsy); \
goto SKIP; \
}
/* BFD_RELOC_ARC_TLS_GD_LD may use fx_subsy to store a label that is
later turned into fx_offset. */
#define TC_FORCE_RELOCATION_SUB_LOCAL(FIX, SEG) \
((FIX)->fx_r_type == BFD_RELOC_ARC_TLS_GD_LD)
#define TC_VALIDATE_FIX_SUB(FIX, SEG) \
((md_register_arithmetic || (SEG) != reg_section) \
&& ((FIX)->fx_r_type == BFD_RELOC_GPREL32 \
|| (FIX)->fx_r_type == BFD_RELOC_GPREL16 \
|| (FIX)->fx_r_type == BFD_RELOC_ARC_TLS_DTPOFF \
|| (FIX)->fx_r_type == BFD_RELOC_ARC_TLS_DTPOFF_S9 \
|| TC_FORCE_RELOCATION_SUB_LOCAL (FIX, SEG)))
/* We use this to mark the end-loop label. We use this mark for ZOL
validity checks. */
#define TC_SYMFIELD_TYPE unsigned int
#define ARC_GET_FLAG(s) (*symbol_get_tc (s))
#define ARC_SET_FLAG(s,v) (*symbol_get_tc (s) |= (v))
/* The symbol is a ZOL's end loop label. */
#define ARC_FLAG_ZOL (1 << 0)
/* We use this hook to check the validity of the last to instructions
of a ZOL. */
#define tc_frob_label(S) arc_frob_label (S)
#define GLOBAL_OFFSET_TABLE_NAME "_GLOBAL_OFFSET_TABLE_"
#define DYNAMIC_STRUCT_NAME "_DYNAMIC"
/* We need to take care of not having section relative fixups for the
fixups with respect to Position Independent Code. */
#define tc_fix_adjustable(FIX) tc_arc_fix_adjustable(FIX)
/* This hook is required to parse register names as operands. */
#define md_parse_name(name, exp, m, c) arc_parse_name (name, exp)
extern bfd_boolean arc_parse_name (const char *, struct expressionS *);
extern int tc_arc_fix_adjustable (struct fix *);
extern void arc_handle_align (fragS *);
extern void arc_cons_fix_new (fragS *, int, int, expressionS *,
bfd_reloc_code_real_type);
extern void arc_frob_label (symbolS *);
/* The blink register is r31. */
#define DWARF2_DEFAULT_RETURN_COLUMN 31
/* Registers are generally saved at negative offsets to the CFA. */
#define DWARF2_CIE_DATA_ALIGNMENT (-4)
/* Define the NOPs. */
#define NOP_OPCODE_S 0x000078E0
#define NOP_OPCODE_L 0x264A7000 /* mov 0,0. */

10
gas/configure.tgt
View File

@ -6,12 +6,12 @@
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3 of the License, or
# (at your option) any later version.
#
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
#
# You should have received a copy of the GNU General Public License
# along with this program; see the file COPYING3. If not see
# <http://www.gnu.org/licenses/>.
@ -50,6 +50,7 @@ case ${cpu} in
aarch64_be) cpu_type=aarch64 endian=big ;;
alpha*) cpu_type=alpha ;;
am33_2.0) cpu_type=mn10300 endian=little ;;
arc*eb) cpu_type=arc endian=big ;;
arm*be|arm*b) cpu_type=arm endian=big ;;
arm*) cpu_type=arm endian=little ;;
bfin*) cpu_type=bfin endian=little ;;
@ -130,6 +131,7 @@ case ${generic_target} in
alpha-*-openbsd*) fmt=elf em=obsd ;;
arc-*-elf*) fmt=elf ;;
arc*-*-linux-uclibc*) fmt=elf bfd_gas=yes ;;
arm-*-aout) fmt=aout ;;
arm-*-coff) fmt=coff ;;
@ -352,7 +354,7 @@ case ${generic_target} in
moxie-*-uclinux) fmt=elf em=linux ;;
moxie-*-moxiebox*) fmt=elf endian=little ;;
moxie-*-*) fmt=elf ;;
mt-*-elf) fmt=elf bfd_gas=yes ;;
msp430-*-*) fmt=elf ;;
@ -461,7 +463,7 @@ case ${generic_target} in
visium-*-elf) fmt=elf ;;
xstormy16-*-*) fmt=elf ;;
xgate-*-*) fmt=elf ;;
xtensa*-*-*) fmt=elf ;;

12
gas/doc/as.texinfo
View File

@ -265,7 +265,9 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
@ifset ARC
@emph{Target ARC options:}
[@b{-marc[5|6|7|8]}]
[@b{-mcpu=@var{cpu}}]
[@b{-mA6}|@b{-mARC600}|@b{-mARC601}|@b{-mA7}|@b{-mARC700}|@b{-mEM}|@b{-mHS}]
[@b{-mcode-density}]
[@b{-EB}|@b{-EL}]
@end ifset
@ifset ARM
@ -860,14 +862,16 @@ processor.
@c man begin OPTIONS
@ifset ARC
The following options are available when @value{AS} is configured for
an ARC processor.
The following options are available when @value{AS} is configured for an ARC
processor.
@table @gcctabopt
@item -marc[5|6|7|8]
@item -mcpu=@var{cpu}
This option selects the core processor variant.
@item -EB | -EL
Select either big-endian (-EB) or little-endian (-EL) output.
@item -mcode-density
Enable Code Density extenssion instructions.
@end table
@end ifset

539
gas/doc/c-arc.texi
View File

@ -19,52 +19,54 @@
@menu
* ARC Options:: Options
* ARC Syntax:: Syntax
* ARC Floating Point:: Floating Point
* ARC Directives:: ARC Machine Directives
* ARC Modifiers:: ARC Assembler Modifiers
* ARC Symbols:: ARC Pre-defined Symbols
* ARC Opcodes:: Opcodes
@end menu
@node ARC Options
@section Options
@cindex ARC options (none)
@cindex options for ARC (none)
@cindex ARC options
@cindex options for ARC
The following options control the type of CPU for which code is
assembled, and generic constraints on the code generated:
@table @code
@cindex @code{-marc[5|6|7|8]} command line option, ARC
@item -marc[5|6|7|8]
This option selects the core processor variant. Using
@code{-marc} is the same as @code{-marc@value{ARC_CORE_DEFAULT}}, which
is also the default.
@item -mcpu=@var{cpu}
@cindex @code{-mcpu=@var{cpu}} command line option, ARC
Set architecture type and register usage for @var{cpu}. There are
also shortcut alias options available for backward compatibility and
convenience. Supported values for @var{cpu} are
@table @code
@cindex @code{mA6} command line option, ARC
@cindex @code{marc600} command line option, ARC
@item arc600
Assemble for ARC 600. Aliases: @code{-mA6}, @code{-mARC600}.
@cindex @code{arc5} arc5, ARC
@item arc5
Base instruction set.
@item arc601
@cindex @code{mARC601} command line option, ARC
Assemble for ARC 601. Alias: @code{-mARC601}.
@cindex @code{arc6} arc6, ARC
@item arc6
Jump-and-link (jl) instruction. No requirement of an instruction between
setting flags and conditional jump. For example:
@item arc700
@cindex @code{mA7} command line option, ARC
@cindex @code{mARC700} command line option, ARC
Assemble for ARC 700. Aliases: @code{-mA7}, @code{-mARC700}.
@smallexample
mov.f r0,r1
beq foo
@end smallexample
@item arcem
@cindex @code{mEM} command line option, ARC
Assemble for ARC EM. Aliases: @code{-mEM}
@cindex @code{arc7} arc7, ARC
@item arc7
Break (brk) and sleep (sleep) instructions.
@cindex @code{arc8} arc8, ARC
@item arc8
Software interrupt (swi) instruction.
@item archs
@cindex @code{mHS} command line option, ARC
Assemble for ARC HS. Aliases: @code{-mHS}, @code{-mav2hs}.
@end table
Note: the @code{.option} directive can to be used to select a core
Note: the @code{.cpu} directive can to be used to select a core
variant from within assembly code.
@cindex @code{-EB} command line option, ARC
@ -78,6 +80,11 @@ This option specifies that the output generated by the assembler should
be marked as being encoded for a little-endian processor - this is the
default.
@cindex @code{-mcode-density} command line option, ARC
@item -mcode-density
This option turns on Code Density instructions. Only valid for ARC EM
processors.
@end table
@node ARC Syntax
@ -90,36 +97,211 @@ default.
@node ARC-Chars
@subsection Special Characters
@table @code
@item %
@cindex register name prefix character, ARC
@cindex ARC register name prefix character
A register name can optionally be prefixed by a @samp{%} character. So
register @code{%r0} is equivalent to @code{r0} in the assembly code.
@item #
@cindex line comment character, ARC
@cindex ARC line comment character
The presence of a @samp{#} on a line indicates the start of a comment
that extends to the end of the current line. Note that if a line
starts with a @samp{#} character then it can also be a logical line
number directive (@pxref{Comments}) or a preprocessor
control command (@pxref{Preprocessing}).
The presence of a @samp{#} character within a line (but not at the
start of a line) indicates the start of a comment that extends to the
end of the current line.
@emph{Note:} if a line starts with a @samp{#} character then it can
also be a logical line number directive (@pxref{Comments}) or a
preprocessor control command (@pxref{Preprocessing}).
@item @@
@cindex symbol prefix character, ARC
@cindex ARC symbol prefix character
Prefixing an operand with an @samp{@@} specifies that the operand is a
symbol and not a register. This is how the assembler disambiguates
the use of an ARC register name as a symbol. So the instruction
@example
mov r0, @@r0
@end example
moves the address of symbol @code{r0} into register @code{r0}.
@item `
@cindex line separator, ARC
@cindex statement separator, ARC
@cindex ARC line separator
The ARC assembler does not support a line separator character.
The @samp{`} (backtick) character is used to separate statements on a
single line.
@cindex line
@item -
@cindex C preprocessor macro separator, ARC
@cindex ARC C preprocessor macro separator
Used as a separator to obtain a sequence of commands from a C
preprocessor macro.
@end table
@node ARC-Regs
@subsection Register Names
@cindex ARC register names
@cindex register names, ARC
*TODO*
The ARC assembler uses the following register names for its core
registers:
@table @code
@item r0-r31
@cindex core general registers, ARC
@cindex ARC core general registers
The core general registers. Registers @code{r26} through @code{r31}
have special functions, and are usually referred to by those synonyms.
@node ARC Floating Point
@section Floating Point
@item gp
@cindex global pointer, ARC
@cindex ARC global pointer
The global pointer and a synonym for @code{r26}.
@cindex floating point, ARC (@sc{ieee})
@cindex ARC floating point (@sc{ieee})
The ARC core does not currently have hardware floating point
support. Software floating point support is provided by @code{GCC}
and uses @sc{ieee} floating-point numbers.
@item fp
@cindex frame pointer, ARC
@cindex ARC frame pointer
The frame pointer and a synonym for @code{r27}.
@item sp
@cindex stack pointer, ARC
@cindex ARC stack pointer
The stack pointer and a synonym for @code{r28}.
@item ilink1
@cindex level 1 interrupt link register, ARC
@cindex ARC level 1 interrupt link register
For ARC 600 and ARC 700, the level 1 interrupt link register and a
synonym for @code{r29}. Not supported for ARCv2.
@item ilink
@cindex interrupt link register, ARC
@cindex ARC interrupt link register
For ARCv2, the interrupt link register and a synonym for @code{r29}.
Not supported for ARC 600 and ARC 700.
@item ilink2
@cindex level 2 interrupt link register, ARC
@cindex ARC level 2 interrupt link register
For ARC 600 and ARC 700, the level 2 interrupt link register and a
synonym for @code{r30}. Not supported for ARC v2.
@item blink
@cindex link register, ARC
@cindex ARC link register
The link register and a synonym for @code{r31}.
@item r32-r59
@cindex extension core registers, ARC
@cindex ARC extension core registers
The extension core registers.
@item lp_count
@cindex loop counter, ARC
@cindex ARC loop counter
The loop count register.
@item pcl
@cindex word aligned program counter, ARC
@cindex ARC word aligned program counter
The word aligned program counter.
@end table
In addition the ARC processor has a large number of @emph{auxiliary
registers}. The precise set depends on the extensions being
supported, but the following baseline set are always defined:
@table @code
@item identity
@cindex Processor Identification register, ARC
@cindex ARC Processor Identification register
Processor Identification register. Auxiliary register address 0x4.
@item pc
@cindex Program Counter, ARC
@cindex ARC Program Counter
Program Counter. Auxiliary register address 0x6.
@item status32
@cindex Status register, ARC
@cindex ARC Status register
Status register. Auxiliary register address 0x0a.
@item bta
@cindex Branch Target Address, ARC
@cindex ARC Branch Target Address
Branch Target Address. Auxiliary register address 0x412.
@item ecr
@cindex Exception Cause Register, ARC
@cindex ARC Exception Cause Register
Exception Cause Register. Auxiliary register address 0x403.
@item int_vector_base
@cindex Interrupt Vector Base address, ARC
@cindex ARC Interrupt Vector Base address
Interrupt Vector Base address. Auxiliary register address 0x25.
@item status32_p0
@cindex Stored STATUS32 register on entry to level P0 interrupts, ARC
@cindex ARC Stored STATUS32 register on entry to level P0 interrupts
Stored STATUS32 register on entry to level P0 interrupts. Auxiliary
register address 0xb.
@item aux_user_sp
@cindex Saved User Stack Pointer, ARC
@cindex ARC Saved User Stack Pointer
Saved User Stack Pointer. Auxiliary register address 0xd.
@item eret
@cindex Exception Return Address, ARC
@cindex ARC Exception Return Address
Exception Return Address. Auxiliary register address 0x400.
@item erbta
@cindex BTA saved on exception entry, ARC
@cindex ARC BTA saved on exception entry
BTA saved on exception entry. Auxiliary register address 0x401.
@item erstatus
@cindex STATUS32 saved on exception, ARC
@cindex ARC STATUS32 saved on exception
STATUS32 saved on exception. Auxiliary register address 0x402.
@item bcr_ver
@cindex Build Configuration Registers Version, ARC
@cindex ARC Build Configuration Registers Version
Build Configuration Registers Version. Auxiliary register address 0x60.
@item bta_link_build
@cindex Build configuration for: BTA Registers, ARC
@cindex ARC Build configuration for: BTA Registers
Build configuration for: BTA Registers. Auxiliary register address 0x63.
@item vecbase_ac_build
@cindex Build configuration for: Interrupts, ARC
@cindex ARC Build configuration for: Interrupts
Build configuration for: Interrupts. Auxiliary register address 0x68.
@item rf_build
@cindex Build configuration for: Core Registers, ARC
@cindex ARC Build configuration for: Core Registers
Build configuration for: Core Registers. Auxiliary register address 0x6e.
@item dccm_build
@cindex DCCM RAM Configuration Register, ARC
@cindex ARC DCCM RAM Configuration Register
DCCM RAM Configuration Register. Auxiliary register address 0xc1.
@end table
Additional auxiliary register names are defined according to the
processor architecture version and extensions selected by the options.
@node ARC Directives
@section ARC Machine Directives
@ -131,205 +313,106 @@ machine directives:
@table @code
@cindex @code{2byte} directive, ARC
@item .2byte @var{expressions}
*TODO*
@cindex @code{lcomm} directive
@item .lcomm @var{symbol} , @var{length}[, @var{alignment}]
Reserve @var{length} (an absolute expression) bytes for a local common
denoted by @var{symbol}. The section and value of @var{symbol} are
those of the new local common. The addresses are allocated in the bss
section, so that at run-time the bytes start off zeroed. Since
@var{symbol} is not declared global, it is normally not visible to
@code{@value{LD}}. The optional third parameter, @var{alignment},
specifies the desired alignment of the symbol in the bss section,
specified as a byte boundary (for example, an alignment of 16 means
that the least significant 4 bits of the address should be zero). The
alignment must be an absolute expression, and it must be a power of
two. If no alignment is specified, as will set the alignment to the
largest power of two less than or equal to the size of the symbol, up
to a maximum of 16.
@cindex @code{3byte} directive, ARC
@item .3byte @var{expressions}
*TODO*
@cindex @code{lcommon} directive
@item .lcommon @var{symbol} , @var{length}[, @var{alignment}]
The same as @code{lcomm} directive.
@cindex @code{4byte} directive, ARC
@item .4byte @var{expressions}
*TODO*
@cindex @code{cpu} directive, ARC
@cindex @code{cpu} directive, ARC
The @code{.cpu} directive must be followed by the desired core
version. Permitted values for CPU are:
@table @code
@item ARC600
Assemble for the ARC600 instruction set.
@cindex @code{extAuxRegister} directive, ARC
@item .extAuxRegister @var{name},@var{address},@var{mode}
The ARCtangent A4 has extensible auxiliary register space. The
auxiliary registers can be defined in the assembler source code by
using this directive. The first parameter is the @var{name} of the
new auxiallry register. The second parameter is the @var{address} of
the register in the auxiliary register memory map for the variant of
the ARC. The third parameter specifies the @var{mode} in which the
register can be operated is and it can be one of:
@item ARC700
Assemble for the ARC700 instruction set.
@item EM
Assemble for the ARC EM instruction set.
@item HS
Assemble for the ARC HS instruction set.
@end table
Note: the @code{.cpu} directive overrides the command line option
@code{-mcpu=@var{cpu}}; a warning is emitted when the version is not
consistent between the two.
@end table
@node ARC Modifiers
@section ARC Assembler Modifiers
The following additional assembler modifiers have been added for
position-independent code. These modifiers are available only with
the ARC 700 and above processors and generate relocation entries,
which are interpreted by the linker as follows:
@table @code
@item r (readonly)
@item w (write only)
@item r|w (read or write)
@item @@pcl(@var{symbol})
@cindex @@pcl(@var{symbol}), ARC modifier
Relative distance of @var{symbol}'s from the current program counter
location.
@item @@gotpc(@var{symbol})
@cindex @@gotpc(@var{symbol}), ARC modifier
Relative distance of @var{symbol}'s Global Offset Table entry from the
current program counter location.
@item @@gotoff(@var{symbol})
@cindex @@gotoff(@var{symbol}), ARC modifier
Distance of @var{symbol} from the base of the Global Offset Table.
@item @@plt(@var{symbol})
@cindex @@plt(@var{symbol}), ARC modifier
Distance of @var{symbol}'s Procedure Linkage Table entry from the
current program counter. This is valid only with branch and link
instructions and PC-relative calls.
@item @@sda(@var{symbol})
@cindex @@sda(@var{symbol}), ARC modifier
Relative distance of @var{symbol} from the base of the Small Data
Pointer.
@end table
For example:
@node ARC Symbols
@section ARC Pre-defined Symbols
@smallexample
.extAuxRegister mulhi,0x12,w
@end smallexample
This specifies an extension auxiliary register called @emph{mulhi}
which is at address 0x12 in the memory space and which is only
writable.
@cindex @code{extCondCode} directive, ARC
@item .extCondCode @var{suffix},@var{value}
The condition codes on the ARCtangent A4 are extensible and can be
specified by means of this assembler directive. They are specified
by the suffix and the value for the condition code. They can be used to
specify extra condition codes with any values. For example:
@smallexample
.extCondCode is_busy,0x14
add.is_busy r1,r2,r3
bis_busy _main
@end smallexample
@cindex @code{extCoreRegister} directive, ARC
@item .extCoreRegister @var{name},@var{regnum},@var{mode},@var{shortcut}
Specifies an extension core register @var{name} for the application.
This allows a register @var{name} with a valid @var{regnum} between 0
and 60, with the following as valid values for @var{mode}
@table @samp
@item @emph{r} (readonly)
@item @emph{w} (write only)
@item @emph{r|w} (read or write)
@end table
The other parameter gives a description of the register having a
@var{shortcut} in the pipeline. The valid values are:
The following assembler symbols will prove useful when developing
position-independent code. These symbols are available only with the
ARC 700 and above processors.
@table @code
@item can_shortcut
@item cannot_shortcut
@end table
@item __GLOBAL_OFFSET_TABLE__
@cindex __GLOBAL_OFFSET_TABLE__, ARC pre-defined symbol
Symbol referring to the base of the Global Offset Table.
For example:
@smallexample
.extCoreRegister mlo,57,r,can_shortcut
@end smallexample
This defines an extension core register mlo with the value 57 which
can shortcut the pipeline.
@cindex @code{extInstruction} directive, ARC
@item .extInstruction @var{name},@var{opcode},@var{subopcode},@var{suffixclass},@var{syntaxclass}
The ARCtangent A4 allows the user to specify extension instructions.
The extension instructions are not macros. The assembler creates
encodings for use of these instructions according to the specification
by the user. The parameters are:
@itemize @bullet
@item @var{name}
Name of the extension instruction
@item @var{opcode}
Opcode to be used. (Bits 27:31 in the encoding). Valid values
0x10-0x1f or 0x03
@item @var{subopcode}
Subopcode to be used. Valid values are from 0x09-0x3f. However the
correct value also depends on @var{syntaxclass}
@item @var{suffixclass}
Determines the kinds of suffixes to be allowed. Valid values are
@code{SUFFIX_NONE}, @code{SUFFIX_COND},
@code{SUFFIX_FLAG} which indicates the absence or presence of
conditional suffixes and flag setting by the extension instruction.
It is also possible to specify that an instruction sets the flags and
is conditional by using @code{SUFFIX_CODE} | @code{SUFFIX_FLAG}.
@item @var{syntaxclass}
Determines the syntax class for the instruction. It can have the
following values:
@table @code
@item @code{SYNTAX_2OP}:
2 Operand Instruction
@item @code{SYNTAX_3OP}:
3 Operand Instruction
@end table
In addition there could be modifiers for the syntax class as described
below:
@itemize @minus
Syntax Class Modifiers are:
@item @code{OP1_MUST_BE_IMM}:
Modifies syntax class SYNTAX_3OP, specifying that the first operand
of a three-operand instruction must be an immediate (i.e., the result
is discarded). OP1_MUST_BE_IMM is used by bitwise ORing it with
SYNTAX_3OP as given in the example below. This could usually be used
to set the flags using specific instructions and not retain results.
@item @code{OP1_IMM_IMPLIED}:
Modifies syntax class SYNTAX_20P, it specifies that there is an
implied immediate destination operand which does not appear in the
syntax. For example, if the source code contains an instruction like:
@smallexample
inst r1,r2
@end smallexample
it really means that the first argument is an implied immediate (that
is, the result is discarded). This is the same as though the source
code were: inst 0,r1,r2. You use OP1_IMM_IMPLIED by bitwise ORing it
with SYNTAX_20P.
@end itemize
@end itemize
For example, defining 64-bit multiplier with immediate operands:
@smallexample
.extInstruction mp64,0x14,0x0,SUFFIX_COND | SUFFIX_FLAG ,
SYNTAX_3OP|OP1_MUST_BE_IMM
@end smallexample
The above specifies an extension instruction called mp64 which has 3 operands,
sets the flags, can be used with a condition code, for which the
first operand is an immediate. (Equivalent to discarding the result
of the operation).
@smallexample
.extInstruction mul64,0x14,0x00,SUFFIX_COND, SYNTAX_2OP|OP1_IMM_IMPLIED
@end smallexample
This describes a 2 operand instruction with an implicit first
immediate operand. The result of this operation would be discarded.
@cindex @code{half} directive, ARC
@item .half @var{expressions}
*TODO*
@cindex @code{long} directive, ARC
@item .long @var{expressions}
*TODO*
@cindex @code{option} directive, ARC
@item .option @var{arc|arc5|arc6|arc7|arc8}
The @code{.option} directive must be followed by the desired core
version. Again @code{arc} is an alias for
@code{arc@value{ARC_CORE_DEFAULT}}.
Note: the @code{.option} directive overrides the command line option
@code{-marc}; a warning is emitted when the version is not consistent
between the two - even for the implicit default core version
(arc@value{ARC_CORE_DEFAULT}).
@cindex @code{short} directive, ARC
@item .short @var{expressions}
*TODO*
@cindex @code{word} directive, ARC
@item .word @var{expressions}
*TODO*
@item __DYNAMIC__
@cindex __DYNAMIC__, ARC pre-defined symbol
An alias for the Global Offset Table
@code{Base__GLOBAL_OFFSET_TABLE__}. It can be used only with
@code{@@gotpc} modifiers.
@end table
@node ARC Opcodes
@section Opcodes
@ -337,4 +420,4 @@ between the two - even for the implicit default core version
@cindex opcodes for ARC
For information on the ARC instruction set, see @cite{ARC Programmers
Reference Manual}, ARC International (www.arc.com)
Reference Manual}, available where you download the processor IP library.

77
gas/testsuite/ChangeLog
View File

@ -1,3 +1,80 @@
2015-10-07 Claudiu Zissulescu <claziss@synopsys.com>
* gas/arc/adc.s: Update test for ARCv1/ARCv2.
* gas/arc/adc.d: Expected output.
* gas/arc/add.s: Update test for ARCv1/ARCv2.
* gas/arc/add.d: Expected output.
* gas/arc/and.s: Update test for ARCv1/ARCv2.
* gas/arc/and.d: Expected output.
* gas/arc/arc.exp: Cleanup.
* gas/arc/asl.s: Update test for ARCv1/ARCv2.
* gas/arc/asl.d: Expected output.
* gas/arc/asr.s: Update test for ARCv1/ARCv2.
* gas/arc/asr.d: Expected output.
* gas/arc/b.s: Update test for ARCv1/ARCv2.
* gas/arc/b.d: Expected output.
* gas/arc/bic.s: Update test for ARCv1/ARCv2.
* gas/arc/bic.d: Expected output.
* gas/arc/bl.s: Update test for ARCv1/ARCv2.
* gas/arc/bl.d: Expected output.
* gas/arc/brk.s: Update test for ARCv1/ARCv2.
* gas/arc/brk.d: Expected output.
* gas/arc/extb.s: Update test for ARCv1/ARCv2.
* gas/arc/extb.d: Expected output.
* gas/arc/extw.s: Update test for ARCv1/ARCv2.
* gas/arc/extw.d: Expected output.
* gas/arc/flag.d: Update output for ARCv1/ARCv2.
* gas/arc/j.s: Update test for ARCv1/ARCv2.
* gas/arc/j.d: Expected output.
* gas/arc/jl.s: Update test for ARCv1/ARCv2.
* gas/arc/jl.d: Expected output.
* gas/arc/ld.s: Update test for ARCv1/ARCv2.
* gas/arc/ld.d: Expected output.
* gas/arc/ld2.s: Update test for ARCv1/ARCv2.
* gas/arc/ld2.d: Expected output.
* gas/arc/lp.s: Update test for ARCv1/ARCv2.
* gas/arc/lp.d: Expected output.
* gas/arc/lsr.s: Update test for ARCv1/ARCv2.
* gas/arc/lsr.d: Expected output.
* gas/arc/mov.s: Update test for ARCv1/ARCv2.
* gas/arc/mov.d: Expected output.
* gas/arc/nop.s: Update test for ARCv1/ARCv2.
* gas/arc/nop.d: Expected output.
* gas/arc/or.s: Update test for ARCv1/ARCv2.
* gas/arc/or.d: Expected output.
* gas/arc/rlc.s: Update test for ARCv1/ARCv2.
* gas/arc/rlc.d: Expected output.
* gas/arc/ror.s: Update test for ARCv1/ARCv2.
* gas/arc/ror.d: Expected output.
* gas/arc/rrc.s: Update test for ARCv1/ARCv2.
* gas/arc/rrc.d: Expected output.
* gas/arc/sbc.s: Update test for ARCv1/ARCv2.
* gas/arc/sbc.d: Expected output.
* gas/arc/sexb.s: Update test for ARCv1/ARCv2.
* gas/arc/sexb.d: Expected output.
* gas/arc/sexw.s: Update test for ARCv1/ARCv2.
* gas/arc/sexw.d: Expected output.
* gas/arc/sleep.s: Update test for ARCv1/ARCv2.
* gas/arc/sleep.d: Expected output.
* gas/arc/st.s: Update test for ARCv1/ARCv2.
* gas/arc/st.d: Expected output.
* gas/arc/sub.s: Update test for ARCv1/ARCv2.
* gas/arc/sub.d: Expected output.
* gas/arc/swi.d: Update expected output for ARCv1/ARCv2.
* gas/arc/warn.exp: Cleanup
* gas/arc/xor.s: Update test for ARCv1/ARCv2.
* gas/arc/xor.d: Expected output.
* gas/arc/alias.d: Removed.
* gas/arc/alias.s: Likewise.
* gas/arc/branch.d: Likewise.
* gas/arc/branch.s: Likewise.
* gas/arc/insn3.d: Likewise.
* gas/arc/insn3.s: Likewise.
* gas/arc/math.d: Likewise.
* gas/arc/math.s: Likewise.
* gas/arc/sshift.d: Likewise.
* gas/arc/sshift.s: Likewise.
2015-10-02 Renlin Li <renlin.li@arm.com>
* gas/aarch64/reloc-tlsdesc_off_g0_nc.d: New.

2
gas/testsuite/gas/all/gas.exp
View File

@ -152,7 +152,7 @@ case $target_triplet in {
run_dump_test redef
# These targets fail redef2 because they disallow redefined
# symbols on relocs.
setup_xfail "m68hc1*-*-*" "m6811-*-*" "m6812-*-*"
setup_xfail "m68hc1*-*-*" "m6811-*-*" "m6812-*-*" "arc-*-*"
setup_xfail "rx-*-*" "vax*-*-*" "xgate*-*-*" "z8k-*-*"
run_dump_test redef2
setup_xfail "m68hc1*-*-*" "m6811-*-*" "m6812-*-*"

140
gas/testsuite/gas/arc/adc.d
View File

@ -1,85 +1,61 @@
#as: -EL
#objdump: -dr -EL
#as: -mcpu=arc700
#objdump: -dr --prefix-addresses --show-raw-insn
.*: +file format elf32-.*arc
.*: +file format .*arc.*
Disassembly of section .text:
00000000 <.text>:
0: 00 84 00 48 48008400 adc r0,r1,r2
4: 00 b8 4d 4b 4b4db800 adc gp,fp,sp
8: 00 3e af 4b 4baf3e00 adc ilink1,ilink2,blink
c: 00 f8 1d 4f 4f1df800 adc r56,r59,lp_count
10: 00 fe 00 48 4800fe00 adc r0,r1,0
14: 00 84 1f 48 481f8400 adc r0,0,r2
18: 00 84 e0 4f 4fe08400 adc 0,r1,r2
1c: ff ff 00 48 4800ffff adc r0,r1,-1
20: ff 85 1f 48 481f85ff adc r0,-1,r2
24: 00 84 e0 4f 4fe08400 adc 0,r1,r2
28: ff fe 00 48 4800feff adc r0,r1,255
2c: ff 84 1f 48 481f84ff adc r0,255,r2
30: 00 84 e0 4f 4fe08400 adc 0,r1,r2
34: 00 ff 00 48 4800ff00 adc r0,r1,-256
38: 00 85 1f 48 481f8500 adc r0,-256,r2
3c: 00 84 e0 4f 4fe08400 adc 0,r1,r2
40: 00 fc 00 48 4800fc00 adc r0,r1,0x100
44: 00 01 00 00
48: 00 04 1f 48 481f0400 adc r0,0xffff_feff,r2
4c: ff fe ff ff
50: ff fc 1f 48 481ffcff adc r0,255,0x100
54: 00 01 00 00
58: ff 7e 1f 48 481f7eff adc r0,0x100,255
5c: 00 01 00 00
60: 00 fc 00 48 4800fc00 adc r0,r1,0
64: 00 00 00 00
64: R_ARC_32 foo
68: 00 84 00 48 48008400 adc r0,r1,r2
6c: 00 0a 62 48 48620a00 adc r3,r4,r5
70: 01 90 c3 48 48c39001 adc.z r6,r7,r8
74: 01 16 25 49 49251601 adc.z r9,r10,r11
78: 02 9c 86 49 49869c02 adc.nz r12,r13,r14
7c: 02 22 e8 49 49e82202 adc.nz r15,r16,r17
80: 03 a8 49 4a 4a49a803 adc.p r18,r19,r20
84: 03 2e ab 4a 4aab2e03 adc.p r21,r22,r23
88: 04 b4 0c 4b 4b0cb404 adc.n r24,r25,gp
8c: 04 3a 6e 4b 4b6e3a04 adc.n fp,sp,ilink1
90: 05 c0 cf 4b 4bcfc005 adc.c ilink2,blink,r32
94: 05 46 31 4c 4c314605 adc.c r33,r34,r35
98: 05 cc 92 4c 4c92cc05 adc.c r36,r37,r38
9c: 06 52 f4 4c 4cf45206 adc.nc r39,r40,r41
a0: 06 d8 55 4d 4d55d806 adc.nc r42,r43,r44
a4: 06 5e b7 4d 4db75e06 adc.nc r45,r46,r47
a8: 07 e4 18 4e 4e18e407 adc.v r48,r49,r50
ac: 07 6a 1a 4f 4f1a6a07 adc.v r56,r52,r53
b0: 08 f0 1b 4f 4f1bf008 adc.nv r56,r55,r56
b4: 08 76 1d 4f 4f1d7608 adc.nv r56,r58,r59
b8: 09 00 9e 4f 4f9e0009 adc.gt lp_count,lp_count,r0
bc: 0a 7c 00 48 48007c0a adc.ge r0,r0,0
c0: 00 00 00 00
c4: 0b 02 3f 48 483f020b adc.lt r1,1,r1
c8: 01 00 00 00
cc: 0d 06 7f 48 487f060d adc.hi r3,3,r3
d0: 03 00 00 00
d4: 0e 08 df 4f 4fdf080e adc.ls 0,4,r4
d8: 04 00 00 00
dc: 0f fc c2 4f 4fc2fc0f adc.pnz 0,r5,5
e0: 05 00 00 00
e4: 00 85 00 48 48008500 adc.f r0,r1,r2
e8: 01 fa 00 48 4800fa01 adc.f r0,r1,1
ec: 01 84 1e 48 481e8401 adc.f r0,1,r2
f0: 00 85 e0 4f 4fe08500 adc.f 0,r1,r2
f4: 00 fd 00 48 4800fd00 adc.f r0,r1,0x200
f8: 00 02 00 00
fc: 00 05 1f 48 481f0500 adc.f r0,0x200,r2
100: 00 02 00 00
104: 01 85 00 48 48008501 adc.z.f r0,r1,r2
108: 02 fd 00 48 4800fd02 adc.nz.f r0,r1,0
10c: 00 00 00 00
110: 0b 05 1f 48 481f050b adc.lt.f r0,0,r2
114: 00 00 00 00
118: 09 85 c0 4f 4fc08509 adc.gt.f 0,r1,r2
11c: 00 00 00 00 00000000
120: 0c fd 00 48 4800fd0c adc.le.f r0,r1,0x200
124: 00 02 00 00
128: 0a 05 1f 48 481f050a adc.ge.f r0,0x200,r2
12c: 00 02 00 00
0x[0-9a-f]+ 2101 0080 adc r0,r1,r2
0x[0-9a-f]+ 2301 371a adc gp,fp,sp
0x[0-9a-f]+ 2601 37dd adc ilink,r30,blink
0x[0-9a-f]+ 2141 0000 adc r0,r1,0
0x[0-9a-f]+ 2601 7080 0000 0000 adc r0,0,r2
0x[0-9a-f]+ 2101 00be adc 0,r1,r2
0x[0-9a-f]+ 2101 0f80 ffff ffff adc r0,r1,0xffffffff
0x[0-9a-f]+ 2601 7080 ffff ffff adc r0,0xffffffff,r2
0x[0-9a-f]+ 2101 0f80 0000 00ff adc r0,r1,0xff
0x[0-9a-f]+ 2601 7080 0000 00ff adc r0,0xff,r2
0x[0-9a-f]+ 2101 0f80 ffff ff00 adc r0,r1,0xffffff00
0x[0-9a-f]+ 2601 7080 ffff ff00 adc r0,0xffffff00,r2
0x[0-9a-f]+ 2101 0f80 0000 0100 adc r0,r1,0x100
0x[0-9a-f]+ 2601 7080 ffff feff adc r0,0xfffffeff,r2
0x[0-9a-f]+ 2601 7f80 0000 0100 adc r0,0x100,0x100
0x[0-9a-f]+ 2101 0f80 0000 0000 adc r0,r1,0
68: ARC_32_ME foo
0x[0-9a-f]+ 20c1 0080 adc r0,r0,r2
0x[0-9a-f]+ 23c1 0140 adc r3,r3,r5
0x[0-9a-f]+ 26c1 0201 adc.eq r6,r6,r8
0x[0-9a-f]+ 21c1 12c1 adc.eq r9,r9,r11
0x[0-9a-f]+ 24c1 1382 adc.ne r12,r12,r14
0x[0-9a-f]+ 27c1 1442 adc.ne r15,r15,r17
0x[0-9a-f]+ 22c1 2503 adc.p r18,r18,r20
0x[0-9a-f]+ 25c1 25c3 adc.p r21,r21,r23
0x[0-9a-f]+ 20c1 3684 adc.n r24,r24,gp
0x[0-9a-f]+ 23c1 3744 adc.n fp,fp,ilink
0x[0-9a-f]+ 26c1 37c5 adc.c r30,r30,blink
0x[0-9a-f]+ 23c1 00c5 adc.c r3,r3,r3
0x[0-9a-f]+ 23c1 0205 adc.c r3,r3,r8
0x[0-9a-f]+ 23c1 0106 adc.nc r3,r3,r4
0x[0-9a-f]+ 24c1 0106 adc.nc r4,r4,r4
0x[0-9a-f]+ 24c1 01c6 adc.nc r4,r4,r7
0x[0-9a-f]+ 24c1 0147 adc.v r4,r4,r5
0x[0-9a-f]+ 25c1 0147 adc.v r5,r5,r5
0x[0-9a-f]+ 25c1 0148 adc.nv r5,r5,r5
0x[0-9a-f]+ 25c1 0148 adc.nv r5,r5,r5
0x[0-9a-f]+ 26c1 0009 adc.gt r6,r6,r0
0x[0-9a-f]+ 20c1 002a adc.ge r0,r0,0
0x[0-9a-f]+ 21c1 006b adc.lt r1,r1,0x1
0x[0-9a-f]+ 23c1 00ed adc.hi r3,r3,0x3
0x[0-9a-f]+ 24c1 012e adc.ls r4,r4,0x4
0x[0-9a-f]+ 25c1 016f adc.pnz r5,r5,0x5
0x[0-9a-f]+ 2101 8080 adc.f r0,r1,r2
0x[0-9a-f]+ 2141 8040 adc.f r0,r1,0x1
0x[0-9a-f]+ 2601 f080 0000 0001 adc.f r0,0x1,r2
0x[0-9a-f]+ 2101 80be adc.f 0,r1,r2
0x[0-9a-f]+ 2101 8f80 0000 0200 adc.f r0,r1,0x200
0x[0-9a-f]+ 2601 f080 0000 0200 adc.f r0,0x200,r2
0x[0-9a-f]+ 21c1 8081 adc.f.eq r1,r1,r2
0x[0-9a-f]+ 20c1 8022 adc.f.ne r0,r0,0
0x[0-9a-f]+ 22c1 808b adc.f.lt r2,r2,r2
0x[0-9a-f]+ 26c1 f0a9 0000 0001 adc.f.gt 0,0x1,0x2
0x[0-9a-f]+ 26c1 ff8c 0000 0200 adc.f.le 0,0x200,0x200
0x[0-9a-f]+ 26c1 f0aa 0000 0200 adc.f.ge 0,0x200,0x2

69
gas/testsuite/gas/arc/adc.s
View File

@ -3,55 +3,50 @@
adc r0,r1,r2
adc r26,fp,sp
adc ilink1,ilink2,blink
adc r56,r59,lp_count
adc r0,r1,0
adc r0,0,r2
adc 0,r1,r2
adc r0,r1,-1
adc r0,-1,r2
adc -1,r1,r2
adc r0,r1,255
adc r0,255,r2
adc 255,r1,r2
adc r0,r1,-256
adc r0,-256,r2
adc -256,r1,r2
adc r0,r1,256
adc r0,-257,r2
adc r0,255,256
adc r0,256,255
adc r0,256,256
adc r0,r1,foo
adc.al r0,r1,r2
adc.ra r3,r4,r5
adc.eq r6,r7,r8
adc.z r9,r10,r11
adc.ne r12,r13,r14
adc.nz r15,r16,r17
adc.pl r18,r19,r20
adc.p r21,r22,r23
adc.mi r24,r25,r26
adc.n r27,r28,r29
adc.cs r30,r31,r32
adc.c r33,r34,r35
adc.lo r36,r37,r38
adc.cc r39,r40,r41
adc.nc r42,r43,r44
adc.hs r45,r46,r47
adc.vs r48,r49,r50
adc.v r56,r52,r53
adc.vc r56,r55,r56
adc.nv r56,r58,r59
adc.gt r60,r60,r0
adc.al r0,r0,r2
adc.ra r3,r3,r5
adc.eq r6,r6,r8
adc.z r9,r9,r11
adc.ne r12,r12,r14
adc.nz r15,r15,r17
adc.pl r18,r18,r20
adc.p r21,r21,r23
adc.mi r24,r24,r26
adc.n r27,r27,r29
adc.cs r30,r30,r31
adc.c r3,r3,r3
adc.lo r3,r3,r8
adc.cc r3,r3,r4
adc.nc r4,r4,r4
adc.hs r4,r4,r7
adc.vs r4,r4,r5
adc.v r5,r5,r5
adc.vc r5,r5,r5
adc.nv r5,r5,r5
adc.gt r6,r6,r0
adc.ge r0,r0,0
adc.lt r1,1,r1
adc.hi r3,3,r3
adc.ls 4,4,r4
adc.pnz 5,r5,5
adc.lt r1,r1,1
adc.hi r3,r3,3
adc.ls r4,r4,4
adc.pnz r5,r5,5
adc.f r0,r1,r2
adc.f r0,r1,1
@ -60,9 +55,9 @@
adc.f r0,r1,512
adc.f r0,512,r2
adc.eq.f r0,r1,r2
adc.ne.f r0,r1,0
adc.lt.f r0,0,r2
adc.gt.f 0,r1,r2
adc.le.f r0,r1,512
adc.ge.f r0,512,r2
adc.eq.f r1,r1,r2
adc.ne.f r0,r0,0
adc.lt.f r2,r2,r2
adc.gt.f 0,1,2
adc.le.f 0,512,512
adc.ge.f 0,512,2

140
gas/testsuite/gas/arc/add.d
View File

@ -1,85 +1,61 @@
#as: -EL
#objdump: -dr -EL
#as: -mcpu=arc700
#objdump: -dr --prefix-addresses --show-raw-insn
.*: +file format elf32-.*arc
.*: +file format .*arc.*
Disassembly of section .text:
00000000 <.text>:
0: 00 84 00 40 40008400 add r0,r1,r2
4: 00 b8 4d 43 434db800 add gp,fp,sp
8: 00 3e af 43 43af3e00 add ilink1,ilink2,blink
c: 00 f8 1d 47 471df800 add r56,r59,lp_count
10: 00 fe 00 40 4000fe00 add r0,r1,0
14: 00 84 1f 40 401f8400 add r0,0,r2
18: 00 84 e0 47 47e08400 add 0,r1,r2
1c: ff ff 00 40 4000ffff add r0,r1,-1
20: ff 85 1f 40 401f85ff add r0,-1,r2
24: 00 84 e0 47 47e08400 add 0,r1,r2
28: ff fe 00 40 4000feff add r0,r1,255
2c: ff 84 1f 40 401f84ff add r0,255,r2
30: 00 84 e0 47 47e08400 add 0,r1,r2
34: 00 ff 00 40 4000ff00 add r0,r1,-256
38: 00 85 1f 40 401f8500 add r0,-256,r2
3c: 00 84 e0 47 47e08400 add 0,r1,r2
40: 00 fc 00 40 4000fc00 add r0,r1,0x100
44: 00 01 00 00
48: 00 04 1f 40 401f0400 add r0,0xffff_feff,r2
4c: ff fe ff ff
50: ff fc 1f 40 401ffcff add r0,255,0x100
54: 00 01 00 00
58: ff 7e 1f 40 401f7eff add r0,0x100,255
5c: 00 01 00 00
60: 00 fc 00 40 4000fc00 add r0,r1,0
64: 00 00 00 00
64: R_ARC_32 foo
68: 00 84 00 40 40008400 add r0,r1,r2
6c: 00 0a 62 40 40620a00 add r3,r4,r5
70: 01 90 c3 40 40c39001 add.z r6,r7,r8
74: 01 16 25 41 41251601 add.z r9,r10,r11
78: 02 9c 86 41 41869c02 add.nz r12,r13,r14
7c: 02 22 e8 41 41e82202 add.nz r15,r16,r17
80: 03 a8 49 42 4249a803 add.p r18,r19,r20
84: 03 2e ab 42 42ab2e03 add.p r21,r22,r23
88: 04 b4 0c 43 430cb404 add.n r24,r25,gp
8c: 04 3a 6e 43 436e3a04 add.n fp,sp,ilink1
90: 05 c0 cf 43 43cfc005 add.c ilink2,blink,r32
94: 05 46 31 44 44314605 add.c r33,r34,r35
98: 05 cc 92 44 4492cc05 add.c r36,r37,r38
9c: 06 52 f4 44 44f45206 add.nc r39,r40,r41
a0: 06 d8 55 45 4555d806 add.nc r42,r43,r44
a4: 06 5e b7 45 45b75e06 add.nc r45,r46,r47
a8: 07 e4 18 46 4618e407 add.v r48,r49,r50
ac: 07 6a 1a 47 471a6a07 add.v r56,r52,r53
b0: 08 f0 1b 47 471bf008 add.nv r56,r55,r56
b4: 08 76 1d 47 471d7608 add.nv r56,r58,r59
b8: 09 00 9e 47 479e0009 add.gt lp_count,lp_count,r0
bc: 0a 7c 00 40 40007c0a add.ge r0,r0,0
c0: 00 00 00 00
c4: 0b 02 3f 40 403f020b add.lt r1,1,r1
c8: 01 00 00 00
cc: 0d 06 7f 40 407f060d add.hi r3,3,r3
d0: 03 00 00 00
d4: 0e 08 df 47 47df080e add.ls 0,4,r4
d8: 04 00 00 00
dc: 0f fc c2 47 47c2fc0f add.pnz 0,r5,5
e0: 05 00 00 00
e4: 00 85 00 40 40008500 add.f r0,r1,r2
e8: 01 fa 00 40 4000fa01 add.f r0,r1,1
ec: 01 84 1e 40 401e8401 add.f r0,1,r2
f0: 00 85 e0 47 47e08500 add.f 0,r1,r2
f4: 00 fd 00 40 4000fd00 add.f r0,r1,0x200
f8: 00 02 00 00
fc: 00 05 1f 40 401f0500 add.f r0,0x200,r2
100: 00 02 00 00
104: 01 85 00 40 40008501 add.z.f r0,r1,r2
108: 02 fd 00 40 4000fd02 add.nz.f r0,r1,0
10c: 00 00 00 00
110: 0b 05 1f 40 401f050b add.lt.f r0,0,r2
114: 00 00 00 00
118: 09 85 c0 47 47c08509 add.gt.f 0,r1,r2
11c: 00 00 00 00 00000000
120: 0c fd 00 40 4000fd0c add.le.f r0,r1,0x200
124: 00 02 00 00
128: 0a 05 1f 40 401f050a add.ge.f r0,0x200,r2
12c: 00 02 00 00
0x[0-9a-f]+ 2100 0080 add r0,r1,r2
0x[0-9a-f]+ 2300 371a add gp,fp,sp
0x[0-9a-f]+ 2600 37dd add ilink,r30,blink
0x[0-9a-f]+ 2140 0000 add r0,r1,0
0x[0-9a-f]+ 2600 7080 0000 0000 add r0,0,r2
0x[0-9a-f]+ 2100 00be add 0,r1,r2
0x[0-9a-f]+ 2100 0f80 ffff ffff add r0,r1,0xffffffff
0x[0-9a-f]+ 2600 7080 ffff ffff add r0,0xffffffff,r2
0x[0-9a-f]+ 2100 0f80 0000 00ff add r0,r1,0xff
0x[0-9a-f]+ 2600 7080 0000 00ff add r0,0xff,r2
0x[0-9a-f]+ 2100 0f80 ffff ff00 add r0,r1,0xffffff00
0x[0-9a-f]+ 2600 7080 ffff ff00 add r0,0xffffff00,r2
0x[0-9a-f]+ 2100 0f80 0000 0100 add r0,r1,0x100
0x[0-9a-f]+ 2600 7080 ffff feff add r0,0xfffffeff,r2
0x[0-9a-f]+ 2600 7f80 0000 0100 add r0,0x100,0x100
0x[0-9a-f]+ 2100 0f80 0000 0000 add r0,r1,0
68: ARC_32_ME foo
0x[0-9a-f]+ 20c0 0080 add r0,r0,r2
0x[0-9a-f]+ 23c0 0140 add r3,r3,r5
0x[0-9a-f]+ 26c0 0201 add.eq r6,r6,r8
0x[0-9a-f]+ 21c0 12c1 add.eq r9,r9,r11
0x[0-9a-f]+ 24c0 1382 add.ne r12,r12,r14
0x[0-9a-f]+ 27c0 1442 add.ne r15,r15,r17
0x[0-9a-f]+ 22c0 2503 add.p r18,r18,r20
0x[0-9a-f]+ 25c0 25c3 add.p r21,r21,r23
0x[0-9a-f]+ 20c0 3684 add.n r24,r24,gp
0x[0-9a-f]+ 23c0 3744 add.n fp,fp,ilink
0x[0-9a-f]+ 26c0 37c5 add.c r30,r30,blink
0x[0-9a-f]+ 23c0 00c5 add.c r3,r3,r3
0x[0-9a-f]+ 23c0 0205 add.c r3,r3,r8
0x[0-9a-f]+ 23c0 0106 add.nc r3,r3,r4
0x[0-9a-f]+ 24c0 0106 add.nc r4,r4,r4
0x[0-9a-f]+ 24c0 01c6 add.nc r4,r4,r7
0x[0-9a-f]+ 24c0 0147 add.v r4,r4,r5
0x[0-9a-f]+ 25c0 0147 add.v r5,r5,r5
0x[0-9a-f]+ 25c0 0148 add.nv r5,r5,r5
0x[0-9a-f]+ 25c0 0148 add.nv r5,r5,r5
0x[0-9a-f]+ 26c0 0009 add.gt r6,r6,r0
0x[0-9a-f]+ 20c0 002a add.ge r0,r0,0
0x[0-9a-f]+ 21c0 006b add.lt r1,r1,0x1
0x[0-9a-f]+ 23c0 00ed add.hi r3,r3,0x3
0x[0-9a-f]+ 24c0 012e add.ls r4,r4,0x4
0x[0-9a-f]+ 25c0 016f add.pnz r5,r5,0x5
0x[0-9a-f]+ 2100 8080 add.f r0,r1,r2
0x[0-9a-f]+ 2140 8040 add.f r0,r1,0x1
0x[0-9a-f]+ 2600 f080 0000 0001 add.f r0,0x1,r2
0x[0-9a-f]+ 2100 80be add.f 0,r1,r2
0x[0-9a-f]+ 2100 8f80 0000 0200 add.f r0,r1,0x200
0x[0-9a-f]+ 2600 f080 0000 0200 add.f r0,0x200,r2
0x[0-9a-f]+ 21c0 8081 add.f.eq r1,r1,r2
0x[0-9a-f]+ 20c0 8022 add.f.ne r0,r0,0
0x[0-9a-f]+ 22c0 808b add.f.lt r2,r2,r2
0x[0-9a-f]+ 26c0 f0a9 0000 0001 add.f.gt 0,0x1,0x2
0x[0-9a-f]+ 26c0 ff8c 0000 0200 add.f.le 0,0x200,0x200
0x[0-9a-f]+ 26c0 f0aa 0000 0200 add.f.ge 0,0x200,0x2

69
gas/testsuite/gas/arc/add.s
View File

@ -3,55 +3,50 @@
add r0,r1,r2
add r26,fp,sp
add ilink1,ilink2,blink
add r56,r59,lp_count
add r0,r1,0
add r0,0,r2
add 0,r1,r2
add r0,r1,-1
add r0,-1,r2
add -1,r1,r2
add r0,r1,255
add r0,255,r2
add 255,r1,r2
add r0,r1,-256
add r0,-256,r2
add -256,r1,r2
add r0,r1,256
add r0,-257,r2
add r0,255,256
add r0,256,255
add r0,256,256
add r0,r1,foo
add.al r0,r1,r2
add.ra r3,r4,r5
add.eq r6,r7,r8
add.z r9,r10,r11
add.ne r12,r13,r14
add.nz r15,r16,r17
add.pl r18,r19,r20
add.p r21,r22,r23
add.mi r24,r25,r26
add.n r27,r28,r29
add.cs r30,r31,r32
add.c r33,r34,r35
add.lo r36,r37,r38
add.cc r39,r40,r41
add.nc r42,r43,r44
add.hs r45,r46,r47
add.vs r48,r49,r50
add.v r56,r52,r53
add.vc r56,r55,r56
add.nv r56,r58,r59
add.gt r60,r60,r0
add.al r0,r0,r2
add.ra r3,r3,r5
add.eq r6,r6,r8
add.z r9,r9,r11
add.ne r12,r12,r14
add.nz r15,r15,r17
add.pl r18,r18,r20
add.p r21,r21,r23
add.mi r24,r24,r26
add.n r27,r27,r29
add.cs r30,r30,r31
add.c r3,r3,r3
add.lo r3,r3,r8
add.cc r3,r3,r4
add.nc r4,r4,r4
add.hs r4,r4,r7
add.vs r4,r4,r5
add.v r5,r5,r5
add.vc r5,r5,r5
add.nv r5,r5,r5
add.gt r6,r6,r0
add.ge r0,r0,0
add.lt r1,1,r1
add.hi r3,3,r3
add.ls 4,4,r4
add.pnz 5,r5,5
add.lt r1,r1,1
add.hi r3,r3,3
add.ls r4,r4,4
add.pnz r5,r5,5
add.f r0,r1,r2
add.f r0,r1,1
@ -60,9 +55,9 @@
add.f r0,r1,512
add.f r0,512,r2
add.eq.f r0,r1,r2
add.ne.f r0,r1,0
add.lt.f r0,0,r2
add.gt.f 0,r1,r2
add.le.f r0,r1,512
add.ge.f r0,512,r2
add.eq.f r1,r1,r2
add.ne.f r0,r0,0
add.lt.f r2,r2,r2
add.gt.f 0,1,2
add.le.f 0,512,512
add.ge.f 0,512,2

68
gas/testsuite/gas/arc/alias.d
View File

@ -1,68 +0,0 @@
#objdump: -dr
#name: @OC@
# Test the @OC@ insn.
.*: +file format elf32-.*arc
Disassembly of section .text:
00000000 @IC+0@008200 @OC@ r0,r1
00000004 @IC+3@6e3800 @OC@ fp,sp
00000008 @IC+0@1ffe00 @OC@ r0,0
0000000c @IC+0@3fffff @OC@ r1,-1
00000010 @IC+7@e10400 @OC@ 0,r2
00000014 @IC+7@e187ff @OC@ -1,r3
00000018 @IC+0@9ffeff @OC@ r4,255
0000001c @IC+7@e28aff @OC@ 255,r5
00000020 @IC+0@dfff00 @OC@ r6,-256
00000024 @IC+7@e38f00 @OC@ -256,r7
00000028 @IC+1@1f7c00 @OC@ r8,256
00000030 @IC+1@3f7c00 @OC@ r9,-257
00000038 @IC+7@c51400 @OC@ 511,r10
00000040 @IC+1@7f7c00 @OC@ r11,1111638594
00000048 @IC+7@c61800 @OC@ 305419896,r12
00000050 @IC+7@ff7cff @OC@ 255,256
00000058 @IC+7@dffeff @OC@ 256,255
00000060 @IC+0@1f7c00 @OC@ r0,0
RELOC: 00000064 R_ARC_32 foo
00000068 @IC+0@008200 @OC@ r0,r1
0000006c @IC+0@620800 @OC@ r3,r4
00000070 @IC+0@c38e01 @OC@.eq r6,r7
00000074 @IC+1@251401 @OC@.eq r9,r10
00000078 @IC+1@869a02 @OC@.ne r12,r13
0000007c @IC+1@e82002 @OC@.ne r15,r16
00000080 @IC+2@49a603 @OC@.p r18,r19
00000084 @IC+2@ab2c03 @OC@.p r21,r22
00000088 @IC+3@0cb204 @OC@.n r24,r25
0000008c @IC+3@6e3804 @OC@.n fp,sp
00000090 @IC+3@cfbe05 @OC@.c ilink2,blink
00000094 @IC+4@314405 @OC@.c r33,r34
00000098 @IC+4@92ca05 @OC@.c r36,r37
0000009c @IC+4@f45006 @OC@.nc r39,r40
000000a0 @IC+5@55d606 @OC@.nc r42,r43
000000a4 @IC+5@b75c06 @OC@.nc r45,r46
000000a8 @IC+6@18e207 @OC@.v r48,r49
000000ac @IC+6@7a6807 @OC@.v r51,r52
000000b0 @IC+6@dbee08 @OC@.nv r54,r55
000000b4 @IC+7@3d7408 @OC@.nv r57,r58
000000b8 @IC+7@9e7809 @OC@.gt lp_count,lp_count
000000bc @IC+0@1f7c0a @OC@.ge r0,0
000000c4 @IC+7@c0820b @OC@.lt 1,r1
000000cc @IC+7@df7c0c @OC@.le 2,2
000000d4 @IC+0@61860d @OC@.hi r3,r3
000000d8 @IC+0@82080e @OC@.ls r4,r4
000000dc @IC+0@a28a0f @OC@.pnz r5,r5
000000e0 @IC+0@008300 @OC@.f r0,r1
000000e4 @IC+0@5efa01 @OC@.f r2,1
000000e8 @IC+7@a18601 @OC@.f 1,r3
000000ec @IC+7@a20800 @OC@.f 0,r4
000000f0 @IC+0@bf7d00 @OC@.f r5,512
000000f8 @IC+7@c30d00 @OC@.f 512,r6
00000100 @IC+7@df7d00 @OC@.f 512,512
00000108 @IC+0@008301 @OC@.eq.f r0,r1
0000010c @IC+0@3f7d02 @OC@.ne.f r1,0
00000114 @IC+7@c1050b @OC@.lt.f 0,r2
0000011c @IC+7@c10509 @OC@.gt.f 1,r2
00000124 @IC+0@1f7d0c @OC@.le.f r0,512
0000012c @IC+7@c1050a @OC@.ge.f 512,r2
00000134 @IC+7@df7d04 @OC@.n.f 512,512

76
gas/testsuite/gas/arc/alias.s
View File

@ -1,76 +0,0 @@
# @OC@ test
# reg,reg
@OC@ r0,r1
@OC@ fp,sp
# shimm values
@OC@ r0,0
@OC@ r1,-1
@OC@ 0,r2
@OC@ -1,r3
@OC@ r4,255
@OC@ 255,r5
@OC@ r6,-256
@OC@ -256,r7
# limm values
@OC@ r8,256
@OC@ r9,-257
@OC@ 511,r10
@OC@ r11,0x42424242
@OC@ 0x12345678,r12
# shimm and limm
@OC@ 255,256
@OC@ 256,255
# symbols
@OC@ r0,foo
# conditional execution
@OC@.al r0,r1
@OC@.ra r3,r4
@OC@.eq r6,r7
@OC@.z r9,r10
@OC@.ne r12,r13
@OC@.nz r15,r16
@OC@.pl r18,r19
@OC@.p r21,r22
@OC@.mi r24,r25
@OC@.n r27,r28
@OC@.cs r30,r31
@OC@.c r33,r34
@OC@.lo r36,r37
@OC@.cc r39,r40
@OC@.nc r42,r43
@OC@.hs r45,r46
@OC@.vs r48,r49
@OC@.v r51,r52
@OC@.vc r54,r55
@OC@.nv r57,r58
@OC@.gt r60,r60
@OC@.ge r0,0
@OC@.lt 1,r1
@OC@.le 2,2
@OC@.hi r3,r3
@OC@.ls r4,r4
@OC@.pnz r5,r5
# flag setting
@OC@.f r0,r1
@OC@.f r2,1
@OC@.f 1,r3
@OC@.f 0,r4
@OC@.f r5,512
@OC@.f 512,r6
@OC@.f 512,512
# conditional execution + flag setting
@OC@.eq.f r0,r1
@OC@.ne.f r1,0
@OC@.lt.f 0,r2
@OC@.gt.f 1,r2
@OC@.le.f r0,512
@OC@.ge.f 512,r2
@OC@.n.f 512,512

140
gas/testsuite/gas/arc/and.d
View File

@ -1,85 +1,61 @@
#as: -EL
#objdump: -dr -EL
#as: -mcpu=arc700
#objdump: -dr --prefix-addresses --show-raw-insn
.*: +file format elf32-.*arc
.*: +file format .*arc.*
Disassembly of section .text:
00000000 <.text>:
0: 00 84 00 60 60008400 and r0,r1,r2
4: 00 b8 4d 63 634db800 and gp,fp,sp
8: 00 3e af 63 63af3e00 and ilink1,ilink2,blink
c: 00 f8 1d 67 671df800 and r56,r59,lp_count
10: 00 fe 00 60 6000fe00 and r0,r1,0
14: 00 84 1f 60 601f8400 and r0,0,r2
18: 00 84 e0 67 67e08400 and 0,r1,r2
1c: ff ff 00 60 6000ffff and r0,r1,-1
20: ff 85 1f 60 601f85ff and r0,-1,r2
24: 00 84 e0 67 67e08400 and 0,r1,r2
28: ff fe 00 60 6000feff and r0,r1,255
2c: ff 84 1f 60 601f84ff and r0,255,r2
30: 00 84 e0 67 67e08400 and 0,r1,r2
34: 00 ff 00 60 6000ff00 and r0,r1,-256
38: 00 85 1f 60 601f8500 and r0,-256,r2
3c: 00 84 e0 67 67e08400 and 0,r1,r2
40: 00 fc 00 60 6000fc00 and r0,r1,0x100
44: 00 01 00 00
48: 00 04 1f 60 601f0400 and r0,0xffff_feff,r2
4c: ff fe ff ff
50: ff fc 1f 60 601ffcff and r0,255,0x100
54: 00 01 00 00
58: ff 7e 1f 60 601f7eff and r0,0x100,255
5c: 00 01 00 00
60: 00 fc 00 60 6000fc00 and r0,r1,0
64: 00 00 00 00
64: R_ARC_32 foo
68: 00 84 00 60 60008400 and r0,r1,r2
6c: 00 0a 62 60 60620a00 and r3,r4,r5
70: 01 90 c3 60 60c39001 and.z r6,r7,r8
74: 01 16 25 61 61251601 and.z r9,r10,r11
78: 02 9c 86 61 61869c02 and.nz r12,r13,r14
7c: 02 22 e8 61 61e82202 and.nz r15,r16,r17
80: 03 a8 49 62 6249a803 and.p r18,r19,r20
84: 03 2e ab 62 62ab2e03 and.p r21,r22,r23
88: 04 b4 0c 63 630cb404 and.n r24,r25,gp
8c: 04 3a 6e 63 636e3a04 and.n fp,sp,ilink1
90: 05 c0 cf 63 63cfc005 and.c ilink2,blink,r32
94: 05 46 31 64 64314605 and.c r33,r34,r35
98: 05 cc 92 64 6492cc05 and.c r36,r37,r38
9c: 06 52 f4 64 64f45206 and.nc r39,r40,r41
a0: 06 d8 55 65 6555d806 and.nc r42,r43,r44
a4: 06 5e b7 65 65b75e06 and.nc r45,r46,r47
a8: 07 e4 18 66 6618e407 and.v r48,r49,r50
ac: 07 6a 1a 67 671a6a07 and.v r56,r52,r53
b0: 08 f0 1b 67 671bf008 and.nv r56,r55,r56
b4: 08 76 1d 67 671d7608 and.nv r56,r58,r59
b8: 09 00 9e 67 679e0009 and.gt lp_count,lp_count,r0
bc: 0a 7c 00 60 60007c0a and.ge r0,r0,0
c0: 00 00 00 00
c4: 0b 02 3f 60 603f020b and.lt r1,1,r1
c8: 01 00 00 00
cc: 0d 06 7f 60 607f060d and.hi r3,3,r3
d0: 03 00 00 00
d4: 0e 08 df 67 67df080e and.ls 0,4,r4
d8: 04 00 00 00
dc: 0f fc c2 67 67c2fc0f and.pnz 0,r5,5
e0: 05 00 00 00
e4: 00 85 00 60 60008500 and.f r0,r1,r2
e8: 01 fa 00 60 6000fa01 and.f r0,r1,1
ec: 01 84 1e 60 601e8401 and.f r0,1,r2
f0: 00 85 e0 67 67e08500 and.f 0,r1,r2
f4: 00 fd 00 60 6000fd00 and.f r0,r1,0x200
f8: 00 02 00 00
fc: 00 05 1f 60 601f0500 and.f r0,0x200,r2
100: 00 02 00 00
104: 01 85 00 60 60008501 and.z.f r0,r1,r2
108: 02 fd 00 60 6000fd02 and.nz.f r0,r1,0
10c: 00 00 00 00
110: 0b 05 1f 60 601f050b and.lt.f r0,0,r2
114: 00 00 00 00
118: 09 85 c0 67 67c08509 and.gt.f 0,r1,r2
11c: 00 00 00 00 00000000
120: 0c fd 00 60 6000fd0c and.le.f r0,r1,0x200
124: 00 02 00 00
128: 0a 05 1f 60 601f050a and.ge.f r0,0x200,r2
12c: 00 02 00 00
0x[0-9a-f]+ 2104 0080 and r0,r1,r2
0x[0-9a-f]+ 2304 371a and gp,fp,sp
0x[0-9a-f]+ 2604 37dd and ilink,r30,blink
0x[0-9a-f]+ 2144 0000 and r0,r1,0
0x[0-9a-f]+ 2604 7080 0000 0000 and r0,0,r2
0x[0-9a-f]+ 2104 00be and 0,r1,r2
0x[0-9a-f]+ 2104 0f80 ffff ffff and r0,r1,0xffffffff
0x[0-9a-f]+ 2604 7080 ffff ffff and r0,0xffffffff,r2
0x[0-9a-f]+ 2104 0f80 0000 00ff and r0,r1,0xff
0x[0-9a-f]+ 2604 7080 0000 00ff and r0,0xff,r2
0x[0-9a-f]+ 2104 0f80 ffff ff00 and r0,r1,0xffffff00
0x[0-9a-f]+ 2604 7080 ffff ff00 and r0,0xffffff00,r2
0x[0-9a-f]+ 2104 0f80 0000 0100 and r0,r1,0x100
0x[0-9a-f]+ 2604 7080 ffff feff and r0,0xfffffeff,r2
0x[0-9a-f]+ 2604 7f80 0000 0100 and r0,0x100,0x100
0x[0-9a-f]+ 2104 0f80 0000 0000 and r0,r1,0
68: ARC_32_ME foo
0x[0-9a-f]+ 20c4 0080 and r0,r0,r2
0x[0-9a-f]+ 23c4 0140 and r3,r3,r5
0x[0-9a-f]+ 26c4 0201 and.eq r6,r6,r8
0x[0-9a-f]+ 21c4 12c1 and.eq r9,r9,r11
0x[0-9a-f]+ 24c4 1382 and.ne r12,r12,r14
0x[0-9a-f]+ 27c4 1442 and.ne r15,r15,r17
0x[0-9a-f]+ 22c4 2503 and.p r18,r18,r20
0x[0-9a-f]+ 25c4 25c3 and.p r21,r21,r23
0x[0-9a-f]+ 20c4 3684 and.n r24,r24,gp
0x[0-9a-f]+ 23c4 3744 and.n fp,fp,ilink
0x[0-9a-f]+ 26c4 37c5 and.c r30,r30,blink
0x[0-9a-f]+ 23c4 00c5 and.c r3,r3,r3
0x[0-9a-f]+ 23c4 0205 and.c r3,r3,r8
0x[0-9a-f]+ 23c4 0106 and.nc r3,r3,r4
0x[0-9a-f]+ 24c4 0106 and.nc r4,r4,r4
0x[0-9a-f]+ 24c4 01c6 and.nc r4,r4,r7
0x[0-9a-f]+ 24c4 0147 and.v r4,r4,r5
0x[0-9a-f]+ 25c4 0147 and.v r5,r5,r5
0x[0-9a-f]+ 25c4 0148 and.nv r5,r5,r5
0x[0-9a-f]+ 25c4 0148 and.nv r5,r5,r5
0x[0-9a-f]+ 26c4 0009 and.gt r6,r6,r0
0x[0-9a-f]+ 20c4 002a and.ge r0,r0,0
0x[0-9a-f]+ 21c4 006b and.lt r1,r1,0x1
0x[0-9a-f]+ 23c4 00ed and.hi r3,r3,0x3
0x[0-9a-f]+ 24c4 012e and.ls r4,r4,0x4
0x[0-9a-f]+ 25c4 016f and.pnz r5,r5,0x5
0x[0-9a-f]+ 2104 8080 and.f r0,r1,r2
0x[0-9a-f]+ 2144 8040 and.f r0,r1,0x1
0x[0-9a-f]+ 2604 f080 0000 0001 and.f r0,0x1,r2
0x[0-9a-f]+ 2104 80be and.f 0,r1,r2
0x[0-9a-f]+ 2104 8f80 0000 0200 and.f r0,r1,0x200
0x[0-9a-f]+ 2604 f080 0000 0200 and.f r0,0x200,r2
0x[0-9a-f]+ 21c4 8081 and.f.eq r1,r1,r2
0x[0-9a-f]+ 20c4 8022 and.f.ne r0,r0,0
0x[0-9a-f]+ 22c4 808b and.f.lt r2,r2,r2
0x[0-9a-f]+ 26c4 f0a9 0000 0001 and.f.gt 0,0x1,0x2
0x[0-9a-f]+ 26c4 ff8c 0000 0200 and.f.le 0,0x200,0x200
0x[0-9a-f]+ 26c4 f0aa 0000 0200 and.f.ge 0,0x200,0x2

69
gas/testsuite/gas/arc/and.s
View File

@ -3,55 +3,50 @@
and r0,r1,r2
and r26,fp,sp
and ilink1,ilink2,blink
and r56,r59,lp_count
and r0,r1,0
and r0,0,r2
and 0,r1,r2
and r0,r1,-1
and r0,-1,r2
and -1,r1,r2
and r0,r1,255
and r0,255,r2
and 255,r1,r2
and r0,r1,-256
and r0,-256,r2
and -256,r1,r2
and r0,r1,256
and r0,-257,r2
and r0,255,256
and r0,256,255
and r0,256,256
and r0,r1,foo
and.al r0,r1,r2
and.ra r3,r4,r5
and.eq r6,r7,r8
and.z r9,r10,r11
and.ne r12,r13,r14
and.nz r15,r16,r17
and.pl r18,r19,r20
and.p r21,r22,r23
and.mi r24,r25,r26
and.n r27,r28,r29
and.cs r30,r31,r32
and.c r33,r34,r35
and.lo r36,r37,r38
and.cc r39,r40,r41
and.nc r42,r43,r44
and.hs r45,r46,r47
and.vs r48,r49,r50
and.v r56,r52,r53
and.vc r56,r55,r56
and.nv r56,r58,r59
and.gt r60,r60,r0
and.al r0,r0,r2
and.ra r3,r3,r5
and.eq r6,r6,r8
and.z r9,r9,r11
and.ne r12,r12,r14
and.nz r15,r15,r17
and.pl r18,r18,r20
and.p r21,r21,r23
and.mi r24,r24,r26
and.n r27,r27,r29
and.cs r30,r30,r31
and.c r3,r3,r3
and.lo r3,r3,r8
and.cc r3,r3,r4
and.nc r4,r4,r4
and.hs r4,r4,r7
and.vs r4,r4,r5
and.v r5,r5,r5
and.vc r5,r5,r5
and.nv r5,r5,r5
and.gt r6,r6,r0
and.ge r0,r0,0
and.lt r1,1,r1
and.hi r3,3,r3
and.ls 4,4,r4
and.pnz 5,r5,5
and.lt r1,r1,1
and.hi r3,r3,3
and.ls r4,r4,4
and.pnz r5,r5,5
and.f r0,r1,r2
and.f r0,r1,1
@ -60,9 +55,9 @@
and.f r0,r1,512
and.f r0,512,r2
and.eq.f r0,r1,r2
and.ne.f r0,r1,0
and.lt.f r0,0,r2
and.gt.f 0,r1,r2
and.le.f r0,r1,512
and.ge.f r0,512,r2
and.eq.f r1,r1,r2
and.ne.f r0,r0,0
and.lt.f r2,r2,r2
and.gt.f 0,1,2
and.le.f 0,512,512
and.ge.f 0,512,2

50
gas/testsuite/gas/arc/arc.exp
View File

@ -4,59 +4,19 @@
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3 of the License, or
# (at your option) any later version.
#
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
# ARC base instruction set (to arc8)
if [istarget arc*-*-*] then {
run_dump_test ld
run_dump_test ld2
run_dump_test st
# Specially encoded/single operand instructions
run_dump_test flag
run_dump_test brk
run_dump_test sleep
run_dump_test swi
run_dump_test asr
run_dump_test lsr
run_dump_test ror
run_dump_test rrc
run_dump_test sexb
run_dump_test sexw
run_dump_test extb
run_dump_test extw
run_dump_test b
run_dump_test bl
run_dump_test lp
run_dump_test j
run_dump_test jl
run_dump_test add
run_dump_test asl
# FIXME: ??? `lsl' gets dumped as `asl'
# run_dump_test lsl
run_dump_test adc
run_dump_test rlc
run_dump_test sub
run_dump_test sbc
run_dump_test and
run_dump_test mov
run_dump_test or
run_dump_test bic
run_dump_test xor
run_dump_test nop
run_dump_test extensions
}
# ARC base instruction set
# ARC library extensions
if [istarget arc*-*-*] then {
# *TODO*
run_dump_tests [lsort [glob -nocomplain $srcdir/$subdir/*.d]]
}

123
gas/testsuite/gas/arc/asl.d
View File

@ -1,68 +1,61 @@
#as: -EL
#objdump: -dr -EL
#as: -mcpu=arc700
#objdump: -dr --prefix-addresses --show-raw-insn
.*: +file format elf32-.*arc
.*: +file format .*arc.*
Disassembly of section .text:
00000000 <.text>:
0: 00 82 00 40 40008200 asl r0,r1
4: 00 38 6e 43 436e3800 asl fp,sp
8: 00 fe 1f 40 401ffe00 asl r0,0
c: ff ff 3f 40 403fffff asl r1,-1
10: 00 04 e1 47 47e10400 asl 0,r2
14: 00 86 e1 47 47e18600 asl 0,r3
18: ff fe 9f 40 409ffeff asl r4,255
1c: 00 8a e2 47 47e28a00 asl 0,r5
20: 00 ff df 40 40dfff00 asl r6,-256
24: 00 8e e3 47 47e38e00 asl 0,r7
28: 00 7c 1f 41 411f7c00 asl r8,0x100
2c: 00 01 00 00
30: 00 7c 3f 41 413f7c00 asl r9,0xffff_feff
34: ff fe ff ff
38: 00 7c 7f 41 417f7c00 asl r11,0x4242_4242
3c: 42 42 42 42
40: 00 7c ff 47 47ff7c00 asl 0,0x100
44: 00 01 00 00
48: 00 7c 1f 40 401f7c00 asl r0,0
4c: 00 00 00 00
4c: R_ARC_32 foo
50: 00 82 00 40 40008200 asl r0,r1
54: 00 08 62 40 40620800 asl r3,r4
58: 01 8e c3 40 40c38e01 asl.z r6,r7
5c: 01 14 25 41 41251401 asl.z r9,r10
60: 02 9a 86 41 41869a02 asl.nz r12,r13
64: 02 20 e8 41 41e82002 asl.nz r15,r16
68: 03 a6 49 42 4249a603 asl.p r18,r19
6c: 03 2c ab 42 42ab2c03 asl.p r21,r22
70: 04 b2 0c 43 430cb204 asl.n r24,r25
74: 04 38 6e 43 436e3804 asl.n fp,sp
78: 05 be cf 43 43cfbe05 asl.c ilink2,blink
7c: 05 44 31 44 44314405 asl.c r33,r34
80: 05 ca 92 44 4492ca05 asl.c r36,r37
84: 06 50 f4 44 44f45006 asl.nc r39,r40
88: 06 d6 55 45 4555d606 asl.nc r42,r43
8c: 06 5c b7 45 45b75c06 asl.nc r45,r46
90: 07 e2 18 46 4618e207 asl.v r48,r49
94: 07 64 39 46 46396407 asl.v r49,r50
98: 08 ee 3b 46 463bee08 asl.nv r49,r55
9c: 08 74 3d 46 463d7408 asl.nv r49,r58
a0: 09 78 9e 47 479e7809 asl.gt lp_count,lp_count
a4: 0a 7c 1f 40 401f7c0a asl.ge r0,0
a8: 00 00 00 00
ac: 0c 7c df 47 47df7c0c asl.le 0,2
b0: 02 00 00 00
b4: 0d 86 61 40 4061860d asl.hi r3,r3
b8: 0e 08 82 40 4082080e asl.ls r4,r4
bc: 0f 8a a2 40 40a28a0f asl.pnz r5,r5
c0: 00 83 00 40 40008300 asl.f r0,r1
c4: 01 fa 5e 40 405efa01 asl.f r2,1
c8: 00 87 e1 47 47e18700 asl.f 0,r3
cc: 00 09 e2 47 47e20900 asl.f 0,r4
d0: 00 7d bf 40 40bf7d00 asl.f r5,0x200
d4: 00 02 00 00
d8: 00 7d df 47 47df7d00 asl.f 0,0x200
dc: 00 02 00 00
e0: 01 83 00 40 40008301 asl.z.f r0,r1
e4: 02 7d 3f 40 403f7d02 asl.nz.f r1,0
e8: 00 00 00 00
0x[0-9a-f]+ 2900 0080 asl r0,r1,r2
0x[0-9a-f]+ 2b00 371a asl gp,fp,sp
0x[0-9a-f]+ 2e00 37dd asl ilink,r30,blink
0x[0-9a-f]+ 2940 0000 asl r0,r1,0
0x[0-9a-f]+ 2e00 7080 0000 0000 asl r0,0,r2
0x[0-9a-f]+ 2900 00be asl 0,r1,r2
0x[0-9a-f]+ 2900 0f80 ffff ffff asl r0,r1,0xffffffff
0x[0-9a-f]+ 2e00 7080 ffff ffff asl r0,0xffffffff,r2
0x[0-9a-f]+ 2900 0f80 0000 00ff asl r0,r1,0xff
0x[0-9a-f]+ 2e00 7080 0000 00ff asl r0,0xff,r2
0x[0-9a-f]+ 2900 0f80 ffff ff00 asl r0,r1,0xffffff00
0x[0-9a-f]+ 2e00 7080 ffff ff00 asl r0,0xffffff00,r2
0x[0-9a-f]+ 2900 0f80 0000 0100 asl r0,r1,0x100
0x[0-9a-f]+ 2e00 7080 ffff feff asl r0,0xfffffeff,r2
0x[0-9a-f]+ 2e00 7f80 0000 0100 asl r0,0x100,0x100
0x[0-9a-f]+ 2900 0f80 0000 0000 asl r0,r1,0
68: ARC_32_ME foo
0x[0-9a-f]+ 28c0 0080 asl r0,r0,r2
0x[0-9a-f]+ 2bc0 0140 asl r3,r3,r5
0x[0-9a-f]+ 2ec0 0201 asl.eq r6,r6,r8
0x[0-9a-f]+ 29c0 12c1 asl.eq r9,r9,r11
0x[0-9a-f]+ 2cc0 1382 asl.ne r12,r12,r14
0x[0-9a-f]+ 2fc0 1442 asl.ne r15,r15,r17
0x[0-9a-f]+ 2ac0 2503 asl.p r18,r18,r20
0x[0-9a-f]+ 2dc0 25c3 asl.p r21,r21,r23
0x[0-9a-f]+ 28c0 3684 asl.n r24,r24,gp
0x[0-9a-f]+ 2bc0 3744 asl.n fp,fp,ilink
0x[0-9a-f]+ 2ec0 37c5 asl.c r30,r30,blink
0x[0-9a-f]+ 2bc0 00c5 asl.c r3,r3,r3
0x[0-9a-f]+ 2bc0 0205 asl.c r3,r3,r8
0x[0-9a-f]+ 2bc0 0106 asl.nc r3,r3,r4
0x[0-9a-f]+ 2cc0 0106 asl.nc r4,r4,r4
0x[0-9a-f]+ 2cc0 01c6 asl.nc r4,r4,r7
0x[0-9a-f]+ 2cc0 0147 asl.v r4,r4,r5
0x[0-9a-f]+ 2dc0 0147 asl.v r5,r5,r5
0x[0-9a-f]+ 2dc0 0148 asl.nv r5,r5,r5
0x[0-9a-f]+ 2dc0 0148 asl.nv r5,r5,r5
0x[0-9a-f]+ 2ec0 0009 asl.gt r6,r6,r0
0x[0-9a-f]+ 28c0 002a asl.ge r0,r0,0
0x[0-9a-f]+ 29c0 006b asl.lt r1,r1,0x1
0x[0-9a-f]+ 2bc0 00ed asl.hi r3,r3,0x3
0x[0-9a-f]+ 2cc0 012e asl.ls r4,r4,0x4
0x[0-9a-f]+ 2dc0 016f asl.pnz r5,r5,0x5
0x[0-9a-f]+ 2900 8080 asl.f r0,r1,r2
0x[0-9a-f]+ 2940 8040 asl.f r0,r1,0x1
0x[0-9a-f]+ 2e00 f080 0000 0001 asl.f r0,0x1,r2
0x[0-9a-f]+ 2900 80be asl.f 0,r1,r2
0x[0-9a-f]+ 2900 8f80 0000 0200 asl.f r0,r1,0x200
0x[0-9a-f]+ 2e00 f080 0000 0200 asl.f r0,0x200,r2
0x[0-9a-f]+ 29c0 8081 asl.f.eq r1,r1,r2
0x[0-9a-f]+ 28c0 8022 asl.f.ne r0,r0,0
0x[0-9a-f]+ 2ac0 808b asl.f.lt r2,r2,r2
0x[0-9a-f]+ 2ec0 f0a9 0000 0001 asl.f.gt 0,0x1,0x2
0x[0-9a-f]+ 2ec0 ff8c 0000 0200 asl.f.le 0,0x200,0x200
0x[0-9a-f]+ 2ec0 f0aa 0000 0200 asl.f.ge 0,0x200,0x2

103
gas/testsuite/gas/arc/asl.s
View File

@ -1,58 +1,63 @@
# asl test
asl r0,r1
asl fp,sp
asl r0,r1,r2
asl r26,fp,sp
asl ilink1,ilink2,blink
asl r0,0
asl r1,-1
asl 0,r2
asl -1,r3
asl r4,255
asl 255,r5
asl r6,-256
asl -256,r7
asl r0,r1,0
asl r0,0,r2
asl 0,r1,r2
asl r0,r1,-1
asl r0,-1,r2
asl r0,r1,255
asl r0,255,r2
asl r0,r1,-256
asl r0,-256,r2
asl r8,256
asl r9,-257
asl r11,0x42424242
asl r0,r1,256
asl r0,-257,r2
asl 255,256
asl r0,256,256
asl r0,foo
asl r0,r1,foo
asl.al r0,r1
asl.ra r3,r4
asl.eq r6,r7
asl.z r9,r10
asl.ne r12,r13
asl.nz r15,r16
asl.pl r18,r19
asl.p r21,r22
asl.mi r24,r25
asl.n r27,r28
asl.cs r30,r31
asl.c r33,r34
asl.lo r36,r37
asl.cc r39,r40
asl.nc r42,r43
asl.hs r45,r46
asl.vs r48,r49
asl.v r49,r50
asl.vc r49,r55
asl.nv r49,r58
asl.gt r60,r60
asl.ge r0,0
asl.le 2,2
asl.hi r3,r3
asl.ls r4,r4
asl.pnz r5,r5
asl.al r0,r0,r2
asl.ra r3,r3,r5
asl.eq r6,r6,r8
asl.z r9,r9,r11
asl.ne r12,r12,r14
asl.nz r15,r15,r17
asl.pl r18,r18,r20
asl.p r21,r21,r23
asl.mi r24,r24,r26
asl.n r27,r27,r29
asl.cs r30,r30,r31
asl.c r3,r3,r3
asl.lo r3,r3,r8
asl.cc r3,r3,r4
asl.nc r4,r4,r4
asl.hs r4,r4,r7
asl.vs r4,r4,r5
asl.v r5,r5,r5
asl.vc r5,r5,r5
asl.nv r5,r5,r5
asl.gt r6,r6,r0
asl.ge r0,r0,0
asl.lt r1,r1,1
asl.hi r3,r3,3
asl.ls r4,r4,4
asl.pnz r5,r5,5
asl.f r0,r1
asl.f r2,1
asl.f 1,r3
asl.f 0,r4
asl.f r5,512
asl.f 512,512
asl.f r0,r1,r2
asl.f r0,r1,1
asl.f r0,1,r2
asl.f 0,r1,r2
asl.f r0,r1,512
asl.f r0,512,r2
asl.eq.f r0,r1
asl.ne.f r1,0
asl.eq.f r1,r1,r2
asl.ne.f r0,r0,0
asl.lt.f r2,r2,r2
asl.gt.f 0,1,2
asl.le.f 0,512,512
asl.ge.f 0,512,2

106
gas/testsuite/gas/arc/asr.d
View File

@ -1,51 +1,61 @@
#as: -EL
#objdump: -dr -EL
#as: -mcpu=arc700
#objdump: -dr --prefix-addresses --show-raw-insn
.*: +file format elf32-.*arc
.*: +file format .*arc.*
Disassembly of section .text:
00000000 <.text>:
0: 00 82 00 18 18008200 asr r0,r1
4: 00 02 6e 1b 1b6e0200 asr fp,sp
8: 00 82 1f 18 181f8200 asr r0,0
c: ff 83 3f 18 183f83ff asr r1,-1
10: 00 02 e1 1f 1fe10200 asr 0,r2
14: 00 82 e1 1f 1fe18200 asr 0,r3
18: ff 82 9f 18 189f82ff asr r4,255
1c: 00 82 e2 1f 1fe28200 asr 0,r5
20: 00 83 df 18 18df8300 asr r6,-256
24: 00 82 e3 1f 1fe38200 asr 0,r7
28: 00 02 1f 19 191f0200 asr r8,0x100
2c: 00 01 00 00
30: 00 02 3f 19 193f0200 asr r9,0xffff_feff
34: ff fe ff ff
38: 00 02 7f 19 197f0200 asr r11,0x4242_4242
3c: 42 42 42 42
40: 00 02 ff 1f 1fff0200 asr 0,0x100
44: 00 01 00 00
48: 00 02 1f 18 181f0200 asr r0,0
4c: 00 00 00 00
4c: R_ARC_32 foo
50: 01 82 45 19 19458201 asr.z r10,r11
54: 02 82 86 19 19868202 asr.nz r12,r13
58: 0b 02 df 19 19df020b asr.lt r14,0
5c: 00 00 00 00
60: 09 02 ff 19 19ff0209 asr.gt r15,0x200
64: 00 02 00 00
68: 00 83 00 18 18008300 asr.f r0,r1
6c: 01 82 5e 18 185e8201 asr.f r2,1
70: 00 03 e2 1f 1fe20300 asr.f 0,r4
74: 00 03 bf 18 18bf0300 asr.f r5,0x200
78: 00 02 00 00
7c: 00 03 df 1f 1fdf0300 asr.f 0,0x200
80: 00 02 00 00
84: 01 83 00 18 18008301 asr.z.f r0,r1
88: 02 03 3f 18 183f0302 asr.nz.f r1,0
8c: 00 00 00 00
90: 0b 03 c1 1f 1fc1030b asr.lt.f 0,r2
94: 00 00 00 00 00000000
98: 0c 03 1f 18 181f030c asr.le.f r0,0x200
9c: 00 02 00 00
a0: 04 03 df 1f 1fdf0304 asr.n.f 0,0x200
a4: 00 02 00 00
0x[0-9a-f]+ 2902 0080 asr r0,r1,r2
0x[0-9a-f]+ 2b02 371a asr gp,fp,sp
0x[0-9a-f]+ 2e02 37dd asr ilink,r30,blink
0x[0-9a-f]+ 2942 0000 asr r0,r1,0
0x[0-9a-f]+ 2e02 7080 0000 0000 asr r0,0,r2
0x[0-9a-f]+ 2902 00be asr 0,r1,r2
0x[0-9a-f]+ 2902 0f80 ffff ffff asr r0,r1,0xffffffff
0x[0-9a-f]+ 2e02 7080 ffff ffff asr r0,0xffffffff,r2
0x[0-9a-f]+ 2902 0f80 0000 00ff asr r0,r1,0xff
0x[0-9a-f]+ 2e02 7080 0000 00ff asr r0,0xff,r2
0x[0-9a-f]+ 2902 0f80 ffff ff00 asr r0,r1,0xffffff00
0x[0-9a-f]+ 2e02 7080 ffff ff00 asr r0,0xffffff00,r2
0x[0-9a-f]+ 2902 0f80 0000 0100 asr r0,r1,0x100
0x[0-9a-f]+ 2e02 7080 ffff feff asr r0,0xfffffeff,r2
0x[0-9a-f]+ 2e02 7f80 0000 0100 asr r0,0x100,0x100
0x[0-9a-f]+ 2902 0f80 0000 0000 asr r0,r1,0
68: ARC_32_ME foo
0x[0-9a-f]+ 28c2 0080 asr r0,r0,r2
0x[0-9a-f]+ 2bc2 0140 asr r3,r3,r5
0x[0-9a-f]+ 2ec2 0201 asr.eq r6,r6,r8
0x[0-9a-f]+ 29c2 12c1 asr.eq r9,r9,r11
0x[0-9a-f]+ 2cc2 1382 asr.ne r12,r12,r14
0x[0-9a-f]+ 2fc2 1442 asr.ne r15,r15,r17
0x[0-9a-f]+ 2ac2 2503 asr.p r18,r18,r20
0x[0-9a-f]+ 2dc2 25c3 asr.p r21,r21,r23
0x[0-9a-f]+ 28c2 3684 asr.n r24,r24,gp
0x[0-9a-f]+ 2bc2 3744 asr.n fp,fp,ilink
0x[0-9a-f]+ 2ec2 37c5 asr.c r30,r30,blink
0x[0-9a-f]+ 2bc2 00c5 asr.c r3,r3,r3
0x[0-9a-f]+ 2bc2 0205 asr.c r3,r3,r8
0x[0-9a-f]+ 2bc2 0106 asr.nc r3,r3,r4
0x[0-9a-f]+ 2cc2 0106 asr.nc r4,r4,r4
0x[0-9a-f]+ 2cc2 01c6 asr.nc r4,r4,r7
0x[0-9a-f]+ 2cc2 0147 asr.v r4,r4,r5
0x[0-9a-f]+ 2dc2 0147 asr.v r5,r5,r5
0x[0-9a-f]+ 2dc2 0148 asr.nv r5,r5,r5
0x[0-9a-f]+ 2dc2 0148 asr.nv r5,r5,r5
0x[0-9a-f]+ 2ec2 0009 asr.gt r6,r6,r0
0x[0-9a-f]+ 28c2 002a asr.ge r0,r0,0
0x[0-9a-f]+ 29c2 006b asr.lt r1,r1,0x1
0x[0-9a-f]+ 2bc2 00ed asr.hi r3,r3,0x3
0x[0-9a-f]+ 2cc2 012e asr.ls r4,r4,0x4
0x[0-9a-f]+ 2dc2 016f asr.pnz r5,r5,0x5
0x[0-9a-f]+ 2902 8080 asr.f r0,r1,r2
0x[0-9a-f]+ 2942 8040 asr.f r0,r1,0x1
0x[0-9a-f]+ 2e02 f080 0000 0001 asr.f r0,0x1,r2
0x[0-9a-f]+ 2902 80be asr.f 0,r1,r2
0x[0-9a-f]+ 2902 8f80 0000 0200 asr.f r0,r1,0x200
0x[0-9a-f]+ 2e02 f080 0000 0200 asr.f r0,0x200,r2
0x[0-9a-f]+ 29c2 8081 asr.f.eq r1,r1,r2
0x[0-9a-f]+ 28c2 8022 asr.f.ne r0,r0,0
0x[0-9a-f]+ 2ac2 808b asr.f.lt r2,r2,r2
0x[0-9a-f]+ 2ec2 f0a9 0000 0001 asr.f.gt 0,0x1,0x2
0x[0-9a-f]+ 2ec2 ff8c 0000 0200 asr.f.le 0,0x200,0x200
0x[0-9a-f]+ 2ec2 f0aa 0000 0200 asr.f.ge 0,0x200,0x2

83
gas/testsuite/gas/arc/asr.s
View File

@ -1,38 +1,63 @@
# asr test
asr r0,r1
asr fp,sp
asr r0,r1,r2
asr r26,fp,sp
asr ilink1,ilink2,blink
asr r0,0
asr r1,-1
asr 0,r2
asr -1,r3
asr r4,255
asr 255,r5
asr r6,-256
asr -256,r7
asr r0,r1,0
asr r0,0,r2
asr 0,r1,r2
asr r0,r1,-1
asr r0,-1,r2
asr r0,r1,255
asr r0,255,r2
asr r0,r1,-256
asr r0,-256,r2
asr r8,256
asr r9,-257
asr r11,0x42424242
asr r0,r1,256
asr r0,-257,r2
asr 255,256
asr r0,256,256
asr r0,foo
asr r0,r1,foo
asr.eq r10,r11
asr.ne r12,r13
asr.lt r14,0
asr.gt r15,512
asr.al r0,r0,r2
asr.ra r3,r3,r5
asr.eq r6,r6,r8
asr.z r9,r9,r11
asr.ne r12,r12,r14
asr.nz r15,r15,r17
asr.pl r18,r18,r20
asr.p r21,r21,r23
asr.mi r24,r24,r26
asr.n r27,r27,r29
asr.cs r30,r30,r31
asr.c r3,r3,r3
asr.lo r3,r3,r8
asr.cc r3,r3,r4
asr.nc r4,r4,r4
asr.hs r4,r4,r7
asr.vs r4,r4,r5
asr.v r5,r5,r5
asr.vc r5,r5,r5
asr.nv r5,r5,r5
asr.gt r6,r6,r0
asr.ge r0,r0,0
asr.lt r1,r1,1
asr.hi r3,r3,3
asr.ls r4,r4,4
asr.pnz r5,r5,5
asr.f r0,r1
asr.f r2,1
asr.f 0,r4
asr.f r5,512
asr.f 512,512
asr.f r0,r1,r2
asr.f r0,r1,1
asr.f r0,1,r2
asr.f 0,r1,r2
asr.f r0,r1,512
asr.f r0,512,r2
asr.eq.f r0,r1
asr.ne.f r1,0
asr.lt.f 0,r2
asr.le.f r0,512
asr.n.f 512,512
asr.eq.f r1,r1,r2
asr.ne.f r0,r0,0
asr.lt.f r2,r2,r2
asr.gt.f 0,1,2
asr.le.f 0,512,512
asr.ge.f 0,512,2

112
gas/testsuite/gas/arc/b.d
View File

@ -1,76 +1,46 @@
#as: -EL
#objdump: -dr -EL
#as: -mcpu=arc700
#objdump: -dr --show-raw-insn
.*: +file format elf32-.*arc
.*: +file format .*arc.*
Disassembly of section .text:
00000000 <text_label>:
0: 80 ff ff 27 27ffff80 b 0 <text_label>
4: 00 ff ff 27 27ffff00 b 0 <text_label>
8: 80 fe ff 27 27fffe80 b 0 <text_label>
c: 01 fe ff 27 27fffe01 bz 0 <text_label>
10: 81 fd ff 27 27fffd81 bz 0 <text_label>
14: 02 fd ff 27 27fffd02 bnz 0 <text_label>
18: 82 fc ff 27 27fffc82 bnz 0 <text_label>
1c: 03 fc ff 27 27fffc03 bp 0 <text_label>
20: 83 fb ff 27 27fffb83 bp 0 <text_label>
24: 04 fb ff 27 27fffb04 bn 0 <text_label>
28: 84 fa ff 27 27fffa84 bn 0 <text_label>
2c: 05 fa ff 27 27fffa05 bc 0 <text_label>
30: 85 f9 ff 27 27fff985 bc 0 <text_label>
34: 05 f9 ff 27 27fff905 bc 0 <text_label>
38: 86 f8 ff 27 27fff886 bnc 0 <text_label>
3c: 06 f8 ff 27 27fff806 bnc 0 <text_label>
40: 86 f7 ff 27 27fff786 bnc 0 <text_label>
44: 07 f7 ff 27 27fff707 bv 0 <text_label>
48: 87 f6 ff 27 27fff687 bv 0 <text_label>
4c: 08 f6 ff 27 27fff608 bnv 0 <text_label>
50: 88 f5 ff 27 27fff588 bnv 0 <text_label>
54: 09 f5 ff 27 27fff509 bgt 0 <text_label>
58: 8a f4 ff 27 27fff48a bge 0 <text_label>
5c: 0b f4 ff 27 27fff40b blt 0 <text_label>
60: 8c f3 ff 27 27fff38c ble 0 <text_label>
64: 0d f3 ff 27 27fff30d bhi 0 <text_label>
68: 8e f2 ff 27 27fff28e bls 0 <text_label>
6c: 0f f2 ff 27 27fff20f bpnz 0 <text_label>
70: a0 f1 ff 27 27fff1a0 b.d 0 <text_label>
74: 00 f1 ff 27 27fff100 b 0 <text_label>
78: c0 f0 ff 27 27fff0c0 b.jd 0 <text_label>
7c: 21 f0 ff 27 27fff021 bz.d 0 <text_label>
80: 82 ef ff 27 27ffef82 bnz 0 <text_label>
84: 46 ef ff 27 27ffef46 bnc.jd 0 <text_label>
0: 0001 0000 b 0 <text_label>
4: 07fc ffc0 b -4
8: 07f8 ffc0 b -8
c: 07f4 ffc1 beq -12
10: 07f0 ffc1 beq -16
14: 07ec ffc2 bne -20
18: 07e8 ffc2 bne -24
1c: 07e4 ffc3 bp -28
20: 07e0 ffc3 bp -32
24: 07dc ffc4 bn -36
28: 07d8 ffc4 bn -40
2c: 07d4 ffc5 bc -44
30: 07d0 ffc5 bc -48
34: 07cc ffc5 bc -52
38: 07c8 ffc6 bnc -56
3c: 07c4 ffc6 bnc -60
40: 07c0 ffc6 bnc -64
44: 07bc ffc7 bv -68
48: 07b8 ffc7 bv -72
4c: 07b4 ffc8 bnv -76
50: 07b0 ffc8 bnv -80
54: 07ac ffc9 bgt -84
58: 07a8 ffca bge -88
5c: 07a4 ffcb blt -92
60: 07a0 ffcc ble -96
64: 079c ffcd bhi -100
68: 0798 ffce bls -104
6c: 0794 ffcf bpnz -108
70: 0791 ffef b.d 0 <text_label>
74: 264a 7000 mov 0,0
78: 0789 ffcf b 0 <text_label>
7c: 0785 ffef b.d 0 <text_label>
80: 264a 7000 mov 0,0
84: 077c ffe1 b.deq -132
88: 264a 7000 mov 0,0
8c: 0774 ffc2 bne -140
90: 0770 ffe6 b.dnc -144
94: 264a 7000 mov 0,0

10
gas/testsuite/gas/arc/b.s
View File

@ -1,5 +1,5 @@
# b test
text_label:
b text_label
@ -32,9 +32,13 @@ text_label:
bpnz text_label
b.d text_label
nop
b.nd text_label
b.jd text_label
b.d text_label
nop
beq.d text_label
nop
bne.nd text_label
bcc.jd text_label
bcc.d text_label
nop

140
gas/testsuite/gas/arc/bic.d
View File

@ -1,85 +1,61 @@
#as: -EL
#objdump: -dr -EL
#as: -mcpu=arc700
#objdump: -dr --prefix-addresses --show-raw-insn
.*: +file format elf32-.*arc
.*: +file format .*arc.*
Disassembly of section .text:
00000000 <.text>:
0: 00 84 00 70 70008400 bic r0,r1,r2
4: 00 b8 4d 73 734db800 bic gp,fp,sp
8: 00 3e af 73 73af3e00 bic ilink1,ilink2,blink
c: 00 f8 1d 77 771df800 bic r56,r59,lp_count
10: 00 fe 00 70 7000fe00 bic r0,r1,0
14: 00 84 1f 70 701f8400 bic r0,0,r2
18: 00 84 e0 77 77e08400 bic 0,r1,r2
1c: ff ff 00 70 7000ffff bic r0,r1,-1
20: ff 85 1f 70 701f85ff bic r0,-1,r2
24: 00 84 e0 77 77e08400 bic 0,r1,r2
28: ff fe 00 70 7000feff bic r0,r1,255
2c: ff 84 1f 70 701f84ff bic r0,255,r2
30: 00 84 e0 77 77e08400 bic 0,r1,r2
34: 00 ff 00 70 7000ff00 bic r0,r1,-256
38: 00 85 1f 70 701f8500 bic r0,-256,r2
3c: 00 84 e0 77 77e08400 bic 0,r1,r2
40: 00 fc 00 70 7000fc00 bic r0,r1,0x100
44: 00 01 00 00
48: 00 04 1f 70 701f0400 bic r0,0xffff_feff,r2
4c: ff fe ff ff
50: ff fc 1f 70 701ffcff bic r0,255,0x100
54: 00 01 00 00
58: ff 7e 1f 70 701f7eff bic r0,0x100,255
5c: 00 01 00 00
60: 00 fc 00 70 7000fc00 bic r0,r1,0
64: 00 00 00 00
64: R_ARC_32 foo
68: 00 84 00 70 70008400 bic r0,r1,r2
6c: 00 0a 62 70 70620a00 bic r3,r4,r5
70: 01 90 c3 70 70c39001 bic.z r6,r7,r8
74: 01 16 25 71 71251601 bic.z r9,r10,r11
78: 02 9c 86 71 71869c02 bic.nz r12,r13,r14
7c: 02 22 e8 71 71e82202 bic.nz r15,r16,r17
80: 03 a8 49 72 7249a803 bic.p r18,r19,r20
84: 03 2e ab 72 72ab2e03 bic.p r21,r22,r23
88: 04 b4 0c 73 730cb404 bic.n r24,r25,gp
8c: 04 3a 6e 73 736e3a04 bic.n fp,sp,ilink1
90: 05 c0 cf 73 73cfc005 bic.c ilink2,blink,r32
94: 05 46 31 74 74314605 bic.c r33,r34,r35
98: 05 cc 92 74 7492cc05 bic.c r36,r37,r38
9c: 06 52 f4 74 74f45206 bic.nc r39,r40,r41
a0: 06 d8 55 75 7555d806 bic.nc r42,r43,r44
a4: 06 5e b7 75 75b75e06 bic.nc r45,r46,r47
a8: 07 e4 18 76 7618e407 bic.v r48,r49,r50
ac: 07 6a 1a 77 771a6a07 bic.v r56,r52,r53
b0: 08 f0 1b 77 771bf008 bic.nv r56,r55,r56
b4: 08 76 1d 77 771d7608 bic.nv r56,r58,r59
b8: 09 00 9e 77 779e0009 bic.gt lp_count,lp_count,r0
bc: 0a 7c 00 70 70007c0a bic.ge r0,r0,0
c0: 00 00 00 00
c4: 0b 02 3f 70 703f020b bic.lt r1,1,r1
c8: 01 00 00 00
cc: 0d 06 7f 70 707f060d bic.hi r3,3,r3
d0: 03 00 00 00
d4: 0e 08 df 77 77df080e bic.ls 0,4,r4
d8: 04 00 00 00
dc: 0f fc c2 77 77c2fc0f bic.pnz 0,r5,5
e0: 05 00 00 00
e4: 00 85 00 70 70008500 bic.f r0,r1,r2
e8: 01 fa 00 70 7000fa01 bic.f r0,r1,1
ec: 01 84 1e 70 701e8401 bic.f r0,1,r2
f0: 00 85 e0 77 77e08500 bic.f 0,r1,r2
f4: 00 fd 00 70 7000fd00 bic.f r0,r1,0x200
f8: 00 02 00 00
fc: 00 05 1f 70 701f0500 bic.f r0,0x200,r2
100: 00 02 00 00
104: 01 85 00 70 70008501 bic.z.f r0,r1,r2
108: 02 fd 00 70 7000fd02 bic.nz.f r0,r1,0
10c: 00 00 00 00
110: 0b 05 1f 70 701f050b bic.lt.f r0,0,r2
114: 00 00 00 00
118: 09 85 c0 77 77c08509 bic.gt.f 0,r1,r2
11c: 00 00 00 00 00000000
120: 0c fd 00 70 7000fd0c bic.le.f r0,r1,0x200
124: 00 02 00 00
128: 0a 05 1f 70 701f050a bic.ge.f r0,0x200,r2
12c: 00 02 00 00
0x[0-9a-f]+ 2106 0080 bic r0,r1,r2
0x[0-9a-f]+ 2306 371a bic gp,fp,sp
0x[0-9a-f]+ 2606 37dd bic ilink,r30,blink
0x[0-9a-f]+ 2146 0000 bic r0,r1,0
0x[0-9a-f]+ 2606 7080 0000 0000 bic r0,0,r2
0x[0-9a-f]+ 2106 00be bic 0,r1,r2
0x[0-9a-f]+ 2106 0f80 ffff ffff bic r0,r1,0xffffffff
0x[0-9a-f]+ 2606 7080 ffff ffff bic r0,0xffffffff,r2
0x[0-9a-f]+ 2106 0f80 0000 00ff bic r0,r1,0xff
0x[0-9a-f]+ 2606 7080 0000 00ff bic r0,0xff,r2
0x[0-9a-f]+ 2106 0f80 ffff ff00 bic r0,r1,0xffffff00
0x[0-9a-f]+ 2606 7080 ffff ff00 bic r0,0xffffff00,r2
0x[0-9a-f]+ 2106 0f80 0000 0100 bic r0,r1,0x100
0x[0-9a-f]+ 2606 7080 ffff feff bic r0,0xfffffeff,r2
0x[0-9a-f]+ 2606 7f80 0000 0100 bic r0,0x100,0x100
0x[0-9a-f]+ 2106 0f80 0000 0000 bic r0,r1,0
68: ARC_32_ME foo
0x[0-9a-f]+ 20c6 0080 bic r0,r0,r2
0x[0-9a-f]+ 23c6 0140 bic r3,r3,r5
0x[0-9a-f]+ 26c6 0201 biceq r6,r6,r8
0x[0-9a-f]+ 21c6 12c1 biceq r9,r9,r11
0x[0-9a-f]+ 24c6 1382 bicne r12,r12,r14
0x[0-9a-f]+ 27c6 1442 bicne r15,r15,r17
0x[0-9a-f]+ 22c6 2503 bicp r18,r18,r20
0x[0-9a-f]+ 25c6 25c3 bicp r21,r21,r23
0x[0-9a-f]+ 20c6 3684 bicn r24,r24,gp
0x[0-9a-f]+ 23c6 3744 bicn fp,fp,ilink
0x[0-9a-f]+ 26c6 37c5 bicc r30,r30,blink
0x[0-9a-f]+ 23c6 00c5 bicc r3,r3,r3
0x[0-9a-f]+ 23c6 0205 bicc r3,r3,r8
0x[0-9a-f]+ 23c6 0106 bicnc r3,r3,r4
0x[0-9a-f]+ 24c6 0106 bicnc r4,r4,r4
0x[0-9a-f]+ 24c6 01c6 bicnc r4,r4,r7
0x[0-9a-f]+ 24c6 0147 bicv r4,r4,r5
0x[0-9a-f]+ 25c6 0147 bicv r5,r5,r5
0x[0-9a-f]+ 25c6 0148 bicnv r5,r5,r5
0x[0-9a-f]+ 25c6 0148 bicnv r5,r5,r5
0x[0-9a-f]+ 26c6 0009 bicgt r6,r6,r0
0x[0-9a-f]+ 20c6 002a bicge r0,r0,0
0x[0-9a-f]+ 21c6 006b biclt r1,r1,0x1
0x[0-9a-f]+ 23c6 00ed bichi r3,r3,0x3
0x[0-9a-f]+ 24c6 012e bicls r4,r4,0x4
0x[0-9a-f]+ 25c6 016f bicpnz r5,r5,0x5
0x[0-9a-f]+ 2106 8080 bic.f r0,r1,r2
0x[0-9a-f]+ 2146 8040 bic.f r0,r1,0x1
0x[0-9a-f]+ 2606 f080 0000 0001 bic.f r0,0x1,r2
0x[0-9a-f]+ 2106 80be bic.f 0,r1,r2
0x[0-9a-f]+ 2106 8f80 0000 0200 bic.f r0,r1,0x200
0x[0-9a-f]+ 2606 f080 0000 0200 bic.f r0,0x200,r2
0x[0-9a-f]+ 21c6 8081 bic.feq r1,r1,r2
0x[0-9a-f]+ 20c6 8022 bic.fne r0,r0,0
0x[0-9a-f]+ 22c6 808b bic.flt r2,r2,r2
0x[0-9a-f]+ 26c6 f0a9 0000 0001 bic.fgt 0,0x1,0x2
0x[0-9a-f]+ 26c6 ff8c 0000 0200 bic.fle 0,0x200,0x200
0x[0-9a-f]+ 26c6 f0aa 0000 0200 bic.fge 0,0x200,0x2

69
gas/testsuite/gas/arc/bic.s
View File

@ -3,55 +3,50 @@
bic r0,r1,r2
bic r26,fp,sp
bic ilink1,ilink2,blink
bic r56,r59,lp_count
bic r0,r1,0
bic r0,0,r2
bic 0,r1,r2
bic r0,r1,-1
bic r0,-1,r2
bic -1,r1,r2
bic r0,r1,255
bic r0,255,r2
bic 255,r1,r2
bic r0,r1,-256
bic r0,-256,r2
bic -256,r1,r2
bic r0,r1,256
bic r0,-257,r2
bic r0,255,256
bic r0,256,255
bic r0,256,256
bic r0,r1,foo
bic.al r0,r1,r2
bic.ra r3,r4,r5
bic.eq r6,r7,r8
bic.z r9,r10,r11
bic.ne r12,r13,r14
bic.nz r15,r16,r17
bic.pl r18,r19,r20
bic.p r21,r22,r23
bic.mi r24,r25,r26
bic.n r27,r28,r29
bic.cs r30,r31,r32
bic.c r33,r34,r35
bic.lo r36,r37,r38
bic.cc r39,r40,r41
bic.nc r42,r43,r44
bic.hs r45,r46,r47
bic.vs r48,r49,r50
bic.v r56,r52,r53
bic.vc r56,r55,r56
bic.nv r56,r58,r59
bic.gt r60,r60,r0
bic.al r0,r0,r2
bic.ra r3,r3,r5
bic.eq r6,r6,r8
bic.z r9,r9,r11
bic.ne r12,r12,r14
bic.nz r15,r15,r17
bic.pl r18,r18,r20
bic.p r21,r21,r23
bic.mi r24,r24,r26
bic.n r27,r27,r29
bic.cs r30,r30,r31
bic.c r3,r3,r3
bic.lo r3,r3,r8
bic.cc r3,r3,r4
bic.nc r4,r4,r4
bic.hs r4,r4,r7
bic.vs r4,r4,r5
bic.v r5,r5,r5
bic.vc r5,r5,r5
bic.nv r5,r5,r5
bic.gt r6,r6,r0
bic.ge r0,r0,0
bic.lt r1,1,r1
bic.hi r3,3,r3
bic.ls 4,4,r4
bic.pnz 5,r5,5
bic.lt r1,r1,1
bic.hi r3,r3,3
bic.ls r4,r4,4
bic.pnz r5,r5,5
bic.f r0,r1,r2
bic.f r0,r1,1
@ -60,9 +55,9 @@
bic.f r0,r1,512
bic.f r0,512,r2
bic.eq.f r0,r1,r2
bic.ne.f r0,r1,0
bic.lt.f r0,0,r2
bic.gt.f 0,r1,r2
bic.le.f r0,r1,512
bic.ge.f r0,512,r2
bic.eq.f r1,r1,r2
bic.ne.f r0,r0,0
bic.lt.f r2,r2,r2
bic.gt.f 0,1,2
bic.le.f 0,512,512
bic.ge.f 0,512,2

114
gas/testsuite/gas/arc/bl.d
View File

@ -1,76 +1,46 @@
#as: -EL
#objdump: -dr -EL
#as: -mcpu=arc700
#objdump: -dr --show-raw-insn
.*: +file format elf32-.*arc
.*: +file format .*arc.*
Disassembly of section .text:
00000000 <text_label>:
0: 80 ff ff 2f 2fffff80 bl 0 <text_label>
4: 00 ff ff 2f 2fffff00 bl 0 <text_label>
8: 80 fe ff 2f 2ffffe80 bl 0 <text_label>
c: 01 fe ff 2f 2ffffe01 blz 0 <text_label>
10: 81 fd ff 2f 2ffffd81 blz 0 <text_label>
14: 02 fd ff 2f 2ffffd02 blnz 0 <text_label>
18: 82 fc ff 2f 2ffffc82 blnz 0 <text_label>
1c: 03 fc ff 2f 2ffffc03 blp 0 <text_label>
20: 83 fb ff 2f 2ffffb83 blp 0 <text_label>
24: 04 fb ff 2f 2ffffb04 bln 0 <text_label>
28: 84 fa ff 2f 2ffffa84 bln 0 <text_label>
2c: 05 fa ff 2f 2ffffa05 blc 0 <text_label>
30: 85 f9 ff 2f 2ffff985 blc 0 <text_label>
34: 05 f9 ff 2f 2ffff905 blc 0 <text_label>
38: 86 f8 ff 2f 2ffff886 blnc 0 <text_label>
3c: 06 f8 ff 2f 2ffff806 blnc 0 <text_label>
40: 86 f7 ff 2f 2ffff786 blnc 0 <text_label>
44: 07 f7 ff 2f 2ffff707 blv 0 <text_label>
48: 87 f6 ff 2f 2ffff687 blv 0 <text_label>
4c: 08 f6 ff 2f 2ffff608 blnv 0 <text_label>
50: 88 f5 ff 2f 2ffff588 blnv 0 <text_label>
54: 09 f5 ff 2f 2ffff509 blgt 0 <text_label>
58: 8a f4 ff 2f 2ffff48a blge 0 <text_label>
5c: 0b f4 ff 2f 2ffff40b bllt 0 <text_label>
60: 8c f3 ff 2f 2ffff38c blle 0 <text_label>
64: 0d f3 ff 2f 2ffff30d blhi 0 <text_label>
68: 8e f2 ff 2f 2ffff28e blls 0 <text_label>
6c: 0f f2 ff 2f 2ffff20f blpnz 0 <text_label>
70: a0 f1 ff 2f 2ffff1a0 bl.d 0 <text_label>
74: 00 f1 ff 2f 2ffff100 bl 0 <text_label>
78: c0 f0 ff 2f 2ffff0c0 bl.jd 0 <text_label>
7c: 21 f0 ff 2f 2ffff021 blz.d 0 <text_label>
80: 82 ef ff 2f 2fffef82 blnz 0 <text_label>
84: 46 ef ff 2f 2fffef46 blnc.jd 0 <text_label>
[0-9a-f]+ <text_label>:
0: 0802 0000 bl 0 <text_label>
4: 0ffc ffc0 bl 0 <text_label>
8: 0ff8 ffc0 bl 0 <text_label>
c: 0ff4 ffc1 bleq 0 <text_label>
10: 0ff0 ffc1 bleq 0 <text_label>
14: 0fec ffc2 blne 0 <text_label>
18: 0fe8 ffc2 blne 0 <text_label>
1c: 0fe4 ffc3 blp 0 <text_label>
20: 0fe0 ffc3 blp 0 <text_label>
24: 0fdc ffc4 bln 0 <text_label>
28: 0fd8 ffc4 bln 0 <text_label>
2c: 0fd4 ffc5 blc 0 <text_label>
30: 0fd0 ffc5 blc 0 <text_label>
34: 0fcc ffc5 blc 0 <text_label>
38: 0fc8 ffc6 blnc 0 <text_label>
3c: 0fc4 ffc6 blnc 0 <text_label>
40: 0fc0 ffc6 blnc 0 <text_label>
44: 0fbc ffc7 blv 0 <text_label>
48: 0fb8 ffc7 blv 0 <text_label>
4c: 0fb4 ffc8 blnv 0 <text_label>
50: 0fb0 ffc8 blnv 0 <text_label>
54: 0fac ffc9 blgt 0 <text_label>
58: 0fa8 ffca blge 0 <text_label>
5c: 0fa4 ffcb bllt 0 <text_label>
60: 0fa0 ffcc blle 0 <text_label>
64: 0f9c ffcd blhi 0 <text_label>
68: 0f98 ffce blls 0 <text_label>
6c: 0f94 ffcf blpnz 0 <text_label>
70: 0f92 ffef bl.d 0 <text_label>
74: 78e0 nop_s
76: 0f8e ffcf bl 0 <text_label>
7a: 78e0 nop_s
7c: 0f84 ffe1 bleq.d 0 <text_label>
80: 78e0 nop_s
82: 0f80 ffc2 blne 0 <text_label>
86: 78e0 nop_s
88: 0f78 ffe6 blnc.d 0 <text_label>
8c: 78e0 nop_s

10
gas/testsuite/gas/arc/bl.s
View File

@ -1,5 +1,5 @@
# bl test
text_label:
bl text_label
@ -32,9 +32,13 @@ text_label:
blpnz text_label
bl.d text_label
nop_s
bl.nd text_label
bl.jd text_label
nop_s
bleq.d text_label
nop_s
blne.nd text_label
blcc.jd text_label
nop_s
blcc.d text_label
nop_s

45
gas/testsuite/gas/arc/branch.d
View File

@ -1,45 +0,0 @@
#objdump: -dr
#name: @OC@
# Test the @OC@ insn.
.*: +file format elf32-.*arc
Disassembly of section .text:
00000000 <text_label> @IC+7@ffff80 @OC@ 00000000 <text_label>
00000004 <text_label\+4> @IC+7@ffff00 @OC@ 00000000 <text_label>
00000008 <text_label\+8> @IC+7@fffe80 @OC@ 00000000 <text_label>
0000000c <text_label\+c> @IC+7@fffe01 @OC@eq 00000000 <text_label>
00000010 <text_label\+10> @IC+7@fffd81 @OC@eq 00000000 <text_label>
00000014 <text_label\+14> @IC+7@fffd02 @OC@ne 00000000 <text_label>
00000018 <text_label\+18> @IC+7@fffc82 @OC@ne 00000000 <text_label>
0000001c <text_label\+1c> @IC+7@fffc03 @OC@p 00000000 <text_label>
00000020 <text_label\+20> @IC+7@fffb83 @OC@p 00000000 <text_label>
00000024 <text_label\+24> @IC+7@fffb04 @OC@n 00000000 <text_label>
00000028 <text_label\+28> @IC+7@fffa84 @OC@n 00000000 <text_label>
0000002c <text_label\+2c> @IC+7@fffa05 @OC@c 00000000 <text_label>
00000030 <text_label\+30> @IC+7@fff985 @OC@c 00000000 <text_label>
00000034 <text_label\+34> @IC+7@fff905 @OC@c 00000000 <text_label>
00000038 <text_label\+38> @IC+7@fff886 @OC@nc 00000000 <text_label>
0000003c <text_label\+3c> @IC+7@fff806 @OC@nc 00000000 <text_label>
00000040 <text_label\+40> @IC+7@fff786 @OC@nc 00000000 <text_label>
00000044 <text_label\+44> @IC+7@fff707 @OC@v 00000000 <text_label>
00000048 <text_label\+48> @IC+7@fff687 @OC@v 00000000 <text_label>
0000004c <text_label\+4c> @IC+7@fff608 @OC@nv 00000000 <text_label>
00000050 <text_label\+50> @IC+7@fff588 @OC@nv 00000000 <text_label>
00000054 <text_label\+54> @IC+7@fff509 @OC@gt 00000000 <text_label>
00000058 <text_label\+58> @IC+7@fff48a @OC@ge 00000000 <text_label>
0000005c <text_label\+5c> @IC+7@fff40b @OC@lt 00000000 <text_label>
00000060 <text_label\+60> @IC+7@fff38c @OC@le 00000000 <text_label>
00000064 <text_label\+64> @IC+7@fff30d @OC@hi 00000000 <text_label>
00000068 <text_label\+68> @IC+7@fff28e @OC@ls 00000000 <text_label>
0000006c <text_label\+6c> @IC+7@fff20f @OC@pnz 00000000 <text_label>
00000070 <text_label\+70> @IC+7@ffff80 @OC@ 00000070 <text_label\+70>
RELOC: 00000070 R_ARC_B22_PCREL external_text_label
00000074 <text_label\+74> @IC+0@000000 @OC@ 00000078 <text_label\+78>
00000078 <text_label\+78> @IC+7@fff0a0 @OC@.d 00000000 <text_label>
0000007c <text_label\+7c> @IC+7@fff000 @OC@ 00000000 <text_label>
00000080 <text_label\+80> @IC+7@ffefc0 @OC@.jd 00000000 <text_label>
00000084 <text_label\+84> @IC+7@ffef21 @OC@eq.d 00000000 <text_label>
00000088 <text_label\+88> @IC+7@ffee82 @OC@ne 00000000 <text_label>
0000008c <text_label\+8c> @IC+7@ffee46 @OC@nc.jd 00000000 <text_label>

47
gas/testsuite/gas/arc/branch.s
View File

@ -1,47 +0,0 @@
# @OC@ test
text_label:
# Condition tests
@OC@ text_label
@OC@al text_label
@OC@ra text_label
@OC@eq text_label
@OC@z text_label
@OC@ne text_label
@OC@nz text_label
@OC@pl text_label
@OC@p text_label
@OC@mi text_label
@OC@n text_label
@OC@cs text_label
@OC@c text_label
@OC@lo text_label
@OC@cc text_label
@OC@nc text_label
@OC@hs text_label
@OC@vs text_label
@OC@v text_label
@OC@vc text_label
@OC@nv text_label
@OC@gt text_label
@OC@ge text_label
@OC@lt text_label
@OC@le text_label
@OC@hi text_label
@OC@ls text_label
@OC@pnz text_label
@OC@ external_text_label
@OC@ 0
# Delay slots
@OC@.d text_label
@OC@.nd text_label
@OC@.jd text_label
# Condition tests and delay slots
@OC@eq.d text_label
@OC@ne.nd text_label
@OC@cc.jd text_label

14
gas/testsuite/gas/arc/brk.d
View File

@ -1,11 +1,9 @@
#as: -EL -marc7
#objdump: -dr -EL
#as: -mcpu=arc700
#objdump: -dr --prefix-addresses --show-raw-insn
.*: +file format elf32-.*arc
.*: +file format .*arc.*
Disassembly of section .text:
00000000 <main>:
0: 00 84 00 40 40008400 add r0,r1,r2
4: 00 fe ff 1f 1ffffe00 brk
8: 00 0a 62 50 50620a00 sub r3,r4,r5
0x00000000 2100 0080 add r0,r1,r2
0x00000004 256f 003f brk
0x00000008 2402 0143 sub r3,r4,r5

4
gas/testsuite/gas/arc/brk.s
View File

@ -1,7 +1,5 @@
# brk test
main:
add r0,r1,r2
add r0,r1,r2
brk
sub r3,r4,r5

67
gas/testsuite/gas/arc/extb.d
View File

@ -1,51 +1,22 @@
#as: -EL
#objdump: -dr -EL
#as: -mcpu=arc700
#objdump: -dr --prefix-addresses --show-raw-insn
.*: +file format elf32-.*arc
.*: +file format .*arc.*
Disassembly of section .text:
00000000 <.text>:
0: 00 8e 00 18 18008e00 extb r0,r1
4: 00 0e 6e 1b 1b6e0e00 extb fp,sp
8: 00 8e 1f 18 181f8e00 extb r0,0
c: ff 8f 3f 18 183f8fff extb r1,-1
10: 00 0e e1 1f 1fe10e00 extb 0,r2
14: 00 8e e1 1f 1fe18e00 extb 0,r3
18: ff 8e 9f 18 189f8eff extb r4,255
1c: 00 8e e2 1f 1fe28e00 extb 0,r5
20: 00 8f df 18 18df8f00 extb r6,-256
24: 00 8e e3 1f 1fe38e00 extb 0,r7
28: 00 0e 1f 19 191f0e00 extb r8,0x100
2c: 00 01 00 00
30: 00 0e 3f 19 193f0e00 extb r9,0xffff_feff
34: ff fe ff ff
38: 00 0e 7f 19 197f0e00 extb r11,0x4242_4242
3c: 42 42 42 42
40: 00 0e ff 1f 1fff0e00 extb 0,0x100
44: 00 01 00 00
48: 00 0e 1f 18 181f0e00 extb r0,0
4c: 00 00 00 00
4c: R_ARC_32 foo
50: 01 8e 45 19 19458e01 extb.z r10,r11
54: 02 8e 86 19 19868e02 extb.nz r12,r13
58: 0b 0e df 19 19df0e0b extb.lt r14,0
5c: 00 00 00 00
60: 09 0e ff 19 19ff0e09 extb.gt r15,0x200
64: 00 02 00 00
68: 00 8f 00 18 18008f00 extb.f r0,r1
6c: 01 8e 5e 18 185e8e01 extb.f r2,1
70: 00 0f e2 1f 1fe20f00 extb.f 0,r4
74: 00 0f bf 18 18bf0f00 extb.f r5,0x200
78: 00 02 00 00
7c: 00 0f df 1f 1fdf0f00 extb.f 0,0x200
80: 00 02 00 00
84: 01 8f 00 18 18008f01 extb.z.f r0,r1
88: 02 0f 3f 18 183f0f02 extb.nz.f r1,0
8c: 00 00 00 00
90: 0b 0f c1 1f 1fc10f0b extb.lt.f 0,r2
94: 00 00 00 00 00000000
98: 0c 0f 1f 18 181f0f0c extb.le.f r0,0x200
9c: 00 02 00 00
a0: 04 0f df 1f 1fdf0f04 extb.n.f 0,0x200
a4: 00 02 00 00
0x[0-9a-f]+ 202f 0047 extb r0,r1
0x[0-9a-f]+ 232f 3707 extb fp,sp
0x[0-9a-f]+ 206f 0007 extb r0,0
0x[0-9a-f]+ 212f 0f87 ffff ffff extb r1,0xffffffff
0x[0-9a-f]+ 262f 7087 extb 0,r2
0x[0-9a-f]+ 242f 0f87 0000 00ff extb r4,0xff
0x[0-9a-f]+ 262f 0f87 ffff ff00 extb r6,0xffffff00
0x[0-9a-f]+ 202f 1f87 0000 0100 extb r8,0x100
0x[0-9a-f]+ 212f 1f87 ffff feff extb r9,0xfffffeff
0x[0-9a-f]+ 232f 1f87 4242 4242 extb r11,0x42424242
0x[0-9a-f]+ 202f 0f87 0000 0000 extb r0,0
44: ARC_32_ME foo
0x[0-9a-f]+ 202f 8047 extb.f r0,r1
0x[0-9a-f]+ 226f 8047 extb.f r2,0x1
0x[0-9a-f]+ 262f f107 extb.f 0,r4
0x[0-9a-f]+ 252f 8f87 0000 0200 extb.f r5,0x200

17
gas/testsuite/gas/arc/extb.s
View File

@ -6,33 +6,16 @@
extb r0,0
extb r1,-1
extb 0,r2
extb -1,r3
extb r4,255
extb 255,r5
extb r6,-256
extb -256,r7
extb r8,256
extb r9,-257
extb r11,0x42424242
extb 255,256
extb r0,foo
extb.eq r10,r11
extb.ne r12,r13
extb.lt r14,0
extb.gt r15,512
extb.f r0,r1
extb.f r2,1
extb.f 0,r4
extb.f r5,512
extb.f 512,512
extb.eq.f r0,r1
extb.ne.f r1,0
extb.lt.f 0,r2
extb.le.f r0,512
extb.n.f 512,512

5
gas/testsuite/gas/arc/extensions.d
View File

@ -1,5 +1,6 @@
#as: -EL -marc8
#as: -EL
#objdump: -dr -EL
#skip: *-*-*
.*: +file format elf32-.*arc
@ -9,4 +10,4 @@ Disassembly of section .text:
0: 12 02 00 40 40000212 add.isbusy r0,r0,r1
4: 00 02 60 45 45600200 add rwscreg,r0,r1
8: 00 d8 00 40 4000d800 add r0,r1,roscreg
c: 00 02 a0 45 45a00200 add woscreg,r0,r1
c: 00 02 a0 45 45a00200 add woscreg,r0,r1

67
gas/testsuite/gas/arc/extw.d
View File

@ -1,51 +1,22 @@
#as: -EL
#objdump: -dr -EL
#as: -mcpu=arc700
#objdump: -dr --prefix-addresses --show-raw-insn
.*: +file format elf32-.*arc
.*: +file format .*arc.*
Disassembly of section .text:
00000000 <.text>:
0: 00 90 00 18 18009000 extw r0,r1
4: 00 10 6e 1b 1b6e1000 extw fp,sp
8: 00 90 1f 18 181f9000 extw r0,0
c: ff 91 3f 18 183f91ff extw r1,-1
10: 00 10 e1 1f 1fe11000 extw 0,r2
14: 00 90 e1 1f 1fe19000 extw 0,r3
18: ff 90 9f 18 189f90ff extw r4,255
1c: 00 90 e2 1f 1fe29000 extw 0,r5
20: 00 91 df 18 18df9100 extw r6,-256
24: 00 90 e3 1f 1fe39000 extw 0,r7
28: 00 10 1f 19 191f1000 extw r8,0x100
2c: 00 01 00 00
30: 00 10 3f 19 193f1000 extw r9,0xffff_feff
34: ff fe ff ff
38: 00 10 7f 19 197f1000 extw r11,0x4242_4242
3c: 42 42 42 42
40: 00 10 ff 1f 1fff1000 extw 0,0x100
44: 00 01 00 00
48: 00 10 1f 18 181f1000 extw r0,0
4c: 00 00 00 00
4c: R_ARC_32 foo
50: 01 90 45 19 19459001 extw.z r10,r11
54: 02 90 86 19 19869002 extw.nz r12,r13
58: 0b 10 df 19 19df100b extw.lt r14,0
5c: 00 00 00 00
60: 09 10 ff 19 19ff1009 extw.gt r15,0x200
64: 00 02 00 00
68: 00 91 00 18 18009100 extw.f r0,r1
6c: 01 90 5e 18 185e9001 extw.f r2,1
70: 00 11 e2 1f 1fe21100 extw.f 0,r4
74: 00 11 bf 18 18bf1100 extw.f r5,0x200
78: 00 02 00 00
7c: 00 11 df 1f 1fdf1100 extw.f 0,0x200
80: 00 02 00 00
84: 01 91 00 18 18009101 extw.z.f r0,r1
88: 02 11 3f 18 183f1102 extw.nz.f r1,0
8c: 00 00 00 00
90: 0b 11 c1 1f 1fc1110b extw.lt.f 0,r2
94: 00 00 00 00 00000000
98: 0c 11 1f 18 181f110c extw.le.f r0,0x200
9c: 00 02 00 00
a0: 04 11 df 1f 1fdf1104 extw.n.f 0,0x200
a4: 00 02 00 00
0x00000000 202f 0048 ext[hw]+ r0,r1
0x00000004 232f 3708 ext[hw]+ fp,sp
0x00000008 206f 0008 ext[hw]+ r0,0
0x0000000c 212f 0f88 ffff ffff ext[hw]+ r1,0xffffffff
0x00000014 262f 7088 ext[hw]+ 0,r2
0x00000018 242f 0f88 0000 00ff ext[hw]+ r4,0xff
0x00000020 262f 0f88 ffff ff00 ext[hw]+ r6,0xffffff00
0x00000028 202f 1f88 0000 0100 ext[hw]+ r8,0x100
0x00000030 212f 1f88 ffff feff ext[hw]+ r9,0xfffffeff
0x00000038 232f 1f88 4242 4242 ext[hw]+ r11,0x42424242
0x00000040 202f 0f88 0000 0000 ext[hw]+ r0,0
44: ARC_32_ME foo
0x00000048 202f 8048 ext[hw]+.f r0,r1
0x0000004c 226f 8048 ext[hw]+.f r2,0x1
0x00000050 262f f108 ext[hw]+.f 0,r4
0x00000054 252f 8f88 0000 0200 ext[hw]+.f r5,0x200

17
gas/testsuite/gas/arc/extw.s
View File

@ -6,33 +6,16 @@
extw r0,0
extw r1,-1
extw 0,r2
extw -1,r3
extw r4,255
extw 255,r5
extw r6,-256
extw -256,r7
extw r8,256
extw r9,-257
extw r11,0x42424242
extw 255,256
extw r0,foo
extw.eq r10,r11
extw.ne r12,r13
extw.lt r14,0
extw.gt r15,512
extw.f r0,r1
extw.f r2,1
extw.f 0,r4
extw.f r5,512
extw.f 512,512
extw.eq.f r0,r1
extw.ne.f r1,0
extw.lt.f 0,r2
extw.le.f r0,512
extw.n.f 512,512

58
gas/testsuite/gas/arc/flag.d
View File

@ -1,38 +1,26 @@
#as: -EL
#objdump: -dr -EL
#as: -mcpu=arc700
#objdump: -dr --prefix-addresses --show-raw-insn
.*: +file format elf32-.*arc
.*: +file format .*arc.*
Disassembly of section .text:
00000000 <.text>:
0: 00 00 a0 1f 1fa00000 flag r0
4: 01 80 bf 1f 1fbf8001 flag 1
8: 02 80 bf 1f 1fbf8002 flag 2
c: 04 80 bf 1f 1fbf8004 flag 4
10: 08 80 bf 1f 1fbf8008 flag 8
14: 10 80 bf 1f 1fbf8010 flag 16
18: 20 80 bf 1f 1fbf8020 flag 32
1c: 40 80 bf 1f 1fbf8040 flag 64
20: 80 80 bf 1f 1fbf8080 flag 128
24: 00 00 bf 1f 1fbf0000 flag 0x8000_0001
28: 01 00 00 80
2c: 0b 00 a0 1f 1fa0000b flag.lt r0
30: 09 00 bf 1f 1fbf0009 flag.gt 1
34: 01 00 00 00
38: 09 00 bf 1f 1fbf0009 flag.gt 2
3c: 02 00 00 00
40: 09 00 bf 1f 1fbf0009 flag.gt 4
44: 04 00 00 00
48: 09 00 bf 1f 1fbf0009 flag.gt 8
4c: 08 00 00 00
50: 09 00 bf 1f 1fbf0009 flag.gt 16
54: 10 00 00 00
58: 09 00 bf 1f 1fbf0009 flag.gt 32
5c: 20 00 00 00
60: 09 00 bf 1f 1fbf0009 flag.gt 64
64: 40 00 00 00
68: 09 00 bf 1f 1fbf0009 flag.gt 128
6c: 80 00 00 00
70: 0a 00 bf 1f 1fbf000a flag.ge 0x8000_0001
74: 01 00 00 80
0x[0-9a-f]+ 2029 0000 flag r0
0x[0-9a-f]+ 2069 0040 flag 0x1
0x[0-9a-f]+ 2069 0080 flag 0x2
0x[0-9a-f]+ 2069 0100 flag 0x4
0x[0-9a-f]+ 2069 0200 flag 0x8
0x[0-9a-f]+ 2069 0400 flag 0x10
0x[0-9a-f]+ 2069 0800 flag 0x20
0x[0-9a-f]+ 20a9 0001 flag 64
0x[0-9a-f]+ 20a9 0002 flag 128
0x[0-9a-f]+ 2029 0f80 8000 0001 flag 0x80000001
0x[0-9a-f]+ 20e9 000b flag.lt r0
0x[0-9a-f]+ 20e9 0069 flag.gt 0x1
0x[0-9a-f]+ 20e9 00a9 flag.gt 0x2
0x[0-9a-f]+ 20e9 0129 flag.gt 0x4
0x[0-9a-f]+ 20e9 0229 flag.gt 0x8
0x[0-9a-f]+ 20e9 0429 flag.gt 0x10
0x[0-9a-f]+ 20e9 0829 flag.gt 0x20
0x[0-9a-f]+ 20e9 0f89 0000 0040 flag.gt 0x40
0x[0-9a-f]+ 20e9 0f89 0000 0080 flag.gt 0x80
0x[0-9a-f]+ 20e9 0f8a 8000 0001 flag.ge 0x80000001

44
gas/testsuite/gas/arc/insn3.d
View File

@ -1,44 +0,0 @@
#objdump: -dr
#name: @OC@
# Test the @OC@ insn.
.*: +file format elf32-.*arc
Disassembly of section .text:
00000000 1800@I3+80@00 @OC@ r0,r1
00000004 1b6e@I3+00@00 @OC@ fp,sp
00000008 181f@I3+80@00 @OC@ r0,0
0000000c 183f@I3+81@ff @OC@ r1,-1
00000010 1fe1@I3+00@00 @OC@ 0,r2
00000014 1fe1@I3+81@ff @OC@ -1,r3
00000018 189f@I3+80@ff @OC@ r4,255
0000001c 1fe2@I3+80@ff @OC@ 255,r5
00000020 18df@I3+81@00 @OC@ r6,-256
00000024 1fe3@I3+81@00 @OC@ -256,r7
00000028 191f@I3+00@00 @OC@ r8,256
00000030 193f@I3+00@00 @OC@ r9,-257
00000038 1fc5@I3+00@00 @OC@ 511,r10
00000040 197f@I3+00@00 @OC@ r11,1111638594
00000048 1fc6@I3+00@00 @OC@ 305419896,r12
00000050 1fff@I3+00@ff @OC@ 255,256
00000058 1fdf@I3+80@ff @OC@ 256,255
00000060 181f@I3+00@00 @OC@ r0,0
RELOC: 00000064 R_ARC_32 foo
00000068 1945@I3+80@01 @OC@.eq r10,r11
0000006c 1986@I3+80@02 @OC@.ne r12,r13
00000070 19df@I3+00@0b @OC@.lt r14,0
00000078 19ff@I3+00@09 @OC@.gt r15,512
00000080 1800@I3+81@00 @OC@.f r0,r1
00000084 185e@I3+80@01 @OC@.f r2,1
00000088 1fa2@I3+00@00 @OC@.f 0,r4
0000008c 18bf@I3+01@00 @OC@.f r5,512
00000094 1fc3@I3+01@00 @OC@.f 512,r6
0000009c 1fdf@I3+01@00 @OC@.f 512,512
000000a4 1800@I3+81@01 @OC@.eq.f r0,r1
000000a8 183f@I3+01@02 @OC@.ne.f r1,0
000000b0 1fc1@I3+01@0b @OC@.lt.f 0,r2
000000b8 1fc1@I3+01@09 @OC@.gt.f 1,r2
000000c0 181f@I3+01@0c @OC@.le.f r0,512
000000c8 1fc1@I3+01@0a @OC@.ge.f 512,r2
000000d0 1fdf@I3+01@04 @OC@.n.f 512,512

52
gas/testsuite/gas/arc/insn3.s
View File

@ -1,52 +0,0 @@
# Insn 3 @OC@ test
# reg,reg
@OC@ r0,r1
@OC@ fp,sp
# shimm values
@OC@ r0,0
@OC@ r1,-1
@OC@ 0,r2
@OC@ -1,r3
@OC@ r4,255
@OC@ 255,r5
@OC@ r6,-256
@OC@ -256,r7
# limm values
@OC@ r8,256
@OC@ r9,-257
@OC@ 511,r10
@OC@ r11,0x42424242
@OC@ 0x12345678,r12
# shimm and limm
@OC@ 255,256
@OC@ 256,255
# symbols
@OC@ r0,foo
# conditional execution
@OC@.eq r10,r11
@OC@.ne r12,r13
@OC@.lt r14,0
@OC@.gt r15,512
# flag setting
@OC@.f r0,r1
@OC@.f r2,1
@OC@.f 0,r4
@OC@.f r5,512
@OC@.f 512,r6
@OC@.f 512,512
# conditional execution + flag setting
@OC@.eq.f r0,r1
@OC@.ne.f r1,0
@OC@.lt.f 0,r2
@OC@.gt.f 1,r2
@OC@.le.f r0,512
@OC@.ge.f 512,r2
@OC@.n.f 512,512

186
gas/testsuite/gas/arc/j.d
View File

@ -1,127 +1,67 @@
#as: -EL
#objdump: -dr -EL
#as: -mcpu=arc700
#objdump: -dr --show-raw-insn
.*: +file format elf32-.*arc
.*: +file format .*arc.*
Disassembly of section .text:
00000000 <text_label>:
0: 00 00 1f 38 381f0000 j 0 <text_label>
4: 00 00 00 00
4: R_ARC_B26 .text
8: 00 00 1f 38 381f0000 j 0 <text_label>
c: 00 00 00 00
c: R_ARC_B26 .text
10: 00 00 1f 38 381f0000 j 0 <text_label>
14: 00 00 00 00
14: R_ARC_B26 .text
18: 01 00 1f 38 381f0001 jz 0 <text_label>
1c: 00 00 00 00
1c: R_ARC_B26 .text
20: 01 00 1f 38 381f0001 jz 0 <text_label>
24: 00 00 00 00
24: R_ARC_B26 .text
28: 02 00 1f 38 381f0002 jnz 0 <text_label>
2c: 00 00 00 00
2c: R_ARC_B26 .text
30: 02 00 1f 38 381f0002 jnz 0 <text_label>
34: 00 00 00 00
34: R_ARC_B26 .text
38: 03 00 1f 38 381f0003 jp 0 <text_label>
3c: 00 00 00 00
3c: R_ARC_B26 .text
40: 03 00 1f 38 381f0003 jp 0 <text_label>
44: 00 00 00 00
44: R_ARC_B26 .text
48: 04 00 1f 38 381f0004 jn 0 <text_label>
4c: 00 00 00 00
4c: R_ARC_B26 .text
50: 04 00 1f 38 381f0004 jn 0 <text_label>
54: 00 00 00 00
54: R_ARC_B26 .text
58: 05 00 1f 38 381f0005 jc 0 <text_label>
5c: 00 00 00 00
5c: R_ARC_B26 .text
60: 05 00 1f 38 381f0005 jc 0 <text_label>
64: 00 00 00 00
64: R_ARC_B26 .text
68: 05 00 1f 38 381f0005 jc 0 <text_label>
6c: 00 00 00 00
6c: R_ARC_B26 .text
70: 06 00 1f 38 381f0006 jnc 0 <text_label>
74: 00 00 00 00
74: R_ARC_B26 .text
78: 06 00 1f 38 381f0006 jnc 0 <text_label>
7c: 00 00 00 00
7c: R_ARC_B26 .text
80: 06 00 1f 38 381f0006 jnc 0 <text_label>
84: 00 00 00 00
84: R_ARC_B26 .text
88: 07 00 1f 38 381f0007 jv 0 <text_label>
8c: 00 00 00 00
8c: R_ARC_B26 .text
90: 07 00 1f 38 381f0007 jv 0 <text_label>
94: 00 00 00 00
94: R_ARC_B26 .text
98: 08 00 1f 38 381f0008 jnv 0 <text_label>
9c: 00 00 00 00
9c: R_ARC_B26 .text
a0: 08 00 1f 38 381f0008 jnv 0 <text_label>
a4: 00 00 00 00
a4: R_ARC_B26 .text
a8: 09 00 1f 38 381f0009 jgt 0 <text_label>
ac: 00 00 00 00
ac: R_ARC_B26 .text
b0: 0a 00 1f 38 381f000a jge 0 <text_label>
b4: 00 00 00 00
b4: R_ARC_B26 .text
b8: 0b 00 1f 38 381f000b jlt 0 <text_label>
bc: 00 00 00 00
bc: R_ARC_B26 .text
c0: 0c 00 1f 38 381f000c jle 0 <text_label>
c4: 00 00 00 00
c4: R_ARC_B26 .text
c8: 0d 00 1f 38 381f000d jhi 0 <text_label>
cc: 00 00 00 00
cc: R_ARC_B26 .text
d0: 0e 00 1f 38 381f000e jls 0 <text_label>
d4: 00 00 00 00
d4: R_ARC_B26 .text
d8: 0f 00 1f 38 381f000f jpnz 0 <text_label>
dc: 00 00 00 00
dc: R_ARC_B26 .text
e0: 00 00 1f 38 381f0000 j 0 <text_label>
e4: 00 00 00 00
e4: R_ARC_B26 external_text_label
e8: 00 00 1f 38 381f0000 j 0 <text_label>
ec: 00 00 00 00
[0-9a-f]+ <text_label>:
0: 2020 0f80 0000 0000 j 0
4: ARC_32_ME text_label
8: 20e0 0f80 0000 0000 j 0
c: ARC_32_ME text_label
10: 20e0 0f80 0000 0000 j 0
14: ARC_32_ME text_label
18: 20e0 0f81 0000 0000 jeq 0
1c: ARC_32_ME text_label
20: 20e0 0f81 0000 0000 jeq 0
24: ARC_32_ME text_label
28: 20e0 0f82 0000 0000 jne 0
2c: ARC_32_ME text_label
30: 20e0 0f82 0000 0000 jne 0
34: ARC_32_ME text_label
38: 20e0 0f83 0000 0000 jp 0
3c: ARC_32_ME text_label
40: 20e0 0f83 0000 0000 jp 0
44: ARC_32_ME text_label
48: 20e0 0f84 0000 0000 jn 0
4c: ARC_32_ME text_label
50: 20e0 0f84 0000 0000 jn 0
54: ARC_32_ME text_label
58: 20e0 0f85 0000 0000 jc 0
5c: ARC_32_ME text_label
60: 20e0 0f85 0000 0000 jc 0
64: ARC_32_ME text_label
68: 20e0 0f85 0000 0000 jc 0
6c: ARC_32_ME text_label
70: 20e0 0f86 0000 0000 jnc 0
74: ARC_32_ME text_label
78: 20e0 0f86 0000 0000 jnc 0
7c: ARC_32_ME text_label
80: 20e0 0f86 0000 0000 jnc 0
84: ARC_32_ME text_label
88: 20e0 0f87 0000 0000 jv 0
8c: ARC_32_ME text_label
90: 20e0 0f87 0000 0000 jv 0
94: ARC_32_ME text_label
98: 20e0 0f88 0000 0000 jnv 0
9c: ARC_32_ME text_label
a0: 20e0 0f88 0000 0000 jnv 0
a4: ARC_32_ME text_label
a8: 20e0 0f89 0000 0000 jgt 0
ac: ARC_32_ME text_label
b0: 20e0 0f8a 0000 0000 jge 0
b4: ARC_32_ME text_label
b8: 20e0 0f8b 0000 0000 jlt 0
bc: ARC_32_ME text_label
c0: 20e0 0f8c 0000 0000 jle 0
c4: ARC_32_ME text_label
c8: 20e0 0f8d 0000 0000 jhi 0
cc: ARC_32_ME text_label
d0: 20e0 0f8e 0000 0000 jls 0
d4: ARC_32_ME text_label
d8: 20e0 0f8f 0000 0000 jpnz 0
dc: ARC_32_ME text_label
e0: 2020 0f80 0000 0000 j 0
e4: ARC_32_ME external_text_label
e8: 20a0 0000 j 0

4
gas/testsuite/gas/arc/j.s
View File

@ -1,6 +1,6 @@
# j test
text_label:
text_label:
j text_label
jal text_label

31
gas/testsuite/gas/arc/jl.d
View File

@ -1,25 +1,14 @@
#as: -EL -marc6
#objdump: -dr -EL
#as: -mcpu=archs
#objdump: -dr --show-raw-insn
.*: +file format elf32-.*arc
.*: +file format .*arc.*
Disassembly of section .text:
00000000 <text_label>:
0: 40 02 1f 38 381f0240 jl 0 <text_label>
4: 00 00 00 00
4: R_ARC_B26 .text
8: 40 03 1f 38 381f0340 jl.f 0 <text_label>
c: 00 00 00 00
c: R_ARC_B26 .text
10: 02 82 00 38 38008202 jlnz \[r1\]
14: 40 02 1f 38 381f0240 jl 0 <text_label>
18: 00 00 00 00
18: R_ARC_B26 .text
1c: 40 03 1f 38 381f0340 jl.f 0 <text_label>
20: 00 00 00 00
20: R_ARC_B26 .text
[0-9a-f]+ <text_label>:
0: 2022 0f80 0000 0000 jl 0
4: ARC_32_ME text_label
8: 20e3 0042 jlne.d \[r1\]
c: 78e0 nop_s
e: 20e2 0f80 0000 0000 jl 0
12: ARC_32_ME text_label

5
gas/testsuite/gas/arc/jl.s
View File

@ -3,7 +3,6 @@
text_label:
jl text_label
jl.f text_label
jlnz.nd [r1]
jlnz.d [r1]
nop_s
jlal text_label
jlal.f text_label

24
gas/testsuite/gas/arc/ld.d
View File

@ -1,16 +1,16 @@
#as: -EL
#objdump: -dr -EL
#as: -mcpu=arc700
#objdump: -dr --show-raw-insn
.*: +file format elf32-.*arc
.*: +file format .*arc.*
Disassembly of section .text:
00000000 <.text>:
0: 00 84 00 00 00008400 ld r0,\[r1,r2\]
4: 02 84 00 00 00008402 ldb r0,\[r1,r2\]
8: 08 88 21 00 00218808 ld.a r1,\[r3,r4\]
c: 05 06 21 00 00210605 ldw.x r1,\[r2,r3\]
10: 0d 88 41 00 0041880d ldw.x.a r2,\[r3,r4\]
14: 00 80 1f 08 081f8000 ld r0,\[0\]
18: 1e 80 00 08 0800801e ld r0,\[r1,30\]
1c: ec 01 21 08 082101ec ld r1,\[r2,-20\]
[0-9a-f]+ <.text>:
0: 2130 0080 ld r0,\[r1,r2\]
4: 2132 0080 ldb r0,\[r1,r2\]
8: 2370 0101 ld.aw r1,\[r3,r4\]
c: 2235 00c1 ld[hw]+.x r1,\[r2,r3\]
10: 2375 0102 ld[hw]+.aw.x r2,\[r3,r4\]
14: 1600 7000 0000 0000 ld r0,\[0\]
1c: 111e 0000 ld r0,\[r1,30\]
20: 12ec 8001 ld r1,\[r2,-20\]

6
gas/testsuite/gas/arc/ld.s
View File

@ -1,10 +1,10 @@
# ld test
ld r0,[r1,r2]
ldb r0,[r1,r2]
ld.a r1,[r3,r4]
ldw.x r1,[r2,r3]
ldw.x.a r2,[r3,r4]
ld r0,[0]
ld r0,[r1,30]
ld r1,[r2,-20]
ld r0,[r1,30]
ld r1,[r2,-20]

32
gas/testsuite/gas/arc/ld2.d
View File

@ -1,21 +1,19 @@
#as: -EL
#objdump: -dr -EL
#as: -mcpu=arc700
#objdump: -dr --show-raw-insn
.*: +file format elf32-.*arc
.*: +file format .*arc.*
Disassembly of section .text:
00000000 <.text>:
0: 00 80 00 08 08008000 ld r0,\[r1\]
4: 01 00 a3 08 08a30001 ld r5,\[r6,1\]
8: 00 00 7f 0a 0a7f0000 ld r19,\[0\]
c: 00 00 00 00
c: R_ARC_32 foo
10: 0a 10 81 08 0881100a ld.a r4,\[r2,10\]
14: 00 00 3f 08 083f0000 ld r1,\[0x384\]
18: 84 03 00 00
1c: 0f 84 41 08 0841840f ldb r2,\[r3,15\]
20: fe 09 62 08 086209fe ldw r3,\[r4,-2\]
24: 00 20 21 08 08212000 lr r1,\[r2\]
28: 14 a0 3f 08 083fa014 lr r1,\[0x14\]
2c: 00 a0 1f 08 081fa000 lr r0,\[status\]
[0-9a-f]+ <.text>:
0: 1100 0000 ld r0,\[r1\]
4: 1601 0005 ld r5,\[r6,1\]
8: 1600 7013 0000 0000 ld r19,\[0\]
c: ARC_32_ME foo
10: 120a 0204 ld.aw r4,\[r2,10\]
14: 1600 7001 0000 0384 ld r1,\[0x384\]
1c: 130f 0082 ldb r2,\[r3,15\]
20: 14fe 8103 ld[hw]+ r3,\[r4,-2\]
24: 212a 0080 lr r1,\[r2\]
28: 216a 0500 lr r1,\[0x14\]
2c: 206a 0000 lr r0,\[0\]

2
gas/testsuite/gas/arc/ld2.s
View File

@ -7,7 +7,7 @@
ld r1,[900]
ldb r2,[r3,15]
ldw r3,[r4,-2]
lr r1,[r2]
lr r1,[20]
lr r0,[status]

105
gas/testsuite/gas/arc/lp.d
View File

@ -1,76 +1,37 @@
#as: -EL
#objdump: -dr -EL
#as: -mcpu=archs
#objdump: -dr --show-raw-insn
.*: +file format elf32-.*arc
.*: +file format .*arc.*
Disassembly of section .text:
00000000 <text_label>:
0: 80 ff ff 37 37ffff80 lp 0 <text_label>
4: 00 ff ff 37 37ffff00 lp 0 <text_label>
8: 80 fe ff 37 37fffe80 lp 0 <text_label>
c: 01 fe ff 37 37fffe01 lpz 0 <text_label>
10: 81 fd ff 37 37fffd81 lpz 0 <text_label>
14: 02 fd ff 37 37fffd02 lpnz 0 <text_label>
18: 82 fc ff 37 37fffc82 lpnz 0 <text_label>
1c: 03 fc ff 37 37fffc03 lpp 0 <text_label>
20: 83 fb ff 37 37fffb83 lpp 0 <text_label>
24: 04 fb ff 37 37fffb04 lpn 0 <text_label>
28: 84 fa ff 37 37fffa84 lpn 0 <text_label>
2c: 05 fa ff 37 37fffa05 lpc 0 <text_label>
30: 85 f9 ff 37 37fff985 lpc 0 <text_label>
34: 05 f9 ff 37 37fff905 lpc 0 <text_label>
38: 86 f8 ff 37 37fff886 lpnc 0 <text_label>
3c: 06 f8 ff 37 37fff806 lpnc 0 <text_label>
40: 86 f7 ff 37 37fff786 lpnc 0 <text_label>
44: 07 f7 ff 37 37fff707 lpv 0 <text_label>
48: 87 f6 ff 37 37fff687 lpv 0 <text_label>
4c: 08 f6 ff 37 37fff608 lpnv 0 <text_label>
50: 88 f5 ff 37 37fff588 lpnv 0 <text_label>
54: 09 f5 ff 37 37fff509 lpgt 0 <text_label>
58: 8a f4 ff 37 37fff48a lpge 0 <text_label>
5c: 0b f4 ff 37 37fff40b lplt 0 <text_label>
60: 8c f3 ff 37 37fff38c lple 0 <text_label>
64: 0d f3 ff 37 37fff30d lphi 0 <text_label>
68: 8e f2 ff 37 37fff28e lpls 0 <text_label>
6c: 0f f2 ff 37 37fff20f lppnz 0 <text_label>
70: a0 f1 ff 37 37fff1a0 lp.d 0 <text_label>
74: 00 f1 ff 37 37fff100 lp 0 <text_label>
78: c0 f0 ff 37 37fff0c0 lp.jd 0 <text_label>
7c: 21 f0 ff 37 37fff021 lpz.d 0 <text_label>
80: 82 ef ff 37 37ffef82 lpnz 0 <text_label>
84: 46 ef ff 37 37ffef46 lpnc.jd 0 <text_label>
[0-9a-f]+ <text_label-0x72>:
0: 20a8 0e40 lp 72 <text_label>
4: 20e8 0de0 lp 72 <text_label>
8: 20e8 0d60 lp 72 <text_label>
c: 20e8 0ce1 lpeq 72 <text_label>
10: 20e8 0c61 lpeq 72 <text_label>
14: 20e8 0be2 lpne 72 <text_label>
18: 20e8 0b62 lpne 72 <text_label>
1c: 20e8 0ae3 lpp 72 <text_label>
20: 20e8 0a63 lpp 72 <text_label>
24: 20e8 09e4 lpn 72 <text_label>
28: 20e8 0964 lpn 72 <text_label>
2c: 20e8 08e5 lpc 72 <text_label>
30: 20e8 0865 lpc 72 <text_label>
34: 20e8 07e5 lpc 72 <text_label>
38: 20e8 0766 lpnc 72 <text_label>
3c: 20e8 06e6 lpnc 72 <text_label>
40: 20e8 0666 lpnc 72 <text_label>
44: 20e8 05e7 lpv 72 <text_label>
48: 20e8 0567 lpv 72 <text_label>
4c: 20e8 04e8 lpnv 72 <text_label>
50: 20e8 0468 lpnv 72 <text_label>
54: 20e8 03e9 lpgt 72 <text_label>
58: 20e8 036a lpge 72 <text_label>
5c: 20e8 02eb lplt 72 <text_label>
60: 20e8 026c lple 72 <text_label>
64: 20e8 01ed lphi 72 <text_label>
68: 20e8 016e lpls 72 <text_label>
6c: 20e8 00ef lppnz 72 <text_label>
70: 78e0 nop_s

11
gas/testsuite/gas/arc/lp.s
View File

@ -1,6 +1,4 @@
# lp test
text_label:
lp text_label
lpal text_label
@ -31,10 +29,5 @@ text_label:
lpls text_label
lppnz text_label
lp.d text_label
lp.nd text_label
lp.jd text_label
lpeq.d text_label
lpne.nd text_label
lpcc.jd text_label
nop_s
text_label:

106
gas/testsuite/gas/arc/lsr.d
View File

@ -1,51 +1,61 @@
#as: -EL
#objdump: -dr -EL
#as: -mcpu=arc700
#objdump: -dr --prefix-addresses --show-raw-insn
.*: +file format elf32-.*arc
.*: +file format .*arc.*
Disassembly of section .text:
00000000 <.text>:
0: 00 84 00 18 18008400 lsr r0,r1
4: 00 04 6e 1b 1b6e0400 lsr fp,sp
8: 00 84 1f 18 181f8400 lsr r0,0
c: ff 85 3f 18 183f85ff lsr r1,-1
10: 00 04 e1 1f 1fe10400 lsr 0,r2
14: 00 84 e1 1f 1fe18400 lsr 0,r3
18: ff 84 9f 18 189f84ff lsr r4,255
1c: 00 84 e2 1f 1fe28400 lsr 0,r5
20: 00 85 df 18 18df8500 lsr r6,-256
24: 00 84 e3 1f 1fe38400 lsr 0,r7
28: 00 04 1f 19 191f0400 lsr r8,0x100
2c: 00 01 00 00
30: 00 04 3f 19 193f0400 lsr r9,0xffff_feff
34: ff fe ff ff
38: 00 04 7f 19 197f0400 lsr r11,0x4242_4242
3c: 42 42 42 42
40: 00 04 ff 1f 1fff0400 lsr 0,0x100
44: 00 01 00 00
48: 00 04 1f 18 181f0400 lsr r0,0
4c: 00 00 00 00
4c: R_ARC_32 foo
50: 01 84 45 19 19458401 lsr.z r10,r11
54: 02 84 86 19 19868402 lsr.nz r12,r13
58: 0b 04 df 19 19df040b lsr.lt r14,0
5c: 00 00 00 00
60: 09 04 ff 19 19ff0409 lsr.gt r15,0x200
64: 00 02 00 00
68: 00 85 00 18 18008500 lsr.f r0,r1
6c: 01 84 5e 18 185e8401 lsr.f r2,1
70: 00 05 e2 1f 1fe20500 lsr.f 0,r4
74: 00 05 bf 18 18bf0500 lsr.f r5,0x200
78: 00 02 00 00
7c: 00 05 df 1f 1fdf0500 lsr.f 0,0x200
80: 00 02 00 00
84: 01 85 00 18 18008501 lsr.z.f r0,r1
88: 02 05 3f 18 183f0502 lsr.nz.f r1,0
8c: 00 00 00 00
90: 0b 05 c1 1f 1fc1050b lsr.lt.f 0,r2
94: 00 00 00 00 00000000
98: 0c 05 1f 18 181f050c lsr.le.f r0,0x200
9c: 00 02 00 00
a0: 04 05 df 1f 1fdf0504 lsr.n.f 0,0x200
a4: 00 02 00 00
0x[0-9a-f]+ 2901 0080 lsr r0,r1,r2
0x[0-9a-f]+ 2b01 371a lsr gp,fp,sp
0x[0-9a-f]+ 2e01 37dd lsr ilink,r30,blink
0x[0-9a-f]+ 2941 0000 lsr r0,r1,0
0x[0-9a-f]+ 2e01 7080 0000 0000 lsr r0,0,r2
0x[0-9a-f]+ 2901 00be lsr 0,r1,r2
0x[0-9a-f]+ 2901 0f80 ffff ffff lsr r0,r1,0xffffffff
0x[0-9a-f]+ 2e01 7080 ffff ffff lsr r0,0xffffffff,r2
0x[0-9a-f]+ 2901 0f80 0000 00ff lsr r0,r1,0xff
0x[0-9a-f]+ 2e01 7080 0000 00ff lsr r0,0xff,r2
0x[0-9a-f]+ 2901 0f80 ffff ff00 lsr r0,r1,0xffffff00
0x[0-9a-f]+ 2e01 7080 ffff ff00 lsr r0,0xffffff00,r2
0x[0-9a-f]+ 2901 0f80 0000 0100 lsr r0,r1,0x100
0x[0-9a-f]+ 2e01 7080 ffff feff lsr r0,0xfffffeff,r2
0x[0-9a-f]+ 2e01 7f80 0000 0100 lsr r0,0x100,0x100
0x[0-9a-f]+ 2901 0f80 0000 0000 lsr r0,r1,0
68: ARC_32_ME foo
0x[0-9a-f]+ 28c1 0080 lsr r0,r0,r2
0x[0-9a-f]+ 2bc1 0140 lsr r3,r3,r5
0x[0-9a-f]+ 2ec1 0201 lsr.eq r6,r6,r8
0x[0-9a-f]+ 29c1 12c1 lsr.eq r9,r9,r11
0x[0-9a-f]+ 2cc1 1382 lsr.ne r12,r12,r14
0x[0-9a-f]+ 2fc1 1442 lsr.ne r15,r15,r17
0x[0-9a-f]+ 2ac1 2503 lsr.p r18,r18,r20
0x[0-9a-f]+ 2dc1 25c3 lsr.p r21,r21,r23
0x[0-9a-f]+ 28c1 3684 lsr.n r24,r24,gp
0x[0-9a-f]+ 2bc1 3744 lsr.n fp,fp,ilink
0x[0-9a-f]+ 2ec1 37c5 lsr.c r30,r30,blink
0x[0-9a-f]+ 2bc1 00c5 lsr.c r3,r3,r3
0x[0-9a-f]+ 2bc1 0205 lsr.c r3,r3,r8
0x[0-9a-f]+ 2bc1 0106 lsr.nc r3,r3,r4
0x[0-9a-f]+ 2cc1 0106 lsr.nc r4,r4,r4
0x[0-9a-f]+ 2cc1 01c6 lsr.nc r4,r4,r7
0x[0-9a-f]+ 2cc1 0147 lsr.v r4,r4,r5
0x[0-9a-f]+ 2dc1 0147 lsr.v r5,r5,r5
0x[0-9a-f]+ 2dc1 0148 lsr.nv r5,r5,r5
0x[0-9a-f]+ 2dc1 0148 lsr.nv r5,r5,r5
0x[0-9a-f]+ 2ec1 0009 lsr.gt r6,r6,r0
0x[0-9a-f]+ 28c1 002a lsr.ge r0,r0,0
0x[0-9a-f]+ 29c1 006b lsr.lt r1,r1,0x1
0x[0-9a-f]+ 2bc1 00ed lsr.hi r3,r3,0x3
0x[0-9a-f]+ 2cc1 012e lsr.ls r4,r4,0x4
0x[0-9a-f]+ 2dc1 016f lsr.pnz r5,r5,0x5
0x[0-9a-f]+ 2901 8080 lsr.f r0,r1,r2
0x[0-9a-f]+ 2941 8040 lsr.f r0,r1,0x1
0x[0-9a-f]+ 2e01 f080 0000 0001 lsr.f r0,0x1,r2
0x[0-9a-f]+ 2901 80be lsr.f 0,r1,r2
0x[0-9a-f]+ 2901 8f80 0000 0200 lsr.f r0,r1,0x200
0x[0-9a-f]+ 2e01 f080 0000 0200 lsr.f r0,0x200,r2
0x[0-9a-f]+ 29c1 8081 lsr.f.eq r1,r1,r2
0x[0-9a-f]+ 28c1 8022 lsr.f.ne r0,r0,0
0x[0-9a-f]+ 2ac1 808b lsr.f.lt r2,r2,r2
0x[0-9a-f]+ 2ec1 f0a9 0000 0001 lsr.f.gt 0,0x1,0x2
0x[0-9a-f]+ 2ec1 ff8c 0000 0200 lsr.f.le 0,0x200,0x200
0x[0-9a-f]+ 2ec1 f0aa 0000 0200 lsr.f.ge 0,0x200,0x2

83
gas/testsuite/gas/arc/lsr.s
View File

@ -1,38 +1,63 @@
# lsr test
lsr r0,r1
lsr fp,sp
lsr r0,r1,r2
lsr r26,fp,sp
lsr ilink1,ilink2,blink
lsr r0,0
lsr r1,-1
lsr 0,r2
lsr -1,r3
lsr r4,255
lsr 255,r5
lsr r6,-256
lsr -256,r7
lsr r0,r1,0
lsr r0,0,r2
lsr 0,r1,r2
lsr r0,r1,-1
lsr r0,-1,r2
lsr r0,r1,255
lsr r0,255,r2
lsr r0,r1,-256
lsr r0,-256,r2
lsr r8,256
lsr r9,-257
lsr r11,0x42424242
lsr r0,r1,256
lsr r0,-257,r2
lsr 255,256
lsr r0,256,256
lsr r0,foo
lsr r0,r1,foo
lsr.eq r10,r11
lsr.ne r12,r13
lsr.lt r14,0
lsr.gt r15,512
lsr.al r0,r0,r2
lsr.ra r3,r3,r5
lsr.eq r6,r6,r8
lsr.z r9,r9,r11
lsr.ne r12,r12,r14
lsr.nz r15,r15,r17
lsr.pl r18,r18,r20
lsr.p r21,r21,r23
lsr.mi r24,r24,r26
lsr.n r27,r27,r29
lsr.cs r30,r30,r31
lsr.c r3,r3,r3
lsr.lo r3,r3,r8
lsr.cc r3,r3,r4
lsr.nc r4,r4,r4
lsr.hs r4,r4,r7
lsr.vs r4,r4,r5
lsr.v r5,r5,r5
lsr.vc r5,r5,r5
lsr.nv r5,r5,r5
lsr.gt r6,r6,r0
lsr.ge r0,r0,0
lsr.lt r1,r1,1
lsr.hi r3,r3,3
lsr.ls r4,r4,4
lsr.pnz r5,r5,5
lsr.f r0,r1
lsr.f r2,1
lsr.f 0,r4
lsr.f r5,512
lsr.f 512,512
lsr.f r0,r1,r2
lsr.f r0,r1,1
lsr.f r0,1,r2
lsr.f 0,r1,r2
lsr.f r0,r1,512
lsr.f r0,512,r2
lsr.eq.f r0,r1
lsr.ne.f r1,0
lsr.lt.f 0,r2
lsr.le.f r0,512
lsr.n.f 512,512
lsr.eq.f r1,r1,r2
lsr.ne.f r0,r0,0
lsr.lt.f r2,r2,r2
lsr.gt.f 0,1,2
lsr.le.f 0,512,512
lsr.ge.f 0,512,2

78
gas/testsuite/gas/arc/math.d
View File

@ -1,78 +0,0 @@
#objdump: -dr
#name: @OC@
# Test the @OC@ insn.
.*: +file format elf32-.*arc
Disassembly of section .text:
00000000 @IC+0@008400 @OC@ r0,r1,r2
00000004 @IC+3@4db800 @OC@ r26,fp,sp
00000008 @IC+3@af3e00 @OC@ ilink1,ilink2,blink
0000000c @IC+7@5df800 @OC@ r58,r59,lp_count
00000010 @IC+0@00fe00 @OC@ r0,r1,0
00000014 @IC+0@1f8400 @OC@ r0,0,r2
00000018 @IC+7@e08400 @OC@ 0,r1,r2
0000001c @IC+0@00ffff @OC@ r0,r1,-1
00000020 @IC+0@1f85ff @OC@ r0,-1,r2
00000024 @IC+7@e085ff @OC@ -1,r1,r2
00000028 @IC+0@00feff @OC@ r0,r1,255
0000002c @IC+0@1f84ff @OC@ r0,255,r2
00000030 @IC+7@e084ff @OC@ 255,r1,r2
00000034 @IC+0@00ff00 @OC@ r0,r1,-256
00000038 @IC+0@1f8500 @OC@ r0,-256,r2
0000003c @IC+7@e08500 @OC@ -256,r1,r2
00000040 @IC+0@00fc00 @OC@ r0,r1,256
00000048 @IC+0@1f0400 @OC@ r0,-257,r2
00000050 @IC+7@c08400 @OC@ 511,r1,r2
00000058 @IC+0@1f0400 @OC@ r0,1111638594,r2
00000060 @IC+7@c0fc00 @OC@ 305419896,r1,305419896
00000068 @IC+0@1ffcff @OC@ r0,255,256
00000070 @IC+0@1f7eff @OC@ r0,256,255
00000078 @IC+7@e0fcff @OC@ 255,r1,256
00000080 @IC+7@ff04ff @OC@ 255,256,r2
00000088 @IC+7@c0feff @OC@ 256,r1,255
00000090 @IC+7@df84ff @OC@ 256,255,r2
00000098 @IC+0@00fc00 @OC@ r0,r1,0
RELOC: 0000009c R_ARC_32 foo
000000a0 @IC+0@008400 @OC@ r0,r1,r2
000000a4 @IC+0@620a00 @OC@ r3,r4,r5
000000a8 @IC+0@c39001 @OC@.eq r6,r7,r8
000000ac @IC+1@251601 @OC@.eq r9,r10,r11
000000b0 @IC+1@869c02 @OC@.ne r12,r13,r14
000000b4 @IC+1@e82202 @OC@.ne r15,r16,r17
000000b8 @IC+2@49a803 @OC@.p r18,r19,r20
000000bc @IC+2@ab2e03 @OC@.p r21,r22,r23
000000c0 @IC+3@0cb404 @OC@.n r24,r25,r26
000000c4 @IC+3@6e3a04 @OC@.n fp,sp,ilink1
000000c8 @IC+3@cfc005 @OC@.c ilink2,blink,r32
000000cc @IC+4@314605 @OC@.c r33,r34,r35
000000d0 @IC+4@92cc05 @OC@.c r36,r37,r38
000000d4 @IC+4@f45206 @OC@.nc r39,r40,r41
000000d8 @IC+5@55d806 @OC@.nc r42,r43,r44
000000dc @IC+5@b75e06 @OC@.nc r45,r46,r47
000000e0 @IC+6@18e407 @OC@.v r48,r49,r50
000000e4 @IC+6@7a6a07 @OC@.v r51,r52,r53
000000e8 @IC+6@dbf008 @OC@.nv r54,r55,r56
000000ec @IC+7@3d7608 @OC@.nv r57,r58,r59
000000f0 @IC+7@9e0009 @OC@.gt lp_count,lp_count,r0
000000f4 @IC+0@007c0a @OC@.ge r0,r0,0
000000fc @IC+0@3f020b @OC@.lt r1,1,r1
00000104 @IC+7@c0840c @OC@.le 2,r1,r2
0000010c @IC+0@7f060d @OC@.hi r3,3,r3
00000114 @IC+7@df080e @OC@.ls 4,4,r4
0000011c @IC+7@c2fc0f @OC@.pnz 5,r5,5
00000124 @IC+0@008500 @OC@.f r0,r1,r2
00000128 @IC+0@00fa01 @OC@.f r0,r1,1
0000012c @IC+0@1e8401 @OC@.f r0,1,r2
00000130 @IC+7@a08400 @OC@.f 0,r1,r2
00000134 @IC+0@00fd00 @OC@.f r0,r1,512
0000013c @IC+0@1f0500 @OC@.f r0,512,r2
00000144 @IC+7@c08500 @OC@.f 512,r1,r2
0000014c @IC+0@008501 @OC@.eq.f r0,r1,r2
00000150 @IC+0@00fd02 @OC@.ne.f r0,r1,0
00000158 @IC+0@1f050b @OC@.lt.f r0,0,r2
00000160 @IC+7@c08509 @OC@.gt.f 0,r1,r2
00000168 @IC+0@00fd0c @OC@.le.f r0,r1,512
00000170 @IC+0@1f050a @OC@.ge.f r0,512,r2
00000178 @IC+7@c08504 @OC@.n.f 512,r1,r2

89
gas/testsuite/gas/arc/math.s
View File

@ -1,89 +0,0 @@
# @OC@ test
# Stay away from operands with duplicate arguments (eg: add r0,r1,r1).
# They will be disassembled as they're macro counterparts (eg: asl r0,r1).
# reg,reg,reg
@OC@ r0,r1,r2
@OC@ r26,fp,sp
@OC@ ilink1,ilink2,blink
@OC@ r58,r59,lp_count
# shimm values
@OC@ r0,r1,0
@OC@ r0,0,r2
@OC@ 0,r1,r2
@OC@ r0,r1,-1
@OC@ r0,-1,r2
@OC@ -1,r1,r2
@OC@ r0,r1,255
@OC@ r0,255,r2
@OC@ 255,r1,r2
@OC@ r0,r1,-256
@OC@ r0,-256,r2
@OC@ -256,r1,r2
# limm values
@OC@ r0,r1,256
@OC@ r0,-257,r2
@OC@ 511,r1,r2
@OC@ r0,0x42424242,r2
@OC@ 0x12345678,r1,0x12345678
# shimm and limm
@OC@ r0,255,256
@OC@ r0,256,255
@OC@ 255,r1,256
@OC@ 255,256,r2
@OC@ 256,r1,255
@OC@ 256,255,r2
# symbols
@OC@ r0,r1,foo
# conditional execution
@OC@.al r0,r1,r2
@OC@.ra r3,r4,r5
@OC@.eq r6,r7,r8
@OC@.z r9,r10,r11
@OC@.ne r12,r13,r14
@OC@.nz r15,r16,r17
@OC@.pl r18,r19,r20
@OC@.p r21,r22,r23
@OC@.mi r24,r25,r26
@OC@.n r27,r28,r29
@OC@.cs r30,r31,r32
@OC@.c r33,r34,r35
@OC@.lo r36,r37,r38
@OC@.cc r39,r40,r41
@OC@.nc r42,r43,r44
@OC@.hs r45,r46,r47
@OC@.vs r48,r49,r50
@OC@.v r51,r52,r53
@OC@.vc r54,r55,r56
@OC@.nv r57,r58,r59
@OC@.gt r60,r60,r0
@OC@.ge r0,r0,0
@OC@.lt r1,1,r1
@OC@.le 2,r1,r2
@OC@.hi r3,3,r3
@OC@.ls 4,4,r4
@OC@.pnz 5,r5,5
# flag setting
@OC@.f r0,r1,r2
@OC@.f r0,r1,1
@OC@.f r0,1,r2
@OC@.f 0,r1,r2
@OC@.f r0,r1,512
@OC@.f r0,512,r2
@OC@.f 512,r1,r2
# conditional execution + flag setting
@OC@.eq.f r0,r1,r2
@OC@.ne.f r0,r1,0
@OC@.lt.f r0,0,r2
@OC@.gt.f 0,r1,r2
@OC@.le.f r0,r1,512
@OC@.ge.f r0,512,r2
@OC@.n.f 512,r1,r2

118
gas/testsuite/gas/arc/mov.d
View File

@ -1,68 +1,56 @@
#as: -EL
#objdump: -dr -EL
#as: -mcpu=arc700
#objdump: -dr --prefix-addresses --show-raw-insn
.*: +file format elf32-.*arc
.*: +file format .*arc.*
Disassembly of section .text:
00000000 <.text>:
0: 00 82 00 60 60008200 mov r0,r1
4: 00 38 6e 63 636e3800 mov fp,sp
8: 00 fe 1f 60 601ffe00 mov r0,0
c: ff ff 3f 60 603fffff mov r1,-1
10: 00 04 e1 67 67e10400 mov 0,r2
14: 00 86 e1 67 67e18600 mov 0,r3
18: ff fe 9f 60 609ffeff mov r4,255
1c: 00 8a e2 67 67e28a00 mov 0,r5
20: 00 ff df 60 60dfff00 mov r6,-256
24: 00 8e e3 67 67e38e00 mov 0,r7
28: 00 7c 1f 61 611f7c00 mov r8,0x100
2c: 00 01 00 00
30: 00 7c 3f 61 613f7c00 mov r9,0xffff_feff
34: ff fe ff ff
38: 00 7c 7f 61 617f7c00 mov r11,0x4242_4242
3c: 42 42 42 42
40: 00 7c ff 67 67ff7c00 mov 0,0x100
44: 00 01 00 00
48: 00 7c 1f 60 601f7c00 mov r0,0
4c: 00 00 00 00
4c: R_ARC_32 foo
50: 00 82 00 60 60008200 mov r0,r1
54: 00 08 62 60 60620800 mov r3,r4
58: 01 8e c3 60 60c38e01 mov.z r6,r7
5c: 01 14 25 61 61251401 mov.z r9,r10
60: 02 9a 86 61 61869a02 mov.nz r12,r13
64: 02 20 e8 61 61e82002 mov.nz r15,r16
68: 03 a6 49 62 6249a603 mov.p r18,r19
6c: 03 2c ab 62 62ab2c03 mov.p r21,r22
70: 04 b2 0c 63 630cb204 mov.n r24,r25
74: 04 38 6e 63 636e3804 mov.n fp,sp
78: 05 be cf 63 63cfbe05 mov.c ilink2,blink
7c: 05 44 31 64 64314405 mov.c r33,r34
80: 05 ca 92 64 6492ca05 mov.c r36,r37
84: 06 50 f4 64 64f45006 mov.nc r39,r40
88: 06 d6 55 65 6555d606 mov.nc r42,r43
8c: 06 5c b7 65 65b75c06 mov.nc r45,r46
90: 07 e2 18 66 6618e207 mov.v r48,r49
94: 07 64 39 66 66396407 mov.v r49,r50
98: 08 ee 3b 66 663bee08 mov.nv r49,r55
9c: 08 74 3d 66 663d7408 mov.nv r49,r58
a0: 09 78 9e 67 679e7809 mov.gt lp_count,lp_count
a4: 0a 7c 1f 60 601f7c0a mov.ge r0,0
a8: 00 00 00 00
ac: 0c 7c df 67 67df7c0c mov.le 0,2
b0: 02 00 00 00
b4: 0d 86 61 60 6061860d mov.hi r3,r3
b8: 0e 08 82 60 6082080e mov.ls r4,r4
bc: 0f 8a a2 60 60a28a0f mov.pnz r5,r5
c0: 00 83 00 60 60008300 mov.f r0,r1
c4: 01 fa 5e 60 605efa01 mov.f r2,1
c8: 00 87 e1 67 67e18700 mov.f 0,r3
cc: 00 09 e2 67 67e20900 mov.f 0,r4
d0: 00 7d bf 60 60bf7d00 mov.f r5,0x200
d4: 00 02 00 00
d8: 00 7d df 67 67df7d00 mov.f 0,0x200
dc: 00 02 00 00
e0: 01 83 00 60 60008301 mov.z.f r0,r1
e4: 02 7d 3f 60 603f7d02 mov.nz.f r1,0
e8: 00 00 00 00
0x[0-9a-f]+ 200a 0040 mov r0,r1
0x[0-9a-f]+ 230a 3700 mov fp,sp
0x[0-9a-f]+ 204a 0000 mov r0,0
0x[0-9a-f]+ 218a 0fff mov r1,-1
0x[0-9a-f]+ 260a 7080 mov 0,r2
0x[0-9a-f]+ 248a 0fc3 mov r4,255
0x[0-9a-f]+ 268a 7fc3 mov 0,255
0x[0-9a-f]+ 268a 003c mov r6,-256
0x[0-9a-f]+ 230a 1f80 4242 4242 mov r11,0x42424242
0x[0-9a-f]+ 260a 7f80 1234 5678 mov 0,0x12345678
0x[0-9a-f]+ 200a 0f80 0000 0000 mov r0,0
34: ARC_32_ME foo
0x[0-9a-f]+ 20ca 0040 mov r0,r1
0x[0-9a-f]+ 23ca 0100 mov r3,r4
0x[0-9a-f]+ 26ca 01c1 mov.eq r6,r7
0x[0-9a-f]+ 21ca 1281 mov.eq r9,r10
0x[0-9a-f]+ 24ca 1342 mov.ne r12,r13
0x[0-9a-f]+ 27ca 1402 mov.ne r15,r16
0x[0-9a-f]+ 22ca 24c3 mov.p r18,r19
0x[0-9a-f]+ 25ca 2583 mov.p r21,r22
0x[0-9a-f]+ 20ca 3644 mov.n r24,r25
0x[0-9a-f]+ 23ca 3704 mov.n fp,sp
0x[0-9a-f]+ 20ca 0045 mov.c r0,r1
0x[0-9a-f]+ 23ca 0105 mov.c r3,r4
0x[0-9a-f]+ 26ca 01c5 mov.c r6,r7
0x[0-9a-f]+ 21ca 1006 mov.nc r9,r0
0x[0-9a-f]+ 22ca 00c6 mov.nc r2,r3
0x[0-9a-f]+ 25ca 0186 mov.nc r5,r6
0x[0-9a-f]+ 20ca 1247 mov.v r8,r9
0x[0-9a-f]+ 21ca 0087 mov.v r1,r2
0x[0-9a-f]+ 24ca 0148 mov.nv r4,r5
0x[0-9a-f]+ 27ca 0208 mov.nv r7,r8
0x[0-9a-f]+ 20ca 0009 mov.gt r0,r0
0x[0-9a-f]+ 20ca 002a mov.ge r0,0
0x[0-9a-f]+ 26ca 704b mov.lt 0,r1
0x[0-9a-f]+ 26ca 70ac mov.le 0,0x2
0x[0-9a-f]+ 23ca 00cd mov.hi r3,r3
0x[0-9a-f]+ 24ca 010e mov.ls r4,r4
0x[0-9a-f]+ 25ca 014f mov.pnz r5,r5
0x[0-9a-f]+ 200a 8040 mov.f r0,r1
0x[0-9a-f]+ 224a 8040 mov.f r2,0x1
0x[0-9a-f]+ 260a f100 mov.f 0,r4
0x[0-9a-f]+ 258a 8008 mov.f r5,512
0x[0-9a-f]+ 20ca 8041 mov.f.eq r0,r1
0x[0-9a-f]+ 21ca 8022 mov.f.ne r1,0
0x[0-9a-f]+ 26ca f08b mov.f.lt 0,r2
0x[0-9a-f]+ 26ca f089 mov.f.gt 0,r2
0x[0-9a-f]+ 20ca 8f8c 0000 0200 mov.f.le r0,0x200
0x[0-9a-f]+ 26ca f08a mov.f.ge 0,r2
0x[0-9a-f]+ 26ca ff84 0000 0200 mov.f.n 0,0x200

56
gas/testsuite/gas/arc/mov.s
View File

@ -1,58 +1,64 @@
# mov test
# reg,reg
mov r0,r1
mov fp,sp
# shimm values
mov r0,0
mov r1,-1
mov 0,r2
mov -1,r3
mov r4,255
mov 255,r5
mov 0,255
mov r6,-256
mov -256,r7
mov r8,256
mov r9,-257
# limm values
mov r11,0x42424242
mov 0, 0x12345678
mov 255,256
mov r0,foo
# symbols
mov r0,@foo
# conditional execution
mov.al r0,r1
mov.ra r3,r4
mov.eq r6,r7
mov.z r9,r10
mov.z r9,r10
mov.ne r12,r13
mov.nz r15,r16
mov.pl r18,r19
mov.p r21,r22
mov.p r21,r22
mov.mi r24,r25
mov.n r27,r28
mov.cs r30,r31
mov.c r33,r34
mov.lo r36,r37
mov.cc r39,r40
mov.nc r42,r43
mov.hs r45,r46
mov.vs r48,r49
mov.v r49,r50
mov.vc r49,r55
mov.nv r49,r58
mov.gt r60,r60
mov.n r27,r28
mov.cs r0,r1
mov.c r3,r4
mov.lo r6,r7
mov.cc r9,r0
mov.nc r2,r3
mov.hs r5,r6
mov.vs r8,r9
mov.v r1,r2
mov.vc r4,r5
mov.nv r7,r8
mov.gt r0,r0
mov.ge r0,0
mov.le 2,2
mov.lt 0,r1
mov.le 0,2
mov.hi r3,r3
mov.ls r4,r4
mov.pnz r5,r5
# flag setting
mov.f r0,r1
mov.f r2,1
mov.f 1,r3
mov.f 0,r4
mov.f r5,512
mov.f 512,512
# conditional execution + flag setting
mov.eq.f r0,r1
mov.ne.f r1,0
mov.lt.f 0,r2
mov.gt.f 0,r2
mov.le.f r0,512
mov.ge.f 0,r2
mov.n.f 0,512

10
gas/testsuite/gas/arc/nop.d
View File

@ -1,9 +1,7 @@
#as: -EL
#objdump: -dr -EL
#as: -mcpu=arc700
#objdump: -dr --prefix-addresses --show-raw-insn
.*: +file format elf32-.*arc
.*: +file format .*arc.*
Disassembly of section .text:
00000000 <.text>:
0: ff ff ff 7f 7fffffff nop
0x00000000 78e0 nop_s

2
gas/testsuite/gas/arc/nop.s
View File

@ -1,3 +1,3 @@
# nop test
nop
nop_s

140
gas/testsuite/gas/arc/or.d
View File

@ -1,85 +1,61 @@
#as: -EL
#objdump: -dr -EL
#as: -mcpu=arc700
#objdump: -dr --prefix-addresses --show-raw-insn
.*: +file format elf32-.*arc
.*: +file format .*arc.*
Disassembly of section .text:
00000000 <.text>:
0: 00 84 00 68 68008400 or r0,r1,r2
4: 00 b8 4d 6b 6b4db800 or gp,fp,sp
8: 00 3e af 6b 6baf3e00 or ilink1,ilink2,blink
c: 00 f8 1d 6f 6f1df800 or r56,r59,lp_count
10: 00 fe 00 68 6800fe00 or r0,r1,0
14: 00 84 1f 68 681f8400 or r0,0,r2
18: 00 84 e0 6f 6fe08400 or 0,r1,r2
1c: ff ff 00 68 6800ffff or r0,r1,-1
20: ff 85 1f 68 681f85ff or r0,-1,r2
24: 00 84 e0 6f 6fe08400 or 0,r1,r2
28: ff fe 00 68 6800feff or r0,r1,255
2c: ff 84 1f 68 681f84ff or r0,255,r2
30: 00 84 e0 6f 6fe08400 or 0,r1,r2
34: 00 ff 00 68 6800ff00 or r0,r1,-256
38: 00 85 1f 68 681f8500 or r0,-256,r2
3c: 00 84 e0 6f 6fe08400 or 0,r1,r2
40: 00 fc 00 68 6800fc00 or r0,r1,0x100
44: 00 01 00 00
48: 00 04 1f 68 681f0400 or r0,0xffff_feff,r2
4c: ff fe ff ff
50: ff fc 1f 68 681ffcff or r0,255,0x100
54: 00 01 00 00
58: ff 7e 1f 68 681f7eff or r0,0x100,255
5c: 00 01 00 00
60: 00 fc 00 68 6800fc00 or r0,r1,0
64: 00 00 00 00
64: R_ARC_32 foo
68: 00 84 00 68 68008400 or r0,r1,r2
6c: 00 0a 62 68 68620a00 or r3,r4,r5
70: 01 90 c3 68 68c39001 or.z r6,r7,r8
74: 01 16 25 69 69251601 or.z r9,r10,r11
78: 02 9c 86 69 69869c02 or.nz r12,r13,r14
7c: 02 22 e8 69 69e82202 or.nz r15,r16,r17
80: 03 a8 49 6a 6a49a803 or.p r18,r19,r20
84: 03 2e ab 6a 6aab2e03 or.p r21,r22,r23
88: 04 b4 0c 6b 6b0cb404 or.n r24,r25,gp
8c: 04 3a 6e 6b 6b6e3a04 or.n fp,sp,ilink1
90: 05 c0 cf 6b 6bcfc005 or.c ilink2,blink,r32
94: 05 46 31 6c 6c314605 or.c r33,r34,r35
98: 05 cc 92 6c 6c92cc05 or.c r36,r37,r38
9c: 06 52 f4 6c 6cf45206 or.nc r39,r40,r41
a0: 06 d8 55 6d 6d55d806 or.nc r42,r43,r44
a4: 06 5e b7 6d 6db75e06 or.nc r45,r46,r47
a8: 07 e4 18 6e 6e18e407 or.v r48,r49,r50
ac: 07 6a 1a 6f 6f1a6a07 or.v r56,r52,r53
b0: 08 f0 1b 6f 6f1bf008 or.nv r56,r55,r56
b4: 08 76 1d 6f 6f1d7608 or.nv r56,r58,r59
b8: 09 00 9e 6f 6f9e0009 or.gt lp_count,lp_count,r0
bc: 0a 7c 00 68 68007c0a or.ge r0,r0,0
c0: 00 00 00 00
c4: 0b 02 3f 68 683f020b or.lt r1,1,r1
c8: 01 00 00 00
cc: 0d 06 7f 68 687f060d or.hi r3,3,r3
d0: 03 00 00 00
d4: 0e 08 df 6f 6fdf080e or.ls 0,4,r4
d8: 04 00 00 00
dc: 0f fc c2 6f 6fc2fc0f or.pnz 0,r5,5
e0: 05 00 00 00
e4: 00 85 00 68 68008500 or.f r0,r1,r2
e8: 01 fa 00 68 6800fa01 or.f r0,r1,1
ec: 01 84 1e 68 681e8401 or.f r0,1,r2
f0: 00 85 e0 6f 6fe08500 or.f 0,r1,r2
f4: 00 fd 00 68 6800fd00 or.f r0,r1,0x200
f8: 00 02 00 00
fc: 00 05 1f 68 681f0500 or.f r0,0x200,r2
100: 00 02 00 00
104: 01 85 00 68 68008501 or.z.f r0,r1,r2
108: 02 fd 00 68 6800fd02 or.nz.f r0,r1,0
10c: 00 00 00 00
110: 0b 05 1f 68 681f050b or.lt.f r0,0,r2
114: 00 00 00 00
118: 09 85 c0 6f 6fc08509 or.gt.f 0,r1,r2
11c: 00 00 00 00 00000000
120: 0c fd 00 68 6800fd0c or.le.f r0,r1,0x200
124: 00 02 00 00
128: 0a 05 1f 68 681f050a or.ge.f r0,0x200,r2
12c: 00 02 00 00
0x[0-9a-f]+ 2105 0080 or r0,r1,r2
0x[0-9a-f]+ 2305 371a or gp,fp,sp
0x[0-9a-f]+ 2605 37dd or ilink,r30,blink
0x[0-9a-f]+ 2145 0000 or r0,r1,0
0x[0-9a-f]+ 2605 7080 0000 0000 or r0,0,r2
0x[0-9a-f]+ 2105 00be or 0,r1,r2
0x[0-9a-f]+ 2105 0f80 ffff ffff or r0,r1,0xffffffff
0x[0-9a-f]+ 2605 7080 ffff ffff or r0,0xffffffff,r2
0x[0-9a-f]+ 2105 0f80 0000 00ff or r0,r1,0xff
0x[0-9a-f]+ 2605 7080 0000 00ff or r0,0xff,r2
0x[0-9a-f]+ 2105 0f80 ffff ff00 or r0,r1,0xffffff00
0x[0-9a-f]+ 2605 7080 ffff ff00 or r0,0xffffff00,r2
0x[0-9a-f]+ 2105 0f80 0000 0100 or r0,r1,0x100
0x[0-9a-f]+ 2605 7080 ffff feff or r0,0xfffffeff,r2
0x[0-9a-f]+ 2605 7f80 0000 0100 or r0,0x100,0x100
0x[0-9a-f]+ 2105 0f80 0000 0000 or r0,r1,0
68: ARC_32_ME foo
0x[0-9a-f]+ 20c5 0080 or r0,r0,r2
0x[0-9a-f]+ 23c5 0140 or r3,r3,r5
0x[0-9a-f]+ 26c5 0201 or.eq r6,r6,r8
0x[0-9a-f]+ 21c5 12c1 or.eq r9,r9,r11
0x[0-9a-f]+ 24c5 1382 or.ne r12,r12,r14
0x[0-9a-f]+ 27c5 1442 or.ne r15,r15,r17
0x[0-9a-f]+ 22c5 2503 or.p r18,r18,r20
0x[0-9a-f]+ 25c5 25c3 or.p r21,r21,r23
0x[0-9a-f]+ 20c5 3684 or.n r24,r24,gp
0x[0-9a-f]+ 23c5 3744 or.n fp,fp,ilink
0x[0-9a-f]+ 26c5 37c5 or.c r30,r30,blink
0x[0-9a-f]+ 23c5 00c5 or.c r3,r3,r3
0x[0-9a-f]+ 23c5 0205 or.c r3,r3,r8
0x[0-9a-f]+ 23c5 0106 or.nc r3,r3,r4
0x[0-9a-f]+ 24c5 0106 or.nc r4,r4,r4
0x[0-9a-f]+ 24c5 01c6 or.nc r4,r4,r7
0x[0-9a-f]+ 24c5 0147 or.v r4,r4,r5
0x[0-9a-f]+ 25c5 0147 or.v r5,r5,r5
0x[0-9a-f]+ 25c5 0148 or.nv r5,r5,r5
0x[0-9a-f]+ 25c5 0148 or.nv r5,r5,r5
0x[0-9a-f]+ 26c5 0009 or.gt r6,r6,r0
0x[0-9a-f]+ 20c5 002a or.ge r0,r0,0
0x[0-9a-f]+ 21c5 006b or.lt r1,r1,0x1
0x[0-9a-f]+ 23c5 00ed or.hi r3,r3,0x3
0x[0-9a-f]+ 24c5 012e or.ls r4,r4,0x4
0x[0-9a-f]+ 25c5 016f or.pnz r5,r5,0x5
0x[0-9a-f]+ 2105 8080 or.f r0,r1,r2
0x[0-9a-f]+ 2145 8040 or.f r0,r1,0x1
0x[0-9a-f]+ 2605 f080 0000 0001 or.f r0,0x1,r2
0x[0-9a-f]+ 2105 80be or.f 0,r1,r2
0x[0-9a-f]+ 2105 8f80 0000 0200 or.f r0,r1,0x200
0x[0-9a-f]+ 2605 f080 0000 0200 or.f r0,0x200,r2
0x[0-9a-f]+ 21c5 8081 or.f.eq r1,r1,r2
0x[0-9a-f]+ 20c5 8022 or.f.ne r0,r0,0
0x[0-9a-f]+ 22c5 808b or.f.lt r2,r2,r2
0x[0-9a-f]+ 26c5 f0a9 0000 0001 or.f.gt 0,0x1,0x2
0x[0-9a-f]+ 26c5 ff8c 0000 0200 or.f.le 0,0x200,0x200
0x[0-9a-f]+ 26c5 f0aa 0000 0200 or.f.ge 0,0x200,0x2

69
gas/testsuite/gas/arc/or.s
View File

@ -3,55 +3,50 @@
or r0,r1,r2
or r26,fp,sp
or ilink1,ilink2,blink
or r56,r59,lp_count
or r0,r1,0
or r0,0,r2
or 0,r1,r2
or r0,r1,-1
or r0,-1,r2
or -1,r1,r2
or r0,r1,255
or r0,255,r2
or 255,r1,r2
or r0,r1,-256
or r0,-256,r2
or -256,r1,r2
or r0,r1,256
or r0,-257,r2
or r0,255,256
or r0,256,255
or r0,256,256
or r0,r1,foo
or.al r0,r1,r2
or.ra r3,r4,r5
or.eq r6,r7,r8
or.z r9,r10,r11
or.ne r12,r13,r14
or.nz r15,r16,r17
or.pl r18,r19,r20
or.p r21,r22,r23
or.mi r24,r25,r26
or.n r27,r28,r29
or.cs r30,r31,r32
or.c r33,r34,r35
or.lo r36,r37,r38
or.cc r39,r40,r41
or.nc r42,r43,r44
or.hs r45,r46,r47
or.vs r48,r49,r50
or.v r56,r52,r53
or.vc r56,r55,r56
or.nv r56,r58,r59
or.gt r60,r60,r0
or.al r0,r0,r2
or.ra r3,r3,r5
or.eq r6,r6,r8
or.z r9,r9,r11
or.ne r12,r12,r14
or.nz r15,r15,r17
or.pl r18,r18,r20
or.p r21,r21,r23
or.mi r24,r24,r26
or.n r27,r27,r29
or.cs r30,r30,r31
or.c r3,r3,r3
or.lo r3,r3,r8
or.cc r3,r3,r4
or.nc r4,r4,r4
or.hs r4,r4,r7
or.vs r4,r4,r5
or.v r5,r5,r5
or.vc r5,r5,r5
or.nv r5,r5,r5
or.gt r6,r6,r0
or.ge r0,r0,0
or.lt r1,1,r1
or.hi r3,3,r3
or.ls 4,4,r4
or.pnz 5,r5,5
or.lt r1,r1,1
or.hi r3,r3,3
or.ls r4,r4,4
or.pnz r5,r5,5
or.f r0,r1,r2
or.f r0,r1,1
@ -60,9 +55,9 @@
or.f r0,r1,512
or.f r0,512,r2
or.eq.f r0,r1,r2
or.ne.f r0,r1,0
or.lt.f r0,0,r2
or.gt.f 0,r1,r2
or.le.f r0,r1,512
or.ge.f r0,512,r2
or.eq.f r1,r1,r2
or.ne.f r0,r0,0
or.lt.f r2,r2,r2
or.gt.f 0,1,2
or.le.f 0,512,512
or.ge.f 0,512,2

84
gas/testsuite/gas/arc/rlc.d
View File

@ -1,68 +1,22 @@
#as: -EL
#objdump: -dr -EL
#as: -mcpu=arc700
#objdump: -dr --prefix-addresses --show-raw-insn
.*: +file format elf32-.*arc
.*: +file format .*arc.*
Disassembly of section .text:
00000000 <.text>:
0: 00 82 00 48 48008200 rlc r0,r1
4: 00 38 6e 4b 4b6e3800 rlc fp,sp
8: 00 fe 1f 48 481ffe00 rlc r0,0
c: ff ff 3f 48 483fffff rlc r1,-1
10: 00 04 e1 4f 4fe10400 rlc 0,r2
14: 00 86 e1 4f 4fe18600 rlc 0,r3
18: ff fe 9f 48 489ffeff rlc r4,255
1c: 00 8a e2 4f 4fe28a00 rlc 0,r5
20: 00 ff df 48 48dfff00 rlc r6,-256
24: 00 8e e3 4f 4fe38e00 rlc 0,r7
28: 00 7c 1f 49 491f7c00 rlc r8,0x100
2c: 00 01 00 00
30: 00 7c 3f 49 493f7c00 rlc r9,0xffff_feff
34: ff fe ff ff
38: 00 7c 7f 49 497f7c00 rlc r11,0x4242_4242
3c: 42 42 42 42
40: 00 7c ff 4f 4fff7c00 rlc 0,0x100
44: 00 01 00 00
48: 00 7c 1f 48 481f7c00 rlc r0,0
4c: 00 00 00 00
4c: R_ARC_32 foo
50: 00 82 00 48 48008200 rlc r0,r1
54: 00 08 62 48 48620800 rlc r3,r4
58: 01 8e c3 48 48c38e01 rlc.z r6,r7
5c: 01 14 25 49 49251401 rlc.z r9,r10
60: 02 9a 86 49 49869a02 rlc.nz r12,r13
64: 02 20 e8 49 49e82002 rlc.nz r15,r16
68: 03 a6 49 4a 4a49a603 rlc.p r18,r19
6c: 03 2c ab 4a 4aab2c03 rlc.p r21,r22
70: 04 b2 0c 4b 4b0cb204 rlc.n r24,r25
74: 04 38 6e 4b 4b6e3804 rlc.n fp,sp
78: 05 be cf 4b 4bcfbe05 rlc.c ilink2,blink
7c: 05 44 31 4c 4c314405 rlc.c r33,r34
80: 05 ca 92 4c 4c92ca05 rlc.c r36,r37
84: 06 50 f4 4c 4cf45006 rlc.nc r39,r40
88: 06 d6 55 4d 4d55d606 rlc.nc r42,r43
8c: 06 5c b7 4d 4db75c06 rlc.nc r45,r46
90: 07 e2 18 4e 4e18e207 rlc.v r48,r49
94: 07 64 39 4e 4e396407 rlc.v r49,r50
98: 08 ee 3b 4e 4e3bee08 rlc.nv r49,r55
9c: 08 74 3d 4e 4e3d7408 rlc.nv r49,r58
a0: 09 78 9e 4f 4f9e7809 rlc.gt lp_count,lp_count
a4: 0a 7c 1f 48 481f7c0a rlc.ge r0,0
a8: 00 00 00 00
ac: 0c 7c df 4f 4fdf7c0c rlc.le 0,2
b0: 02 00 00 00
b4: 0d 86 61 48 4861860d rlc.hi r3,r3
b8: 0e 08 82 48 4882080e rlc.ls r4,r4
bc: 0f 8a a2 48 48a28a0f rlc.pnz r5,r5
c0: 00 83 00 48 48008300 rlc.f r0,r1
c4: 01 fa 5e 48 485efa01 rlc.f r2,1
c8: 00 87 e1 4f 4fe18700 rlc.f 0,r3
cc: 00 09 e2 4f 4fe20900 rlc.f 0,r4
d0: 00 7d bf 48 48bf7d00 rlc.f r5,0x200
d4: 00 02 00 00
d8: 00 7d df 4f 4fdf7d00 rlc.f 0,0x200
dc: 00 02 00 00
e0: 01 83 00 48 48008301 rlc.z.f r0,r1
e4: 02 7d 3f 48 483f7d02 rlc.nz.f r1,0
e8: 00 00 00 00
0x[0-9a-f]+ 202f 004b rlc r0,r1
0x[0-9a-f]+ 232f 370b rlc fp,sp
0x[0-9a-f]+ 206f 000b rlc r0,0
0x[0-9a-f]+ 212f 0f8b ffff ffff rlc r1,0xffffffff
0x[0-9a-f]+ 262f 708b rlc 0,r2
0x[0-9a-f]+ 242f 0f8b 0000 00ff rlc r4,0xff
0x[0-9a-f]+ 262f 0f8b ffff ff00 rlc r6,0xffffff00
0x[0-9a-f]+ 202f 1f8b 0000 0100 rlc r8,0x100
0x[0-9a-f]+ 212f 1f8b ffff feff rlc r9,0xfffffeff
0x[0-9a-f]+ 232f 1f8b 4242 4242 rlc r11,0x42424242
0x[0-9a-f]+ 202f 0f8b 0000 0000 rlc r0,0
44: ARC_32_ME foo
0x[0-9a-f]+ 202f 804b rlc.f r0,r1
0x[0-9a-f]+ 226f 804b rlc.f r2,0x1
0x[0-9a-f]+ 262f f10b rlc.f 0,r4
0x[0-9a-f]+ 252f 8f8b 0000 0200 rlc.f r5,0x200

37
gas/testsuite/gas/arc/rlc.s
View File

@ -6,53 +6,16 @@
rlc r0,0
rlc r1,-1
rlc 0,r2
rlc -1,r3
rlc r4,255
rlc 255,r5
rlc r6,-256
rlc -256,r7
rlc r8,256
rlc r9,-257
rlc r11,0x42424242
rlc 255,256
rlc r0,foo
rlc.al r0,r1
rlc.ra r3,r4
rlc.eq r6,r7
rlc.z r9,r10
rlc.ne r12,r13
rlc.nz r15,r16
rlc.pl r18,r19
rlc.p r21,r22
rlc.mi r24,r25
rlc.n r27,r28
rlc.cs r30,r31
rlc.c r33,r34
rlc.lo r36,r37
rlc.cc r39,r40
rlc.nc r42,r43
rlc.hs r45,r46
rlc.vs r48,r49
rlc.v r49,r50
rlc.vc r49,r55
rlc.nv r49,r58
rlc.gt r60,r60
rlc.ge r0,0
rlc.le 2,2
rlc.hi r3,r3
rlc.ls r4,r4
rlc.pnz r5,r5
rlc.f r0,r1
rlc.f r2,1
rlc.f 1,r3
rlc.f 0,r4
rlc.f r5,512
rlc.f 512,512
rlc.eq.f r0,r1
rlc.ne.f r1,0

106
gas/testsuite/gas/arc/ror.d
View File

@ -1,51 +1,61 @@
#as: -EL
#objdump: -dr -EL
#as: -mcpu=arc700
#objdump: -dr --prefix-addresses --show-raw-insn
.*: +file format elf32-.*arc
.*: +file format .*arc.*
Disassembly of section .text:
00000000 <.text>:
0: 00 86 00 18 18008600 ror r0,r1
4: 00 06 6e 1b 1b6e0600 ror fp,sp
8: 00 86 1f 18 181f8600 ror r0,0
c: ff 87 3f 18 183f87ff ror r1,-1
10: 00 06 e1 1f 1fe10600 ror 0,r2
14: 00 86 e1 1f 1fe18600 ror 0,r3
18: ff 86 9f 18 189f86ff ror r4,255
1c: 00 86 e2 1f 1fe28600 ror 0,r5
20: 00 87 df 18 18df8700 ror r6,-256
24: 00 86 e3 1f 1fe38600 ror 0,r7
28: 00 06 1f 19 191f0600 ror r8,0x100
2c: 00 01 00 00
30: 00 06 3f 19 193f0600 ror r9,0xffff_feff
34: ff fe ff ff
38: 00 06 7f 19 197f0600 ror r11,0x4242_4242
3c: 42 42 42 42
40: 00 06 ff 1f 1fff0600 ror 0,0x100
44: 00 01 00 00
48: 00 06 1f 18 181f0600 ror r0,0
4c: 00 00 00 00
4c: R_ARC_32 foo
50: 01 86 45 19 19458601 ror.z r10,r11
54: 02 86 86 19 19868602 ror.nz r12,r13
58: 0b 06 df 19 19df060b ror.lt r14,0
5c: 00 00 00 00
60: 09 06 ff 19 19ff0609 ror.gt r15,0x200
64: 00 02 00 00
68: 00 87 00 18 18008700 ror.f r0,r1
6c: 01 86 5e 18 185e8601 ror.f r2,1
70: 00 07 e2 1f 1fe20700 ror.f 0,r4
74: 00 07 bf 18 18bf0700 ror.f r5,0x200
78: 00 02 00 00
7c: 00 07 df 1f 1fdf0700 ror.f 0,0x200
80: 00 02 00 00
84: 01 87 00 18 18008701 ror.z.f r0,r1
88: 02 07 3f 18 183f0702 ror.nz.f r1,0
8c: 00 00 00 00
90: 0b 07 c1 1f 1fc1070b ror.lt.f 0,r2
94: 00 00 00 00 00000000
98: 0c 07 1f 18 181f070c ror.le.f r0,0x200
9c: 00 02 00 00
a0: 04 07 df 1f 1fdf0704 ror.n.f 0,0x200
a4: 00 02 00 00
0x[0-9a-f]+ 2903 0080 ror r0,r1,r2
0x[0-9a-f]+ 2b03 371a ror gp,fp,sp
0x[0-9a-f]+ 2e03 37dd ror ilink,r30,blink
0x[0-9a-f]+ 2943 0000 ror r0,r1,0
0x[0-9a-f]+ 2e03 7080 0000 0000 ror r0,0,r2
0x[0-9a-f]+ 2903 00be ror 0,r1,r2
0x[0-9a-f]+ 2903 0f80 ffff ffff ror r0,r1,0xffffffff
0x[0-9a-f]+ 2e03 7080 ffff ffff ror r0,0xffffffff,r2
0x[0-9a-f]+ 2903 0f80 0000 00ff ror r0,r1,0xff
0x[0-9a-f]+ 2e03 7080 0000 00ff ror r0,0xff,r2
0x[0-9a-f]+ 2903 0f80 ffff ff00 ror r0,r1,0xffffff00
0x[0-9a-f]+ 2e03 7080 ffff ff00 ror r0,0xffffff00,r2
0x[0-9a-f]+ 2903 0f80 0000 0100 ror r0,r1,0x100
0x[0-9a-f]+ 2e03 7080 ffff feff ror r0,0xfffffeff,r2
0x[0-9a-f]+ 2e03 7f80 0000 0100 ror r0,0x100,0x100
0x[0-9a-f]+ 2903 0f80 0000 0000 ror r0,r1,0
68: ARC_32_ME foo
0x[0-9a-f]+ 28c3 0080 ror r0,r0,r2
0x[0-9a-f]+ 2bc3 0140 ror r3,r3,r5
0x[0-9a-f]+ 2ec3 0201 ror.eq r6,r6,r8
0x[0-9a-f]+ 29c3 12c1 ror.eq r9,r9,r11
0x[0-9a-f]+ 2cc3 1382 ror.ne r12,r12,r14
0x[0-9a-f]+ 2fc3 1442 ror.ne r15,r15,r17
0x[0-9a-f]+ 2ac3 2503 ror.p r18,r18,r20
0x[0-9a-f]+ 2dc3 25c3 ror.p r21,r21,r23
0x[0-9a-f]+ 28c3 3684 ror.n r24,r24,gp
0x[0-9a-f]+ 2bc3 3744 ror.n fp,fp,ilink
0x[0-9a-f]+ 2ec3 37c5 ror.c r30,r30,blink
0x[0-9a-f]+ 2bc3 00c5 ror.c r3,r3,r3
0x[0-9a-f]+ 2bc3 0205 ror.c r3,r3,r8
0x[0-9a-f]+ 2bc3 0106 ror.nc r3,r3,r4
0x[0-9a-f]+ 2cc3 0106 ror.nc r4,r4,r4
0x[0-9a-f]+ 2cc3 01c6 ror.nc r4,r4,r7
0x[0-9a-f]+ 2cc3 0147 ror.v r4,r4,r5
0x[0-9a-f]+ 2dc3 0147 ror.v r5,r5,r5
0x[0-9a-f]+ 2dc3 0148 ror.nv r5,r5,r5
0x[0-9a-f]+ 2dc3 0148 ror.nv r5,r5,r5
0x[0-9a-f]+ 2ec3 0009 ror.gt r6,r6,r0
0x[0-9a-f]+ 28c3 002a ror.ge r0,r0,0
0x[0-9a-f]+ 29c3 006b ror.lt r1,r1,0x1
0x[0-9a-f]+ 2bc3 00ed ror.hi r3,r3,0x3
0x[0-9a-f]+ 2cc3 012e ror.ls r4,r4,0x4
0x[0-9a-f]+ 2dc3 016f ror.pnz r5,r5,0x5
0x[0-9a-f]+ 2903 8080 ror.f r0,r1,r2
0x[0-9a-f]+ 2943 8040 ror.f r0,r1,0x1
0x[0-9a-f]+ 2e03 f080 0000 0001 ror.f r0,0x1,r2
0x[0-9a-f]+ 2903 80be ror.f 0,r1,r2
0x[0-9a-f]+ 2903 8f80 0000 0200 ror.f r0,r1,0x200
0x[0-9a-f]+ 2e03 f080 0000 0200 ror.f r0,0x200,r2
0x[0-9a-f]+ 29c3 8081 ror.f.eq r1,r1,r2
0x[0-9a-f]+ 28c3 8022 ror.f.ne r0,r0,0
0x[0-9a-f]+ 2ac3 808b ror.f.lt r2,r2,r2
0x[0-9a-f]+ 2ec3 f0a9 0000 0001 ror.f.gt 0,0x1,0x2
0x[0-9a-f]+ 2ec3 ff8c 0000 0200 ror.f.le 0,0x200,0x200
0x[0-9a-f]+ 2ec3 f0aa 0000 0200 ror.f.ge 0,0x200,0x2

83
gas/testsuite/gas/arc/ror.s
View File

@ -1,38 +1,63 @@
# ror test
ror r0,r1
ror fp,sp
ror r0,r1,r2
ror r26,fp,sp
ror ilink1,ilink2,blink
ror r0,0
ror r1,-1
ror 0,r2
ror -1,r3
ror r4,255
ror 255,r5
ror r6,-256
ror -256,r7
ror r0,r1,0
ror r0,0,r2
ror 0,r1,r2
ror r0,r1,-1
ror r0,-1,r2
ror r0,r1,255
ror r0,255,r2
ror r0,r1,-256
ror r0,-256,r2
ror r8,256
ror r9,-257
ror r11,0x42424242
ror r0,r1,256
ror r0,-257,r2
ror 255,256
ror r0,256,256
ror r0,foo
ror r0,r1,foo
ror.eq r10,r11
ror.ne r12,r13
ror.lt r14,0
ror.gt r15,512
ror.al r0,r0,r2
ror.ra r3,r3,r5
ror.eq r6,r6,r8
ror.z r9,r9,r11
ror.ne r12,r12,r14
ror.nz r15,r15,r17
ror.pl r18,r18,r20
ror.p r21,r21,r23
ror.mi r24,r24,r26
ror.n r27,r27,r29
ror.cs r30,r30,r31
ror.c r3,r3,r3
ror.lo r3,r3,r8
ror.cc r3,r3,r4
ror.nc r4,r4,r4
ror.hs r4,r4,r7
ror.vs r4,r4,r5
ror.v r5,r5,r5
ror.vc r5,r5,r5
ror.nv r5,r5,r5
ror.gt r6,r6,r0
ror.ge r0,r0,0
ror.lt r1,r1,1
ror.hi r3,r3,3
ror.ls r4,r4,4
ror.pnz r5,r5,5
ror.f r0,r1
ror.f r2,1
ror.f 0,r4
ror.f r5,512
ror.f 512,512
ror.f r0,r1,r2
ror.f r0,r1,1
ror.f r0,1,r2
ror.f 0,r1,r2
ror.f r0,r1,512
ror.f r0,512,r2
ror.eq.f r0,r1
ror.ne.f r1,0
ror.lt.f 0,r2
ror.le.f r0,512
ror.n.f 512,512
ror.eq.f r1,r1,r2
ror.ne.f r0,r0,0
ror.lt.f r2,r2,r2
ror.gt.f 0,1,2
ror.le.f 0,512,512
ror.ge.f 0,512,2

67
gas/testsuite/gas/arc/rrc.d
View File

@ -1,51 +1,22 @@
#as: -EL
#objdump: -dr -EL
#as: -mcpu=arc700
#objdump: -dr --prefix-addresses --show-raw-insn
.*: +file format elf32-.*arc
.*: +file format .*arc.*
Disassembly of section .text:
00000000 <.text>:
0: 00 88 00 18 18008800 rrc r0,r1
4: 00 08 6e 1b 1b6e0800 rrc fp,sp
8: 00 88 1f 18 181f8800 rrc r0,0
c: ff 89 3f 18 183f89ff rrc r1,-1
10: 00 08 e1 1f 1fe10800 rrc 0,r2
14: 00 88 e1 1f 1fe18800 rrc 0,r3
18: ff 88 9f 18 189f88ff rrc r4,255
1c: 00 88 e2 1f 1fe28800 rrc 0,r5
20: 00 89 df 18 18df8900 rrc r6,-256
24: 00 88 e3 1f 1fe38800 rrc 0,r7
28: 00 08 1f 19 191f0800 rrc r8,0x100
2c: 00 01 00 00
30: 00 08 3f 19 193f0800 rrc r9,0xffff_feff
34: ff fe ff ff
38: 00 08 7f 19 197f0800 rrc r11,0x4242_4242
3c: 42 42 42 42
40: 00 08 ff 1f 1fff0800 rrc 0,0x100
44: 00 01 00 00
48: 00 08 1f 18 181f0800 rrc r0,0
4c: 00 00 00 00
4c: R_ARC_32 foo
50: 01 88 45 19 19458801 rrc.z r10,r11
54: 02 88 86 19 19868802 rrc.nz r12,r13
58: 0b 08 df 19 19df080b rrc.lt r14,0
5c: 00 00 00 00
60: 09 08 ff 19 19ff0809 rrc.gt r15,0x200
64: 00 02 00 00
68: 00 89 00 18 18008900 rrc.f r0,r1
6c: 01 88 5e 18 185e8801 rrc.f r2,1
70: 00 09 e2 1f 1fe20900 rrc.f 0,r4
74: 00 09 bf 18 18bf0900 rrc.f r5,0x200
78: 00 02 00 00
7c: 00 09 df 1f 1fdf0900 rrc.f 0,0x200
80: 00 02 00 00
84: 01 89 00 18 18008901 rrc.z.f r0,r1
88: 02 09 3f 18 183f0902 rrc.nz.f r1,0
8c: 00 00 00 00
90: 0b 09 c1 1f 1fc1090b rrc.lt.f 0,r2
94: 00 00 00 00 00000000
98: 0c 09 1f 18 181f090c rrc.le.f r0,0x200
9c: 00 02 00 00
a0: 04 09 df 1f 1fdf0904 rrc.n.f 0,0x200
a4: 00 02 00 00
0x[0-9a-f]+ 202f 0044 rrc r0,r1
0x[0-9a-f]+ 232f 3704 rrc fp,sp
0x[0-9a-f]+ 206f 0004 rrc r0,0
0x[0-9a-f]+ 212f 0f84 ffff ffff rrc r1,0xffffffff
0x[0-9a-f]+ 262f 7084 rrc 0,r2
0x[0-9a-f]+ 242f 0f84 0000 00ff rrc r4,0xff
0x[0-9a-f]+ 262f 0f84 ffff ff00 rrc r6,0xffffff00
0x[0-9a-f]+ 202f 1f84 0000 0100 rrc r8,0x100
0x[0-9a-f]+ 212f 1f84 ffff feff rrc r9,0xfffffeff
0x[0-9a-f]+ 232f 1f84 4242 4242 rrc r11,0x42424242
0x[0-9a-f]+ 202f 0f84 0000 0000 rrc r0,0
44: ARC_32_ME foo
0x[0-9a-f]+ 202f 8044 rrc.f r0,r1
0x[0-9a-f]+ 226f 8044 rrc.f r2,0x1
0x[0-9a-f]+ 262f f104 rrc.f 0,r4
0x[0-9a-f]+ 252f 8f84 0000 0200 rrc.f r5,0x200

17
gas/testsuite/gas/arc/rrc.s
View File

@ -6,33 +6,16 @@
rrc r0,0
rrc r1,-1
rrc 0,r2
rrc -1,r3
rrc r4,255
rrc 255,r5
rrc r6,-256
rrc -256,r7
rrc r8,256
rrc r9,-257
rrc r11,0x42424242
rrc 255,256
rrc r0,foo
rrc.eq r10,r11
rrc.ne r12,r13
rrc.lt r14,0
rrc.gt r15,512
rrc.f r0,r1
rrc.f r2,1
rrc.f 0,r4
rrc.f r5,512
rrc.f 512,512
rrc.eq.f r0,r1
rrc.ne.f r1,0
rrc.lt.f 0,r2
rrc.le.f r0,512
rrc.n.f 512,512

140
gas/testsuite/gas/arc/sbc.d
View File

@ -1,85 +1,61 @@
#as: -EL
#objdump: -dr -EL
#as: -mcpu=arc700
#objdump: -dr --prefix-addresses --show-raw-insn
.*: +file format elf32-.*arc
.*: +file format .*arc.*
Disassembly of section .text:
00000000 <.text>:
0: 00 84 00 58 58008400 sbc r0,r1,r2
4: 00 b8 4d 5b 5b4db800 sbc gp,fp,sp
8: 00 3e af 5b 5baf3e00 sbc ilink1,ilink2,blink
c: 00 f8 1d 5f 5f1df800 sbc r56,r59,lp_count
10: 00 fe 00 58 5800fe00 sbc r0,r1,0
14: 00 84 1f 58 581f8400 sbc r0,0,r2
18: 00 84 e0 5f 5fe08400 sbc 0,r1,r2
1c: ff ff 00 58 5800ffff sbc r0,r1,-1
20: ff 85 1f 58 581f85ff sbc r0,-1,r2
24: 00 84 e0 5f 5fe08400 sbc 0,r1,r2
28: ff fe 00 58 5800feff sbc r0,r1,255
2c: ff 84 1f 58 581f84ff sbc r0,255,r2
30: 00 84 e0 5f 5fe08400 sbc 0,r1,r2
34: 00 ff 00 58 5800ff00 sbc r0,r1,-256
38: 00 85 1f 58 581f8500 sbc r0,-256,r2
3c: 00 84 e0 5f 5fe08400 sbc 0,r1,r2
40: 00 fc 00 58 5800fc00 sbc r0,r1,0x100
44: 00 01 00 00
48: 00 04 1f 58 581f0400 sbc r0,0xffff_feff,r2
4c: ff fe ff ff
50: ff fc 1f 58 581ffcff sbc r0,255,0x100
54: 00 01 00 00
58: ff 7e 1f 58 581f7eff sbc r0,0x100,255
5c: 00 01 00 00
60: 00 fc 00 58 5800fc00 sbc r0,r1,0
64: 00 00 00 00
64: R_ARC_32 foo
68: 00 84 00 58 58008400 sbc r0,r1,r2
6c: 00 0a 62 58 58620a00 sbc r3,r4,r5
70: 01 90 c3 58 58c39001 sbc.z r6,r7,r8
74: 01 16 25 59 59251601 sbc.z r9,r10,r11
78: 02 9c 86 59 59869c02 sbc.nz r12,r13,r14
7c: 02 22 e8 59 59e82202 sbc.nz r15,r16,r17
80: 03 a8 49 5a 5a49a803 sbc.p r18,r19,r20
84: 03 2e ab 5a 5aab2e03 sbc.p r21,r22,r23
88: 04 b4 0c 5b 5b0cb404 sbc.n r24,r25,gp
8c: 04 3a 6e 5b 5b6e3a04 sbc.n fp,sp,ilink1
90: 05 c0 cf 5b 5bcfc005 sbc.c ilink2,blink,r32
94: 05 46 31 5c 5c314605 sbc.c r33,r34,r35
98: 05 cc 92 5c 5c92cc05 sbc.c r36,r37,r38
9c: 06 52 f4 5c 5cf45206 sbc.nc r39,r40,r41
a0: 06 d8 55 5d 5d55d806 sbc.nc r42,r43,r44
a4: 06 5e b7 5d 5db75e06 sbc.nc r45,r46,r47
a8: 07 e4 18 5e 5e18e407 sbc.v r48,r49,r50
ac: 07 6a 1a 5f 5f1a6a07 sbc.v r56,r52,r53
b0: 08 f0 1b 5f 5f1bf008 sbc.nv r56,r55,r56
b4: 08 76 1d 5f 5f1d7608 sbc.nv r56,r58,r59
b8: 09 00 9e 5f 5f9e0009 sbc.gt lp_count,lp_count,r0
bc: 0a 7c 00 58 58007c0a sbc.ge r0,r0,0
c0: 00 00 00 00
c4: 0b 02 3f 58 583f020b sbc.lt r1,1,r1
c8: 01 00 00 00
cc: 0d 06 7f 58 587f060d sbc.hi r3,3,r3
d0: 03 00 00 00
d4: 0e 08 df 5f 5fdf080e sbc.ls 0,4,r4
d8: 04 00 00 00
dc: 0f fc c2 5f 5fc2fc0f sbc.pnz 0,r5,5
e0: 05 00 00 00
e4: 00 85 00 58 58008500 sbc.f r0,r1,r2
e8: 01 fa 00 58 5800fa01 sbc.f r0,r1,1
ec: 01 84 1e 58 581e8401 sbc.f r0,1,r2
f0: 00 85 e0 5f 5fe08500 sbc.f 0,r1,r2
f4: 00 fd 00 58 5800fd00 sbc.f r0,r1,0x200
f8: 00 02 00 00
fc: 00 05 1f 58 581f0500 sbc.f r0,0x200,r2
100: 00 02 00 00
104: 01 85 00 58 58008501 sbc.z.f r0,r1,r2
108: 02 fd 00 58 5800fd02 sbc.nz.f r0,r1,0
10c: 00 00 00 00
110: 0b 05 1f 58 581f050b sbc.lt.f r0,0,r2
114: 00 00 00 00
118: 09 85 c0 5f 5fc08509 sbc.gt.f 0,r1,r2
11c: 00 00 00 00 00000000
120: 0c fd 00 58 5800fd0c sbc.le.f r0,r1,0x200
124: 00 02 00 00
128: 0a 05 1f 58 581f050a sbc.ge.f r0,0x200,r2
12c: 00 02 00 00
0x[0-9a-f]+ 2103 0080 sbc r0,r1,r2
0x[0-9a-f]+ 2303 371a sbc gp,fp,sp
0x[0-9a-f]+ 2603 37dd sbc ilink,r30,blink
0x[0-9a-f]+ 2143 0000 sbc r0,r1,0
0x[0-9a-f]+ 2603 7080 0000 0000 sbc r0,0,r2
0x[0-9a-f]+ 2103 00be sbc 0,r1,r2
0x[0-9a-f]+ 2103 0f80 ffff ffff sbc r0,r1,0xffffffff
0x[0-9a-f]+ 2603 7080 ffff ffff sbc r0,0xffffffff,r2
0x[0-9a-f]+ 2103 0f80 0000 00ff sbc r0,r1,0xff
0x[0-9a-f]+ 2603 7080 0000 00ff sbc r0,0xff,r2
0x[0-9a-f]+ 2103 0f80 ffff ff00 sbc r0,r1,0xffffff00
0x[0-9a-f]+ 2603 7080 ffff ff00 sbc r0,0xffffff00,r2
0x[0-9a-f]+ 2103 0f80 0000 0100 sbc r0,r1,0x100
0x[0-9a-f]+ 2603 7080 ffff feff sbc r0,0xfffffeff,r2
0x[0-9a-f]+ 2603 7f80 0000 0100 sbc r0,0x100,0x100
0x[0-9a-f]+ 2103 0f80 0000 0000 sbc r0,r1,0
68: ARC_32_ME foo
0x[0-9a-f]+ 20c3 0080 sbc r0,r0,r2
0x[0-9a-f]+ 23c3 0140 sbc r3,r3,r5
0x[0-9a-f]+ 26c3 0201 sbc.eq r6,r6,r8
0x[0-9a-f]+ 21c3 12c1 sbc.eq r9,r9,r11
0x[0-9a-f]+ 24c3 1382 sbc.ne r12,r12,r14
0x[0-9a-f]+ 27c3 1442 sbc.ne r15,r15,r17
0x[0-9a-f]+ 22c3 2503 sbc.p r18,r18,r20
0x[0-9a-f]+ 25c3 25c3 sbc.p r21,r21,r23
0x[0-9a-f]+ 20c3 3684 sbc.n r24,r24,gp
0x[0-9a-f]+ 23c3 3744 sbc.n fp,fp,ilink
0x[0-9a-f]+ 26c3 37c5 sbc.c r30,r30,blink
0x[0-9a-f]+ 23c3 00c5 sbc.c r3,r3,r3
0x[0-9a-f]+ 23c3 0205 sbc.c r3,r3,r8
0x[0-9a-f]+ 23c3 0106 sbc.nc r3,r3,r4
0x[0-9a-f]+ 24c3 0106 sbc.nc r4,r4,r4
0x[0-9a-f]+ 24c3 01c6 sbc.nc r4,r4,r7
0x[0-9a-f]+ 24c3 0147 sbc.v r4,r4,r5
0x[0-9a-f]+ 25c3 0147 sbc.v r5,r5,r5
0x[0-9a-f]+ 25c3 0148 sbc.nv r5,r5,r5
0x[0-9a-f]+ 25c3 0148 sbc.nv r5,r5,r5
0x[0-9a-f]+ 26c3 0009 sbc.gt r6,r6,r0
0x[0-9a-f]+ 20c3 002a sbc.ge r0,r0,0
0x[0-9a-f]+ 21c3 006b sbc.lt r1,r1,0x1
0x[0-9a-f]+ 23c3 00ed sbc.hi r3,r3,0x3
0x[0-9a-f]+ 24c3 012e sbc.ls r4,r4,0x4
0x[0-9a-f]+ 25c3 016f sbc.pnz r5,r5,0x5
0x[0-9a-f]+ 2103 8080 sbc.f r0,r1,r2
0x[0-9a-f]+ 2143 8040 sbc.f r0,r1,0x1
0x[0-9a-f]+ 2603 f080 0000 0001 sbc.f r0,0x1,r2
0x[0-9a-f]+ 2103 80be sbc.f 0,r1,r2
0x[0-9a-f]+ 2103 8f80 0000 0200 sbc.f r0,r1,0x200
0x[0-9a-f]+ 2603 f080 0000 0200 sbc.f r0,0x200,r2
0x[0-9a-f]+ 21c3 8081 sbc.f.eq r1,r1,r2
0x[0-9a-f]+ 20c3 8022 sbc.f.ne r0,r0,0
0x[0-9a-f]+ 22c3 808b sbc.f.lt r2,r2,r2
0x[0-9a-f]+ 26c3 f0a9 0000 0001 sbc.f.gt 0,0x1,0x2
0x[0-9a-f]+ 26c3 ff8c 0000 0200 sbc.f.le 0,0x200,0x200
0x[0-9a-f]+ 26c3 f0aa 0000 0200 sbc.f.ge 0,0x200,0x2

69
gas/testsuite/gas/arc/sbc.s
View File

@ -3,55 +3,50 @@
sbc r0,r1,r2
sbc r26,fp,sp
sbc ilink1,ilink2,blink
sbc r56,r59,lp_count
sbc r0,r1,0
sbc r0,0,r2
sbc 0,r1,r2
sbc r0,r1,-1
sbc r0,-1,r2
sbc -1,r1,r2
sbc r0,r1,255
sbc r0,255,r2
sbc 255,r1,r2
sbc r0,r1,-256
sbc r0,-256,r2
sbc -256,r1,r2
sbc r0,r1,256
sbc r0,-257,r2
sbc r0,255,256
sbc r0,256,255
sbc r0,256,256
sbc r0,r1,foo
sbc.al r0,r1,r2
sbc.ra r3,r4,r5
sbc.eq r6,r7,r8
sbc.z r9,r10,r11
sbc.ne r12,r13,r14
sbc.nz r15,r16,r17
sbc.pl r18,r19,r20
sbc.p r21,r22,r23
sbc.mi r24,r25,r26
sbc.n r27,r28,r29
sbc.cs r30,r31,r32
sbc.c r33,r34,r35
sbc.lo r36,r37,r38
sbc.cc r39,r40,r41
sbc.nc r42,r43,r44
sbc.hs r45,r46,r47
sbc.vs r48,r49,r50
sbc.v r56,r52,r53
sbc.vc r56,r55,r56
sbc.nv r56,r58,r59
sbc.gt r60,r60,r0
sbc.al r0,r0,r2
sbc.ra r3,r3,r5
sbc.eq r6,r6,r8
sbc.z r9,r9,r11
sbc.ne r12,r12,r14
sbc.nz r15,r15,r17
sbc.pl r18,r18,r20
sbc.p r21,r21,r23
sbc.mi r24,r24,r26
sbc.n r27,r27,r29
sbc.cs r30,r30,r31
sbc.c r3,r3,r3
sbc.lo r3,r3,r8
sbc.cc r3,r3,r4
sbc.nc r4,r4,r4
sbc.hs r4,r4,r7
sbc.vs r4,r4,r5
sbc.v r5,r5,r5
sbc.vc r5,r5,r5
sbc.nv r5,r5,r5
sbc.gt r6,r6,r0
sbc.ge r0,r0,0
sbc.lt r1,1,r1
sbc.hi r3,3,r3
sbc.ls 4,4,r4
sbc.pnz 5,r5,5
sbc.lt r1,r1,1
sbc.hi r3,r3,3
sbc.ls r4,r4,4
sbc.pnz r5,r5,5
sbc.f r0,r1,r2
sbc.f r0,r1,1
@ -60,9 +55,9 @@
sbc.f r0,r1,512
sbc.f r0,512,r2
sbc.eq.f r0,r1,r2
sbc.ne.f r0,r1,0
sbc.lt.f r0,0,r2
sbc.gt.f 0,r1,r2
sbc.le.f r0,r1,512
sbc.ge.f r0,512,r2
sbc.eq.f r1,r1,r2
sbc.ne.f r0,r0,0
sbc.lt.f r2,r2,r2
sbc.gt.f 0,1,2
sbc.le.f 0,512,512
sbc.ge.f 0,512,2

67
gas/testsuite/gas/arc/sexb.d
View File

@ -1,51 +1,22 @@
#as: -EL
#objdump: -dr -EL
#as: -mcpu=arc700
#objdump: -dr --prefix-addresses --show-raw-insn
.*: +file format elf32-.*arc
.*: +file format .*arc.*
Disassembly of section .text:
00000000 <.text>:
0: 00 8a 00 18 18008a00 sexb r0,r1
4: 00 0a 6e 1b 1b6e0a00 sexb fp,sp
8: 00 8a 1f 18 181f8a00 sexb r0,0
c: ff 8b 3f 18 183f8bff sexb r1,-1
10: 00 0a e1 1f 1fe10a00 sexb 0,r2
14: 00 8a e1 1f 1fe18a00 sexb 0,r3
18: ff 8a 9f 18 189f8aff sexb r4,255
1c: 00 8a e2 1f 1fe28a00 sexb 0,r5
20: 00 8b df 18 18df8b00 sexb r6,-256
24: 00 8a e3 1f 1fe38a00 sexb 0,r7
28: 00 0a 1f 19 191f0a00 sexb r8,0x100
2c: 00 01 00 00
30: 00 0a 3f 19 193f0a00 sexb r9,0xffff_feff
34: ff fe ff ff
38: 00 0a 7f 19 197f0a00 sexb r11,0x4242_4242
3c: 42 42 42 42
40: 00 0a ff 1f 1fff0a00 sexb 0,0x100
44: 00 01 00 00
48: 00 0a 1f 18 181f0a00 sexb r0,0
4c: 00 00 00 00
4c: R_ARC_32 foo
50: 01 8a 45 19 19458a01 sexb.z r10,r11
54: 02 8a 86 19 19868a02 sexb.nz r12,r13
58: 0b 0a df 19 19df0a0b sexb.lt r14,0
5c: 00 00 00 00
60: 09 0a ff 19 19ff0a09 sexb.gt r15,0x200
64: 00 02 00 00
68: 00 8b 00 18 18008b00 sexb.f r0,r1
6c: 01 8a 5e 18 185e8a01 sexb.f r2,1
70: 00 0b e2 1f 1fe20b00 sexb.f 0,r4
74: 00 0b bf 18 18bf0b00 sexb.f r5,0x200
78: 00 02 00 00
7c: 00 0b df 1f 1fdf0b00 sexb.f 0,0x200
80: 00 02 00 00
84: 01 8b 00 18 18008b01 sexb.z.f r0,r1
88: 02 0b 3f 18 183f0b02 sexb.nz.f r1,0
8c: 00 00 00 00
90: 0b 0b c1 1f 1fc10b0b sexb.lt.f 0,r2
94: 00 00 00 00 00000000
98: 0c 0b 1f 18 181f0b0c sexb.le.f r0,0x200
9c: 00 02 00 00
a0: 04 0b df 1f 1fdf0b04 sexb.n.f 0,0x200
a4: 00 02 00 00
0x[0-9a-f]+ 202f 0045 sexb r0,r1
0x[0-9a-f]+ 232f 3705 sexb fp,sp
0x[0-9a-f]+ 206f 0005 sexb r0,0
0x[0-9a-f]+ 212f 0f85 ffff ffff sexb r1,0xffffffff
0x[0-9a-f]+ 262f 7085 sexb 0,r2
0x[0-9a-f]+ 242f 0f85 0000 00ff sexb r4,0xff
0x[0-9a-f]+ 262f 0f85 ffff ff00 sexb r6,0xffffff00
0x[0-9a-f]+ 202f 1f85 0000 0100 sexb r8,0x100
0x[0-9a-f]+ 212f 1f85 ffff feff sexb r9,0xfffffeff
0x[0-9a-f]+ 232f 1f85 4242 4242 sexb r11,0x42424242
0x[0-9a-f]+ 202f 0f85 0000 0000 sexb r0,0
44: ARC_32_ME foo
0x[0-9a-f]+ 202f 8045 sexb.f r0,r1
0x[0-9a-f]+ 226f 8045 sexb.f r2,0x1
0x[0-9a-f]+ 262f f105 sexb.f 0,r4
0x[0-9a-f]+ 252f 8f85 0000 0200 sexb.f r5,0x200

17
gas/testsuite/gas/arc/sexb.s
View File

@ -6,33 +6,16 @@
sexb r0,0
sexb r1,-1
sexb 0,r2
sexb -1,r3
sexb r4,255
sexb 255,r5
sexb r6,-256
sexb -256,r7
sexb r8,256
sexb r9,-257
sexb r11,0x42424242
sexb 255,256
sexb r0,foo
sexb.eq r10,r11
sexb.ne r12,r13
sexb.lt r14,0
sexb.gt r15,512
sexb.f r0,r1
sexb.f r2,1
sexb.f 0,r4
sexb.f r5,512
sexb.f 512,512
sexb.eq.f r0,r1
sexb.ne.f r1,0
sexb.lt.f 0,r2
sexb.le.f r0,512
sexb.n.f 512,512

67
gas/testsuite/gas/arc/sexw.d
View File

@ -1,51 +1,22 @@
#as: -EL
#objdump: -dr -EL
#as: -mcpu=arc700
#objdump: -dr --prefix-addresses --show-raw-insn
.*: +file format elf32-.*arc
.*: +file format .*arc.*
Disassembly of section .text:
00000000 <.text>:
0: 00 8c 00 18 18008c00 sexw r0,r1
4: 00 0c 6e 1b 1b6e0c00 sexw fp,sp
8: 00 8c 1f 18 181f8c00 sexw r0,0
c: ff 8d 3f 18 183f8dff sexw r1,-1
10: 00 0c e1 1f 1fe10c00 sexw 0,r2
14: 00 8c e1 1f 1fe18c00 sexw 0,r3
18: ff 8c 9f 18 189f8cff sexw r4,255
1c: 00 8c e2 1f 1fe28c00 sexw 0,r5
20: 00 8d df 18 18df8d00 sexw r6,-256
24: 00 8c e3 1f 1fe38c00 sexw 0,r7
28: 00 0c 1f 19 191f0c00 sexw r8,0x100
2c: 00 01 00 00
30: 00 0c 3f 19 193f0c00 sexw r9,0xffff_feff
34: ff fe ff ff
38: 00 0c 7f 19 197f0c00 sexw r11,0x4242_4242
3c: 42 42 42 42
40: 00 0c ff 1f 1fff0c00 sexw 0,0x100
44: 00 01 00 00
48: 00 0c 1f 18 181f0c00 sexw r0,0
4c: 00 00 00 00
4c: R_ARC_32 foo
50: 01 8c 45 19 19458c01 sexw.z r10,r11
54: 02 8c 86 19 19868c02 sexw.nz r12,r13
58: 0b 0c df 19 19df0c0b sexw.lt r14,0
5c: 00 00 00 00
60: 09 0c ff 19 19ff0c09 sexw.gt r15,0x200
64: 00 02 00 00
68: 00 8d 00 18 18008d00 sexw.f r0,r1
6c: 01 8c 5e 18 185e8c01 sexw.f r2,1
70: 00 0d e2 1f 1fe20d00 sexw.f 0,r4
74: 00 0d bf 18 18bf0d00 sexw.f r5,0x200
78: 00 02 00 00
7c: 00 0d df 1f 1fdf0d00 sexw.f 0,0x200
80: 00 02 00 00
84: 01 8d 00 18 18008d01 sexw.z.f r0,r1
88: 02 0d 3f 18 183f0d02 sexw.nz.f r1,0
8c: 00 00 00 00
90: 0b 0d c1 1f 1fc10d0b sexw.lt.f 0,r2
94: 00 00 00 00 00000000
98: 0c 0d 1f 18 181f0d0c sexw.le.f r0,0x200
9c: 00 02 00 00
a0: 04 0d df 1f 1fdf0d04 sexw.n.f 0,0x200
a4: 00 02 00 00
0x[0-9a-f]+ 202f 0046 sex[wh]+ r0,r1
0x[0-9a-f]+ 232f 3706 sex[wh]+ fp,sp
0x[0-9a-f]+ 206f 0006 sex[wh]+ r0,0
0x[0-9a-f]+ 212f 0f86 ffff ffff sex[wh]+ r1,0xffffffff
0x[0-9a-f]+ 262f 7086 sex[wh]+ 0,r2
0x[0-9a-f]+ 242f 0f86 0000 00ff sex[wh]+ r4,0xff
0x[0-9a-f]+ 262f 0f86 ffff ff00 sex[wh]+ r6,0xffffff00
0x[0-9a-f]+ 202f 1f86 0000 0100 sex[wh]+ r8,0x100
0x[0-9a-f]+ 212f 1f86 ffff feff sex[wh]+ r9,0xfffffeff
0x[0-9a-f]+ 232f 1f86 4242 4242 sex[wh]+ r11,0x42424242
0x[0-9a-f]+ 202f 0f86 0000 0000 sex[wh]+ r0,0
44: ARC_32_ME foo
0x[0-9a-f]+ 202f 8046 sex[wh]+.f r0,r1
0x[0-9a-f]+ 226f 8046 sex[wh]+.f r2,0x1
0x[0-9a-f]+ 262f f106 sex[wh]+.f 0,r4
0x[0-9a-f]+ 252f 8f86 0000 0200 sex[wh]+.f r5,0x200

17
gas/testsuite/gas/arc/sexw.s
View File

@ -6,33 +6,16 @@
sexw r0,0
sexw r1,-1
sexw 0,r2
sexw -1,r3
sexw r4,255
sexw 255,r5
sexw r6,-256
sexw -256,r7
sexw r8,256
sexw r9,-257
sexw r11,0x42424242
sexw 255,256
sexw r0,foo
sexw.eq r10,r11
sexw.ne r12,r13
sexw.lt r14,0
sexw.gt r15,512
sexw.f r0,r1
sexw.f r2,1
sexw.f 0,r4
sexw.f r5,512
sexw.f 512,512
sexw.eq.f r0,r1
sexw.ne.f r1,0
sexw.lt.f 0,r2
sexw.le.f r0,512
sexw.n.f 512,512

12
gas/testsuite/gas/arc/sleep.d
View File

@ -1,11 +1,11 @@
#as: -EL -marc7
#objdump: -dr -EL
#as: -mcpu=arc700
#objdump: -dr --show-raw-insn
.*: +file format elf32-.*arc
.*: +file format .*arc.*
Disassembly of section .text:
00000000 <main>:
0: 00 84 00 40 40008400 add r0,r1,r2
4: 01 fe ff 1f 1ffffe01 sleep
8: 00 0a 62 50 50620a00 sub r3,r4,r5
0: 2100 0080 add r0,r1,r2
4: 216f 013f sleep 0x4
8: 2402 0143 sub r3,r4,r5

2
gas/testsuite/gas/arc/sleep.s
View File

@ -2,5 +2,5 @@
main:
add r0,r1,r2
sleep
sleep 0x04
sub r3,r4,r5

44
gas/testsuite/gas/arc/sshift.d
View File

@ -1,44 +0,0 @@
#objdump: -dr
#name: @OC@
# Test the @OC@ insn.
.*: +file format elf32-.*arc
Disassembly of section .text:
00000000 1800@I3+80@00 @OC@ r0,r1
00000004 1b6e@I3+00@00 @OC@ fp,sp
00000008 181f@I3+80@00 @OC@ r0,0
0000000c 183f@I3+81@ff @OC@ r1,-1
00000010 1fe1@I3+00@00 @OC@ 0,r2
00000014 1fe1@I3+81@ff @OC@ -1,r3
00000018 189f@I3+80@ff @OC@ r4,255
0000001c 1fe2@I3+80@ff @OC@ 255,r5
00000020 18df@I3+81@00 @OC@ r6,-256
00000024 1fe3@I3+81@00 @OC@ -256,r7
00000028 191f@I3+00@00 @OC@ r8,256
00000030 193f@I3+00@00 @OC@ r9,-257
00000038 1fc5@I3+00@00 @OC@ 511,r10
00000040 197f@I3+00@00 @OC@ r11,1111638594
00000048 1fc6@I3+00@00 @OC@ 305419896,r12
00000050 1fff@I3+00@ff @OC@ 255,256
00000058 1fdf@I3+80@ff @OC@ 256,255
00000060 181f@I3+00@00 @OC@ r0,0
RELOC: 00000064 R_ARC_32 foo
00000068 1945@I3+80@01 @OC@.eq r10,r11
0000006c 1986@I3+80@02 @OC@.ne r12,r13
00000070 19df@I3+00@0b @OC@.lt r14,0
00000078 19ff@I3+00@09 @OC@.gt r15,512
00000080 1800@I3+81@00 @OC@.f r0,r1
00000084 185e@I3+80@01 @OC@.f r2,1
00000088 1fa2@I3+00@00 @OC@.f 0,r4
0000008c 18bf@I3+01@00 @OC@.f r5,512
00000094 1fc3@I3+01@00 @OC@.f 512,r6
0000009c 1fdf@I3+01@00 @OC@.f 512,512
000000a4 1800@I3+81@01 @OC@.eq.f r0,r1
000000a8 183f@I3+01@02 @OC@.ne.f r1,0
000000b0 1fc1@I3+01@0b @OC@.lt.f 0,r2
000000b8 1fc1@I3+01@09 @OC@.gt.f 1,r2
000000c0 181f@I3+01@0c @OC@.le.f r0,512
000000c8 1fc1@I3+01@0a @OC@.ge.f 512,r2
000000d0 1fdf@I3+01@04 @OC@.n.f 512,512

52
gas/testsuite/gas/arc/sshift.s
View File

@ -1,52 +0,0 @@
# Single shift @OC@ test
# reg,reg
@OC@ r0,r1
@OC@ fp,sp
# shimm values
@OC@ r0,0
@OC@ r1,-1
@OC@ 0,r2
@OC@ -1,r3
@OC@ r4,255
@OC@ 255,r5
@OC@ r6,-256
@OC@ -256,r7
# limm values
@OC@ r8,256
@OC@ r9,-257
@OC@ 511,r10
@OC@ r11,0x42424242
@OC@ 0x12345678,r12
# shimm and limm
@OC@ 255,256
@OC@ 256,255
# symbols
@OC@ r0,foo
# conditional execution
@OC@.eq r10,r11
@OC@.ne r12,r13
@OC@.lt r14,0
@OC@.gt r15,512
# flag setting
@OC@.f r0,r1
@OC@.f r2,1
@OC@.f 0,r4
@OC@.f r5,512
@OC@.f 512,r6
@OC@.f 512,512
# conditional execution + flag setting
@OC@.eq.f r0,r1
@OC@.ne.f r1,0
@OC@.lt.f 0,r2
@OC@.gt.f 1,r2
@OC@.le.f r0,512
@OC@.ge.f 512,r2
@OC@.n.f 512,512

66
gas/testsuite/gas/arc/st.d
View File

@ -1,42 +1,32 @@
#as: -EL
#objdump: -dr -EL
#as: -mcpu=archs
#objdump: -dr --show-raw-insn
.*: +file format elf32-.*arc
.*: +file format .*arc.*
Disassembly of section .text:
00000000 <.text>:
0: 00 02 01 10 10010200 st r1,\[r2\]
4: 0e 02 01 10 1001020e st r1,\[r2,14\]
8: 00 02 41 10 10410200 stb r1,\[r2\]
c: 0e 82 01 11 1101820e st.a r1,\[r3,14\]
10: 02 02 81 11 11810202 stw.a r1,\[r2,2\]
14: 00 02 1f 10 101f0200 st r1,\[0x384\]
18: 84 03 00 00
1c: 00 7e 41 10 10417e00 stb 0,\[r2\]
20: f8 7f 01 10 10017ff8 st -8,\[r2,-8\]
24: 50 7e 1f 10 101f7e50 st 80,\[0x2ee\]
28: 9e 02 00 00
2c: 00 04 1f 10 101f0400 st r2,\[0\]
30: 00 00 00 00
30: R_ARC_32 foo
34: 02 02 01 14 14010202 st.di r1,\[r2,2\]
38: 03 02 01 15 15010203 st.a.di r1,\[r2,3\]
3c: 04 02 81 15 15810204 stw.a.di r1,\[r2,4\]
40: 04 7c 06 10 10067c04 st 80,\[r12,4\]
44: 50 00 00 00
44: R_ARC_32 .text
48: 04 7c 06 10 10067c04 st 20,\[r12,4\]
4c: 14 00 00 00
4c: R_ARC_B26 .text
50: 00 02 01 12 12010200 sr r1,\[r2\]
54: 0e 82 1f 12 121f820e sr r1,\[0xe\]
58: 00 fc 00 12 1200fc00 sr 0x3e8,\[r1\]
5c: e8 03 00 00
60: 64 7e 01 12 12017e64 sr 100,\[r2\]
64: 00 02 1f 12 121f0200 sr r1,\[0x2710\]
68: 10 27 00 00
6c: 64 7e 1f 12 121f7e64 sr 100,\[0x2710\]
70: 10 27 00 00
74: 64 fc 1f 12 121ffc64 sr 0x2710,\[0x64\]
78: 10 27 00 00
[0-9a-f]+ <.L1-0x40>:
0: 1a00 0040 st r1,\[r2\]
4: 1a0e 0040 st r1,\[r2,14\]
8: 1a00 0042 stb r1,\[r2\]
c: 1b0e 0048 st.aw r1,\[r3,14\]
10: 1a02 004c st[hw]+.aw r1,\[r2,2\]
14: 1e00 7040 0000 0384 st r1,\[0x384\]
1c: 1a00 0003 stb 0,\[r2\]
20: 1af8 8e01 st 56,\[r2,-8\]
24: 1e00 7080 0000 0000 st r2,\[0\]
28: ARC_32_ME foo
2c: 1a02 0060 st.di r1,\[r2,2\]
30: 1a03 0068 st.di.aw r1,\[r2,3\]
34: 1a04 006c st[hw]+.di.aw r1,\[r2,4\]
38: 1c04 1f80 0000 0000 st 0,\[r12,4\]
3c: ARC_32_ME .L1
[0-9a-f]+ <.L1>:
40: 212b 0080 sr r1,\[r2\]
44: 216b 0380 sr r1,\[0xe\]
48: 262b 7040 0000 03e8 sr 0x3e8,\[r1\]
50: 262b 7080 0000 0064 sr 0x64,\[r2\]
58: 212b 0f80 0000 2710 sr r1,\[0x2710\]
60: 266b 7fc0 0000 0064 sr 0x64,\[0x3f\]
68: 26ab 7901 0000 2710 sr 0x2710,\[100\]

8
gas/testsuite/gas/arc/st.s
View File

@ -8,14 +8,12 @@
st r1,[900]
stb 0,[r2]
st -8,[r2,-8]
st 80,[750]
st r2,[foo]
st r2,[@foo]
st.di r1,[r2,2]
st.a.di r1,[r2,3]
stw.a.di r1,[r2,4]
st .L1,[r12,4]
st .L1@h30,[r12,4]
st @.L1,[r12,4]
.L1:
sr r1,[r2]
@ -23,5 +21,5 @@
sr 1000, [r1]
sr 100, [r2]
sr r1,[10000]
sr 100,[10000]
sr 100,[63]
sr 10000,[100]

140
gas/testsuite/gas/arc/sub.d
View File

@ -1,85 +1,61 @@
#as: -EL
#objdump: -dr -EL
#as: -mcpu=arc700
#objdump: -dr --prefix-addresses --show-raw-insn
.*: +file format elf32-.*arc
.*: +file format .*arc.*
Disassembly of section .text:
00000000 <.text>:
0: 00 84 00 50 50008400 sub r0,r1,r2
4: 00 b8 4d 53 534db800 sub gp,fp,sp
8: 00 3e af 53 53af3e00 sub ilink1,ilink2,blink
c: 00 f8 1d 57 571df800 sub r56,r59,lp_count
10: 00 fe 00 50 5000fe00 sub r0,r1,0
14: 00 84 1f 50 501f8400 sub r0,0,r2
18: 00 84 e0 57 57e08400 sub 0,r1,r2
1c: ff ff 00 50 5000ffff sub r0,r1,-1
20: ff 85 1f 50 501f85ff sub r0,-1,r2
24: 00 84 e0 57 57e08400 sub 0,r1,r2
28: ff fe 00 50 5000feff sub r0,r1,255
2c: ff 84 1f 50 501f84ff sub r0,255,r2
30: 00 84 e0 57 57e08400 sub 0,r1,r2
34: 00 ff 00 50 5000ff00 sub r0,r1,-256
38: 00 85 1f 50 501f8500 sub r0,-256,r2
3c: 00 84 e0 57 57e08400 sub 0,r1,r2
40: 00 fc 00 50 5000fc00 sub r0,r1,0x100
44: 00 01 00 00
48: 00 04 1f 50 501f0400 sub r0,0xffff_feff,r2
4c: ff fe ff ff
50: ff fc 1f 50 501ffcff sub r0,255,0x100
54: 00 01 00 00
58: ff 7e 1f 50 501f7eff sub r0,0x100,255
5c: 00 01 00 00
60: 00 fc 00 50 5000fc00 sub r0,r1,0
64: 00 00 00 00
64: R_ARC_32 foo
68: 00 84 00 50 50008400 sub r0,r1,r2
6c: 00 0a 62 50 50620a00 sub r3,r4,r5
70: 01 90 c3 50 50c39001 sub.z r6,r7,r8
74: 01 16 25 51 51251601 sub.z r9,r10,r11
78: 02 9c 86 51 51869c02 sub.nz r12,r13,r14
7c: 02 22 e8 51 51e82202 sub.nz r15,r16,r17
80: 03 a8 49 52 5249a803 sub.p r18,r19,r20
84: 03 2e ab 52 52ab2e03 sub.p r21,r22,r23
88: 04 b4 0c 53 530cb404 sub.n r24,r25,gp
8c: 04 3a 6e 53 536e3a04 sub.n fp,sp,ilink1
90: 05 c0 cf 53 53cfc005 sub.c ilink2,blink,r32
94: 05 46 31 54 54314605 sub.c r33,r34,r35
98: 05 cc 92 54 5492cc05 sub.c r36,r37,r38
9c: 06 52 f4 54 54f45206 sub.nc r39,r40,r41
a0: 06 d8 55 55 5555d806 sub.nc r42,r43,r44
a4: 06 5e b7 55 55b75e06 sub.nc r45,r46,r47
a8: 07 e4 18 56 5618e407 sub.v r48,r49,r50
ac: 07 6a 1a 57 571a6a07 sub.v r56,r52,r53
b0: 08 f0 1b 57 571bf008 sub.nv r56,r55,r56
b4: 08 76 1d 57 571d7608 sub.nv r56,r58,r59
b8: 09 00 9e 57 579e0009 sub.gt lp_count,lp_count,r0
bc: 0a 7c 00 50 50007c0a sub.ge r0,r0,0
c0: 00 00 00 00
c4: 0b 02 3f 50 503f020b sub.lt r1,1,r1
c8: 01 00 00 00
cc: 0d 06 7f 50 507f060d sub.hi r3,3,r3
d0: 03 00 00 00
d4: 0e 08 df 57 57df080e sub.ls 0,4,r4
d8: 04 00 00 00
dc: 0f fc c2 57 57c2fc0f sub.pnz 0,r5,5
e0: 05 00 00 00
e4: 00 85 00 50 50008500 sub.f r0,r1,r2
e8: 01 fa 00 50 5000fa01 sub.f r0,r1,1
ec: 01 84 1e 50 501e8401 sub.f r0,1,r2
f0: 00 85 e0 57 57e08500 sub.f 0,r1,r2
f4: 00 fd 00 50 5000fd00 sub.f r0,r1,0x200
f8: 00 02 00 00
fc: 00 05 1f 50 501f0500 sub.f r0,0x200,r2
100: 00 02 00 00
104: 01 85 00 50 50008501 sub.z.f r0,r1,r2
108: 02 fd 00 50 5000fd02 sub.nz.f r0,r1,0
10c: 00 00 00 00
110: 0b 05 1f 50 501f050b sub.lt.f r0,0,r2
114: 00 00 00 00
118: 09 85 c0 57 57c08509 sub.gt.f 0,r1,r2
11c: 00 00 00 00 00000000
120: 0c fd 00 50 5000fd0c sub.le.f r0,r1,0x200
124: 00 02 00 00
128: 0a 05 1f 50 501f050a sub.ge.f r0,0x200,r2
12c: 00 02 00 00
0x[0-9a-f]+ 2102 0080 sub r0,r1,r2
0x[0-9a-f]+ 2302 371a sub gp,fp,sp
0x[0-9a-f]+ 2602 37dd sub ilink,r30,blink
0x[0-9a-f]+ 2142 0000 sub r0,r1,0
0x[0-9a-f]+ 2602 7080 0000 0000 sub r0,0,r2
0x[0-9a-f]+ 2102 00be sub 0,r1,r2
0x[0-9a-f]+ 2102 0f80 ffff ffff sub r0,r1,0xffffffff
0x[0-9a-f]+ 2602 7080 ffff ffff sub r0,0xffffffff,r2
0x[0-9a-f]+ 2102 0f80 0000 00ff sub r0,r1,0xff
0x[0-9a-f]+ 2602 7080 0000 00ff sub r0,0xff,r2
0x[0-9a-f]+ 2102 0f80 ffff ff00 sub r0,r1,0xffffff00
0x[0-9a-f]+ 2602 7080 ffff ff00 sub r0,0xffffff00,r2
0x[0-9a-f]+ 2102 0f80 0000 0100 sub r0,r1,0x100
0x[0-9a-f]+ 2602 7080 ffff feff sub r0,0xfffffeff,r2
0x[0-9a-f]+ 2602 7f80 0000 0100 sub r0,0x100,0x100
0x[0-9a-f]+ 2102 0f80 0000 0000 sub r0,r1,0
68: ARC_32_ME foo
0x[0-9a-f]+ 20c2 0080 sub r0,r0,r2
0x[0-9a-f]+ 23c2 0140 sub r3,r3,r5
0x[0-9a-f]+ 26c2 0201 sub.eq r6,r6,r8
0x[0-9a-f]+ 21c2 12c1 sub.eq r9,r9,r11
0x[0-9a-f]+ 24c2 1382 sub.ne r12,r12,r14
0x[0-9a-f]+ 27c2 1442 sub.ne r15,r15,r17
0x[0-9a-f]+ 22c2 2503 sub.p r18,r18,r20
0x[0-9a-f]+ 25c2 25c3 sub.p r21,r21,r23
0x[0-9a-f]+ 20c2 3684 sub.n r24,r24,gp
0x[0-9a-f]+ 23c2 3744 sub.n fp,fp,ilink
0x[0-9a-f]+ 26c2 37c5 sub.c r30,r30,blink
0x[0-9a-f]+ 23c2 00c5 sub.c r3,r3,r3
0x[0-9a-f]+ 23c2 0205 sub.c r3,r3,r8
0x[0-9a-f]+ 23c2 0106 sub.nc r3,r3,r4
0x[0-9a-f]+ 24c2 0106 sub.nc r4,r4,r4
0x[0-9a-f]+ 24c2 01c6 sub.nc r4,r4,r7
0x[0-9a-f]+ 24c2 0147 sub.v r4,r4,r5
0x[0-9a-f]+ 25c2 0147 sub.v r5,r5,r5
0x[0-9a-f]+ 25c2 0148 sub.nv r5,r5,r5
0x[0-9a-f]+ 25c2 0148 sub.nv r5,r5,r5
0x[0-9a-f]+ 26c2 0009 sub.gt r6,r6,r0
0x[0-9a-f]+ 20c2 002a sub.ge r0,r0,0
0x[0-9a-f]+ 21c2 006b sub.lt r1,r1,0x1
0x[0-9a-f]+ 23c2 00ed sub.hi r3,r3,0x3
0x[0-9a-f]+ 24c2 012e sub.ls r4,r4,0x4
0x[0-9a-f]+ 25c2 016f sub.pnz r5,r5,0x5
0x[0-9a-f]+ 2102 8080 sub.f r0,r1,r2
0x[0-9a-f]+ 2142 8040 sub.f r0,r1,0x1
0x[0-9a-f]+ 2602 f080 0000 0001 sub.f r0,0x1,r2
0x[0-9a-f]+ 2102 80be sub.f 0,r1,r2
0x[0-9a-f]+ 2102 8f80 0000 0200 sub.f r0,r1,0x200
0x[0-9a-f]+ 2602 f080 0000 0200 sub.f r0,0x200,r2
0x[0-9a-f]+ 21c2 8081 sub.f.eq r1,r1,r2
0x[0-9a-f]+ 20c2 8022 sub.f.ne r0,r0,0
0x[0-9a-f]+ 22c2 808b sub.f.lt r2,r2,r2
0x[0-9a-f]+ 26c2 f0a9 0000 0001 sub.f.gt 0,0x1,0x2
0x[0-9a-f]+ 26c2 ff8c 0000 0200 sub.f.le 0,0x200,0x200
0x[0-9a-f]+ 26c2 f0aa 0000 0200 sub.f.ge 0,0x200,0x2

69
gas/testsuite/gas/arc/sub.s
View File

@ -3,55 +3,50 @@
sub r0,r1,r2
sub r26,fp,sp
sub ilink1,ilink2,blink
sub r56,r59,lp_count
sub r0,r1,0
sub r0,0,r2
sub 0,r1,r2
sub r0,r1,-1
sub r0,-1,r2
sub -1,r1,r2
sub r0,r1,255
sub r0,255,r2
sub 255,r1,r2
sub r0,r1,-256
sub r0,-256,r2
sub -256,r1,r2
sub r0,r1,256
sub r0,-257,r2
sub r0,255,256
sub r0,256,255
sub r0,256,256
sub r0,r1,foo
sub.al r0,r1,r2
sub.ra r3,r4,r5
sub.eq r6,r7,r8
sub.z r9,r10,r11
sub.ne r12,r13,r14
sub.nz r15,r16,r17
sub.pl r18,r19,r20
sub.p r21,r22,r23
sub.mi r24,r25,r26
sub.n r27,r28,r29
sub.cs r30,r31,r32
sub.c r33,r34,r35
sub.lo r36,r37,r38
sub.cc r39,r40,r41
sub.nc r42,r43,r44
sub.hs r45,r46,r47
sub.vs r48,r49,r50
sub.v r56,r52,r53
sub.vc r56,r55,r56
sub.nv r56,r58,r59
sub.gt r60,r60,r0
sub.al r0,r0,r2
sub.ra r3,r3,r5
sub.eq r6,r6,r8
sub.z r9,r9,r11
sub.ne r12,r12,r14
sub.nz r15,r15,r17
sub.pl r18,r18,r20
sub.p r21,r21,r23
sub.mi r24,r24,r26
sub.n r27,r27,r29
sub.cs r30,r30,r31
sub.c r3,r3,r3
sub.lo r3,r3,r8
sub.cc r3,r3,r4
sub.nc r4,r4,r4
sub.hs r4,r4,r7
sub.vs r4,r4,r5
sub.v r5,r5,r5
sub.vc r5,r5,r5
sub.nv r5,r5,r5
sub.gt r6,r6,r0
sub.ge r0,r0,0
sub.lt r1,1,r1
sub.hi r3,3,r3
sub.ls 4,4,r4
sub.pnz 5,r5,5
sub.lt r1,r1,1
sub.hi r3,r3,3
sub.ls r4,r4,4
sub.pnz r5,r5,5
sub.f r0,r1,r2
sub.f r0,r1,1
@ -60,9 +55,9 @@
sub.f r0,r1,512
sub.f r0,512,r2
sub.eq.f r0,r1,r2
sub.ne.f r0,r1,0
sub.lt.f r0,0,r2
sub.gt.f 0,r1,r2
sub.le.f r0,r1,512
sub.ge.f r0,512,r2
sub.eq.f r1,r1,r2
sub.ne.f r0,r0,0
sub.lt.f r2,r2,r2
sub.gt.f 0,1,2
sub.le.f 0,512,512
sub.ge.f 0,512,2

12
gas/testsuite/gas/arc/swi.d
View File

@ -1,11 +1,11 @@
#as: -EL -marc8
#objdump: -dr -EL
#as: -mcpu=archs
#objdump: -dr --show-raw-insn
.*: +file format elf32-.*arc
.*: +file format .*arc.*
Disassembly of section .text:
00000000 <main>:
0: 00 84 00 40 40008400 add r0,r1,r2
4: 02 fe ff 1f 1ffffe02 swi
8: 00 0a 62 50 50620a00 sub r3,r4,r5
0: 2100 0080 add r0,r1,r2
4: 226f 003f swi
8: 2402 0143 sub r3,r4,r5

2
gas/testsuite/gas/arc/warn.exp
View File

@ -19,6 +19,6 @@
if [istarget arc*-*-*] {
load_lib gas-dg.exp
dg-init
dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/warn*.s]] "" ""
dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*warn*.s $srcdir/$subdir/*err*.s]] "" ""
dg-finish
}

10
gas/testsuite/gas/arc/warn.s
View File

@ -3,14 +3,10 @@
; { dg-do assemble { target arc-*-* } }
b.d foo
mov r0,256 ; { dg-warning "8 byte instruction in delay slot" "8 byte instruction in delay slot" }
mov r0,256
j.d foo ; { dg-warning "8 byte jump instruction with delay slot" "8 byte jump instruction with delay slot" }
j.d foo ; { dg-warning "inappropriate arguments for opcode" "inappropriate arguments for opcode" }
mov r0,r1
foo:
.extCoreRegister roscreg,45,r,can_shortcut
.extCoreRegister woscreg,46,w,can_shortcut
.section .text
add r0,woscreg,r1 ; { dg-warning "Error: attempt to read writeonly register" }
add roscreg,r1,r2 ; { dg-warning "Error: attempt to set readonly register" }

140
gas/testsuite/gas/arc/xor.d
View File

@ -1,85 +1,61 @@
#as: -EL
#objdump: -dr -EL
#as: -mcpu=arc700
#objdump: -dr --prefix-addresses --show-raw-insn
.*: +file format elf32-.*arc
.*: +file format .*arc.*
Disassembly of section .text:
00000000 <.text>:
0: 00 84 00 78 78008400 xor r0,r1,r2
4: 00 b8 4d 7b 7b4db800 xor gp,fp,sp
8: 00 3e af 7b 7baf3e00 xor ilink1,ilink2,blink
c: 00 f8 1d 7f 7f1df800 xor r56,r59,lp_count
10: 00 fe 00 78 7800fe00 xor r0,r1,0
14: 00 84 1f 78 781f8400 xor r0,0,r2
18: 00 84 e0 7f 7fe08400 xor 0,r1,r2
1c: ff ff 00 78 7800ffff xor r0,r1,-1
20: ff 85 1f 78 781f85ff xor r0,-1,r2
24: 00 84 e0 7f 7fe08400 xor 0,r1,r2
28: ff fe 00 78 7800feff xor r0,r1,255
2c: ff 84 1f 78 781f84ff xor r0,255,r2
30: 00 84 e0 7f 7fe08400 xor 0,r1,r2
34: 00 ff 00 78 7800ff00 xor r0,r1,-256
38: 00 85 1f 78 781f8500 xor r0,-256,r2
3c: 00 84 e0 7f 7fe08400 xor 0,r1,r2
40: 00 fc 00 78 7800fc00 xor r0,r1,0x100
44: 00 01 00 00
48: 00 04 1f 78 781f0400 xor r0,0xffff_feff,r2
4c: ff fe ff ff
50: ff fc 1f 78 781ffcff xor r0,255,0x100
54: 00 01 00 00
58: ff 7e 1f 78 781f7eff xor r0,0x100,255
5c: 00 01 00 00
60: 00 fc 00 78 7800fc00 xor r0,r1,0
64: 00 00 00 00
64: R_ARC_32 foo
68: 00 84 00 78 78008400 xor r0,r1,r2
6c: 00 0a 62 78 78620a00 xor r3,r4,r5
70: 01 90 c3 78 78c39001 xor.z r6,r7,r8
74: 01 16 25 79 79251601 xor.z r9,r10,r11
78: 02 9c 86 79 79869c02 xor.nz r12,r13,r14
7c: 02 22 e8 79 79e82202 xor.nz r15,r16,r17
80: 03 a8 49 7a 7a49a803 xor.p r18,r19,r20
84: 03 2e ab 7a 7aab2e03 xor.p r21,r22,r23
88: 04 b4 0c 7b 7b0cb404 xor.n r24,r25,gp
8c: 04 3a 6e 7b 7b6e3a04 xor.n fp,sp,ilink1
90: 05 c0 cf 7b 7bcfc005 xor.c ilink2,blink,r32
94: 05 46 31 7c 7c314605 xor.c r33,r34,r35
98: 05 cc 92 7c 7c92cc05 xor.c r36,r37,r38
9c: 06 52 f4 7c 7cf45206 xor.nc r39,r40,r41
a0: 06 d8 55 7d 7d55d806 xor.nc r42,r43,r44
a4: 06 5e b7 7d 7db75e06 xor.nc r45,r46,r47
a8: 07 e4 18 7e 7e18e407 xor.v r48,r49,r50
ac: 07 6a 1a 7f 7f1a6a07 xor.v r56,r52,r53
b0: 08 f0 1b 7f 7f1bf008 xor.nv r56,r55,r56
b4: 08 76 1d 7f 7f1d7608 xor.nv r56,r58,r59
b8: 09 00 9e 7f 7f9e0009 xor.gt lp_count,lp_count,r0
bc: 0a 7c 00 78 78007c0a xor.ge r0,r0,0
c0: 00 00 00 00
c4: 0b 02 3f 78 783f020b xor.lt r1,1,r1
c8: 01 00 00 00
cc: 0d 06 7f 78 787f060d xor.hi r3,3,r3
d0: 03 00 00 00
d4: 0e 08 df 7f 7fdf080e xor.ls 0,4,r4
d8: 04 00 00 00
dc: 0f fc c2 7f 7fc2fc0f xor.pnz 0,r5,5
e0: 05 00 00 00
e4: 00 85 00 78 78008500 xor.f r0,r1,r2
e8: 01 fa 00 78 7800fa01 xor.f r0,r1,1
ec: 01 84 1e 78 781e8401 xor.f r0,1,r2
f0: 00 85 e0 7f 7fe08500 xor.f 0,r1,r2
f4: 00 fd 00 78 7800fd00 xor.f r0,r1,0x200
f8: 00 02 00 00
fc: 00 05 1f 78 781f0500 xor.f r0,0x200,r2
100: 00 02 00 00
104: 01 85 00 78 78008501 xor.z.f r0,r1,r2
108: 02 fd 00 78 7800fd02 xor.nz.f r0,r1,0
10c: 00 00 00 00
110: 0b 05 1f 78 781f050b xor.lt.f r0,0,r2
114: 00 00 00 00
118: 09 85 c0 7f 7fc08509 xor.gt.f 0,r1,r2
11c: 00 00 00 00 00000000
120: 0c fd 00 78 7800fd0c xor.le.f r0,r1,0x200
124: 00 02 00 00
128: 0a 05 1f 78 781f050a xor.ge.f r0,0x200,r2
12c: 00 02 00 00
0x[0-9a-f]+ 2107 0080 xor r0,r1,r2
0x[0-9a-f]+ 2307 371a xor gp,fp,sp
0x[0-9a-f]+ 2607 37dd xor ilink,r30,blink
0x[0-9a-f]+ 2147 0000 xor r0,r1,0
0x[0-9a-f]+ 2607 7080 0000 0000 xor r0,0,r2
0x[0-9a-f]+ 2107 00be xor 0,r1,r2
0x[0-9a-f]+ 2107 0f80 ffff ffff xor r0,r1,0xffffffff
0x[0-9a-f]+ 2607 7080 ffff ffff xor r0,0xffffffff,r2
0x[0-9a-f]+ 2107 0f80 0000 00ff xor r0,r1,0xff
0x[0-9a-f]+ 2607 7080 0000 00ff xor r0,0xff,r2
0x[0-9a-f]+ 2107 0f80 ffff ff00 xor r0,r1,0xffffff00
0x[0-9a-f]+ 2607 7080 ffff ff00 xor r0,0xffffff00,r2
0x[0-9a-f]+ 2107 0f80 0000 0100 xor r0,r1,0x100
0x[0-9a-f]+ 2607 7080 ffff feff xor r0,0xfffffeff,r2
0x[0-9a-f]+ 2607 7f80 0000 0100 xor r0,0x100,0x100
0x[0-9a-f]+ 2107 0f80 0000 0000 xor r0,r1,0
68: ARC_32_ME foo
0x[0-9a-f]+ 20c7 0080 xor r0,r0,r2
0x[0-9a-f]+ 23c7 0140 xor r3,r3,r5
0x[0-9a-f]+ 26c7 0201 xor.eq r6,r6,r8
0x[0-9a-f]+ 21c7 12c1 xor.eq r9,r9,r11
0x[0-9a-f]+ 24c7 1382 xor.ne r12,r12,r14
0x[0-9a-f]+ 27c7 1442 xor.ne r15,r15,r17
0x[0-9a-f]+ 22c7 2503 xor.p r18,r18,r20
0x[0-9a-f]+ 25c7 25c3 xor.p r21,r21,r23
0x[0-9a-f]+ 20c7 3684 xor.n r24,r24,gp
0x[0-9a-f]+ 23c7 3744 xor.n fp,fp,ilink
0x[0-9a-f]+ 26c7 37c5 xor.c r30,r30,blink
0x[0-9a-f]+ 23c7 00c5 xor.c r3,r3,r3
0x[0-9a-f]+ 23c7 0205 xor.c r3,r3,r8
0x[0-9a-f]+ 23c7 0106 xor.nc r3,r3,r4
0x[0-9a-f]+ 24c7 0106 xor.nc r4,r4,r4
0x[0-9a-f]+ 24c7 01c6 xor.nc r4,r4,r7
0x[0-9a-f]+ 24c7 0147 xor.v r4,r4,r5
0x[0-9a-f]+ 25c7 0147 xor.v r5,r5,r5
0x[0-9a-f]+ 25c7 0148 xor.nv r5,r5,r5
0x[0-9a-f]+ 25c7 0148 xor.nv r5,r5,r5
0x[0-9a-f]+ 26c7 0009 xor.gt r6,r6,r0
0x[0-9a-f]+ 20c7 002a xor.ge r0,r0,0
0x[0-9a-f]+ 21c7 006b xor.lt r1,r1,0x1
0x[0-9a-f]+ 23c7 00ed xor.hi r3,r3,0x3
0x[0-9a-f]+ 24c7 012e xor.ls r4,r4,0x4
0x[0-9a-f]+ 25c7 016f xor.pnz r5,r5,0x5
0x[0-9a-f]+ 2107 8080 xor.f r0,r1,r2
0x[0-9a-f]+ 2147 8040 xor.f r0,r1,0x1
0x[0-9a-f]+ 2607 f080 0000 0001 xor.f r0,0x1,r2
0x[0-9a-f]+ 2107 80be xor.f 0,r1,r2
0x[0-9a-f]+ 2107 8f80 0000 0200 xor.f r0,r1,0x200
0x[0-9a-f]+ 2607 f080 0000 0200 xor.f r0,0x200,r2
0x[0-9a-f]+ 21c7 8081 xor.f.eq r1,r1,r2
0x[0-9a-f]+ 20c7 8022 xor.f.ne r0,r0,0
0x[0-9a-f]+ 22c7 808b xor.f.lt r2,r2,r2
0x[0-9a-f]+ 26c7 f0a9 0000 0001 xor.f.gt 0,0x1,0x2
0x[0-9a-f]+ 26c7 ff8c 0000 0200 xor.f.le 0,0x200,0x200
0x[0-9a-f]+ 26c7 f0aa 0000 0200 xor.f.ge 0,0x200,0x2

69
gas/testsuite/gas/arc/xor.s
View File

@ -3,55 +3,50 @@
xor r0,r1,r2
xor r26,fp,sp
xor ilink1,ilink2,blink
xor r56,r59,lp_count
xor r0,r1,0
xor r0,0,r2
xor 0,r1,r2
xor r0,r1,-1
xor r0,-1,r2
xor -1,r1,r2
xor r0,r1,255
xor r0,255,r2
xor 255,r1,r2
xor r0,r1,-256
xor r0,-256,r2
xor -256,r1,r2
xor r0,r1,256
xor r0,-257,r2
xor r0,255,256
xor r0,256,255
xor r0,256,256
xor r0,r1,foo
xor.al r0,r1,r2
xor.ra r3,r4,r5
xor.eq r6,r7,r8
xor.z r9,r10,r11
xor.ne r12,r13,r14
xor.nz r15,r16,r17
xor.pl r18,r19,r20
xor.p r21,r22,r23
xor.mi r24,r25,r26
xor.n r27,r28,r29
xor.cs r30,r31,r32
xor.c r33,r34,r35
xor.lo r36,r37,r38
xor.cc r39,r40,r41
xor.nc r42,r43,r44
xor.hs r45,r46,r47
xor.vs r48,r49,r50
xor.v r56,r52,r53
xor.vc r56,r55,r56
xor.nv r56,r58,r59
xor.gt r60,r60,r0
xor.al r0,r0,r2
xor.ra r3,r3,r5
xor.eq r6,r6,r8
xor.z r9,r9,r11
xor.ne r12,r12,r14
xor.nz r15,r15,r17
xor.pl r18,r18,r20
xor.p r21,r21,r23
xor.mi r24,r24,r26
xor.n r27,r27,r29
xor.cs r30,r30,r31
xor.c r3,r3,r3
xor.lo r3,r3,r8
xor.cc r3,r3,r4
xor.nc r4,r4,r4
xor.hs r4,r4,r7
xor.vs r4,r4,r5
xor.v r5,r5,r5
xor.vc r5,r5,r5
xor.nv r5,r5,r5
xor.gt r6,r6,r0
xor.ge r0,r0,0
xor.lt r1,1,r1
xor.hi r3,3,r3
xor.ls 4,4,r4
xor.pnz 5,r5,5
xor.lt r1,r1,1
xor.hi r3,r3,3
xor.ls r4,r4,4
xor.pnz r5,r5,5
xor.f r0,r1,r2
xor.f r0,r1,1
@ -60,9 +55,9 @@
xor.f r0,r1,512
xor.f r0,512,r2
xor.eq.f r0,r1,r2
xor.ne.f r0,r1,0
xor.lt.f r0,0,r2
xor.gt.f 0,r1,r2
xor.le.f r0,r1,512
xor.ge.f r0,512,r2
xor.eq.f r1,r1,r2
xor.ne.f r0,r0,0
xor.lt.f r2,r2,r2
xor.gt.f 0,1,2
xor.le.f 0,512,512
xor.ge.f 0,512,2

3
gas/testsuite/gas/elf/elf.exp
View File

@ -90,6 +90,7 @@ if { [is_elf_format] } then {
# optimization because it interfers with link-time relaxation of
# function prologues.
if {![istarget "mn10300-*-*"]
&& ![istarget "arc-*-*"]
&& ![istarget "xtensa*-*-*"]
&& ![istarget "msp430*-*-*"]
&& ![istarget "nds32*-*-*"]
@ -148,7 +149,7 @@ if { [is_elf_format] } then {
# against ordinary symbols into relocations against section symbols.
# This is usually revealed by the error message:
# symbol `sym' required but not present
setup_xfail "m681*-*-*" "m68hc*-*-*"
setup_xfail "m681*-*-*" "m68hc*-*-*" "arc-*-*"
run_dump_test redef
run_dump_test equ-reloc
}

4
include/ChangeLog
View File

@ -1,3 +1,7 @@
2015-10-07 Claudiu Zissulescu <claziss@synopsys.com>
* dis-asm.h (arc_get_disassembler): Correct declaration.
2015-09-30 Nick Clifton <nickc@redhat.com>
Import the following patches from the GCC mainline:

Some files were not shown because too many files have changed in this diff Show More