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gas/testsuite/
2008-01-24 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/x86-64-sib.s: Add tests for r12. * gas/i386/x86-64-sib-intel.d: Updated. * gas/i386/x86-64-sib.d: Likewise. opcodes/ 2008-01-24 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (OP_E_extended): Handle r12 like rsp.
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H.J. Lu
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dd6be23411
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82c18208b8
@ -1,3 +1,10 @@
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2008-01-24 H.J. Lu <hongjiu.lu@intel.com>
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* gas/i386/x86-64-sib.s: Add tests for r12.
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* gas/i386/x86-64-sib-intel.d: Updated.
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* gas/i386/x86-64-sib.d: Likewise.
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2008-01-23 H.J. Lu <hongjiu.lu@intel.com>
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* gas/i386/i386.exp : Run x86-64-arch-1 and x86-64-arch-10.
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@ -28,9 +28,16 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: 8b 04 e3 mov eax,DWORD PTR \[rbx\+riz\*8\]
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[ ]*[a-f0-9]+: 8b 04 24 mov eax,DWORD PTR \[rsp\]
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[ ]*[a-f0-9]+: 8b 04 24 mov eax,DWORD PTR \[rsp\]
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[ ]*[a-f0-9]+: 8b 04 24 mov eax,DWORD PTR \[rsp\]
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[ ]*[a-f0-9]+: 8b 04 64 mov eax,DWORD PTR \[rsp\+riz\*2\]
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[ ]*[a-f0-9]+: 8b 04 a4 mov eax,DWORD PTR \[rsp\+riz\*4\]
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[ ]*[a-f0-9]+: 8b 04 e4 mov eax,DWORD PTR \[rsp\+riz\*8\]
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[ ]*[a-f0-9]+: 41 8b 04 24 mov eax,DWORD PTR \[r12\]
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[ ]*[a-f0-9]+: 41 8b 04 24 mov eax,DWORD PTR \[r12\]
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[ ]*[a-f0-9]+: 41 8b 04 24 mov eax,DWORD PTR \[r12\]
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[ ]*[a-f0-9]+: 41 8b 04 64 mov eax,DWORD PTR \[r12\+riz\*2\]
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[ ]*[a-f0-9]+: 41 8b 04 a4 mov eax,DWORD PTR \[r12\+riz\*4\]
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[ ]*[a-f0-9]+: 41 8b 04 e4 mov eax,DWORD PTR \[r12\+riz\*8\]
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[ ]*[a-f0-9]+: 8b 04 25 e2 ff ff ff mov eax,DWORD PTR ds:0xffffffffffffffe2
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[ ]*[a-f0-9]+: 8b 04 65 e2 ff ff ff mov eax,DWORD PTR \[riz\*2-0x1e\]
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[ ]*[a-f0-9]+: 8b 04 a5 e2 ff ff ff mov eax,DWORD PTR \[riz\*4-0x1e\]
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@ -50,4 +57,10 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: 8b 04 64 mov eax,DWORD PTR \[rsp\+riz\*2\]
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[ ]*[a-f0-9]+: 8b 04 a4 mov eax,DWORD PTR \[rsp\+riz\*4\]
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[ ]*[a-f0-9]+: 8b 04 e4 mov eax,DWORD PTR \[rsp\+riz\*8\]
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[ ]*[a-f0-9]+: 41 8b 04 24 mov eax,DWORD PTR \[r12\]
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[ ]*[a-f0-9]+: 41 8b 04 24 mov eax,DWORD PTR \[r12\]
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[ ]*[a-f0-9]+: 41 8b 04 24 mov eax,DWORD PTR \[r12\]
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[ ]*[a-f0-9]+: 41 8b 04 64 mov eax,DWORD PTR \[r12\+riz\*2\]
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[ ]*[a-f0-9]+: 41 8b 04 a4 mov eax,DWORD PTR \[r12\+riz\*4\]
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[ ]*[a-f0-9]+: 41 8b 04 e4 mov eax,DWORD PTR \[r12\+riz\*8\]
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#pass
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@ -27,9 +27,16 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: 8b 04 e3 mov \(%rbx,%riz,8\),%eax
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[ ]*[a-f0-9]+: 8b 04 24 mov \(%rsp\),%eax
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[ ]*[a-f0-9]+: 8b 04 24 mov \(%rsp\),%eax
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[ ]*[a-f0-9]+: 8b 04 24 mov \(%rsp\),%eax
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[ ]*[a-f0-9]+: 8b 04 64 mov \(%rsp,%riz,2\),%eax
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[ ]*[a-f0-9]+: 8b 04 a4 mov \(%rsp,%riz,4\),%eax
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[ ]*[a-f0-9]+: 8b 04 e4 mov \(%rsp,%riz,8\),%eax
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[ ]*[a-f0-9]+: 41 8b 04 24 mov \(%r12\),%eax
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[ ]*[a-f0-9]+: 41 8b 04 24 mov \(%r12\),%eax
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[ ]*[a-f0-9]+: 41 8b 04 24 mov \(%r12\),%eax
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[ ]*[a-f0-9]+: 41 8b 04 64 mov \(%r12,%riz,2\),%eax
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[ ]*[a-f0-9]+: 41 8b 04 a4 mov \(%r12,%riz,4\),%eax
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[ ]*[a-f0-9]+: 41 8b 04 e4 mov \(%r12,%riz,8\),%eax
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[ ]*[a-f0-9]+: 8b 04 25 e2 ff ff ff mov 0xffffffffffffffe2,%eax
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[ ]*[a-f0-9]+: 8b 04 65 e2 ff ff ff mov -0x1e\(,%riz,2\),%eax
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[ ]*[a-f0-9]+: 8b 04 a5 e2 ff ff ff mov -0x1e\(,%riz,4\),%eax
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@ -49,4 +56,10 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: 8b 04 64 mov \(%rsp,%riz,2\),%eax
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[ ]*[a-f0-9]+: 8b 04 a4 mov \(%rsp,%riz,4\),%eax
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[ ]*[a-f0-9]+: 8b 04 e4 mov \(%rsp,%riz,8\),%eax
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[ ]*[a-f0-9]+: 41 8b 04 24 mov \(%r12\),%eax
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[ ]*[a-f0-9]+: 41 8b 04 24 mov \(%r12\),%eax
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[ ]*[a-f0-9]+: 41 8b 04 24 mov \(%r12\),%eax
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[ ]*[a-f0-9]+: 41 8b 04 64 mov \(%r12,%riz,2\),%eax
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[ ]*[a-f0-9]+: 41 8b 04 a4 mov \(%r12,%riz,4\),%eax
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[ ]*[a-f0-9]+: 41 8b 04 e4 mov \(%r12,%riz,8\),%eax
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#pass
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@ -22,10 +22,17 @@ foo:
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mov (%rbx,%riz,4),%eax
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mov (%rbx,%riz,8),%eax
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mov (%rsp),%eax
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mov (%rsp,%riz),%eax
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mov (%rsp,%riz,1),%eax
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mov (%rsp,%riz,2),%eax
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mov (%rsp,%riz,4),%eax
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mov (%rsp,%riz,8),%eax
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mov (%r12),%eax
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mov (%r12,%riz),%eax
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mov (%r12,%riz,1),%eax
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mov (%r12,%riz,2),%eax
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mov (%r12,%riz,4),%eax
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mov (%r12,%riz,8),%eax
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.intel_syntax noprefix
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mov eax,DWORD PTR [riz*1-30]
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mov eax,DWORD PTR [riz*2-30]
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@ -46,4 +53,9 @@ foo:
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mov eax,DWORD PTR [rsp+riz*2]
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mov eax,DWORD PTR [rsp+riz*4]
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mov eax,DWORD PTR [rsp+riz*8]
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.p2align 4
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mov eax,DWORD PTR [r12]
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mov eax,DWORD PTR [r12+riz]
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mov eax,DWORD PTR [r12+riz*1]
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mov eax,DWORD PTR [r12+riz*2]
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mov eax,DWORD PTR [r12+riz*4]
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mov eax,DWORD PTR [r12+riz*8]
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@ -1,3 +1,7 @@
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2008-01-24 H.J. Lu <hongjiu.lu@intel.com>
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* i386-dis.c (OP_E_extended): Handle r12 like rsp.
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2008-01-23 H.J. Lu <hongjiu.lu@intel.com>
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* i386-gen.c (cpu_flag_init): Add CpuLM to CPU_GENERIC64_FLAGS.
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@ -6645,7 +6645,7 @@ OP_E_extended (int bytemode, int sizeflag, int has_drex)
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int havebase;
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int haveindex;
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int needindex;
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int base;
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int base, rbase;
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int index = 0;
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int scale = 0;
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@ -6667,7 +6667,7 @@ OP_E_extended (int bytemode, int sizeflag, int has_drex)
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haveindex = index != 4;
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codep++;
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}
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base += add;
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rbase = base + add;
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/* If we have a DREX byte, skip it now
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(it has already been handled) */
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@ -6680,7 +6680,7 @@ OP_E_extended (int bytemode, int sizeflag, int has_drex)
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switch (modrm.mod)
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{
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case 0:
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if ((base & 7) == 5)
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if (base == 5)
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{
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havebase = 0;
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if (address_mode == mode_64bit && !havesib)
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@ -6710,7 +6710,7 @@ OP_E_extended (int bytemode, int sizeflag, int has_drex)
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|| (havesib && (haveindex || scale != 0)));
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if (!intel_syntax)
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if (modrm.mod != 0 || (base & 7) == 5)
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if (modrm.mod != 0 || base == 5)
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{
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if (havedisp || riprel)
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print_displacement (scratchbuf, disp);
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@ -6738,7 +6738,7 @@ OP_E_extended (int bytemode, int sizeflag, int has_drex)
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*obufp = '\0';
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if (havebase)
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oappend (address_mode == mode_64bit && (sizeflag & AFLAG)
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? names64[base] : names32[base]);
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? names64[rbase] : names32[rbase]);
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if (havesib)
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{
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/* ESP/RSP won't allow index. If base isn't ESP/RSP,
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@ -6769,7 +6769,7 @@ OP_E_extended (int bytemode, int sizeflag, int has_drex)
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}
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}
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if (intel_syntax
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&& (disp || modrm.mod != 0 || (base & 7) == 5))
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&& (disp || modrm.mod != 0 || base == 5))
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{
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if (!havedisp || (bfd_signed_vma) disp >= 0)
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{
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@ -6795,7 +6795,7 @@ OP_E_extended (int bytemode, int sizeflag, int has_drex)
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}
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else if (intel_syntax)
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{
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if (modrm.mod != 0 || (base & 7) == 5)
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if (modrm.mod != 0 || base == 5)
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{
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if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
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| PREFIX_ES | PREFIX_FS | PREFIX_GS))
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