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RISC-V: Add RV32E support.
Kito Cheng <kito.cheng@gmail.com> Monk Chiang <sh.chiang04@gmail.com> bfd/ * elfnn-riscv.c (_bfd_riscv_elf_merge_private_bfd_data): Handle EF_RISCV_RVE. binutils/ * readelf.c (get_machine_flags): Handle EF_RISCV_RVE. gas/ * config/tc-riscv.c (rve_abi): New. (riscv_set_options): Add rve field. Initialize it. (riscv_set_rve) New function. (riscv_set_arch): Support 'e' ISA subset. (reg_lookup_internal): If rve, check register is available. (riscv_set_abi): New parameter rve. (md_parse_option): Pass new argument to riscv_set_abi. (riscv_after_parse_args): Call riscv_set_rve. If rve_abi, set EF_RISCV_RVE. * doc/c-riscv.texi (-mabi): Document new ilp32e argument. include/ * elf/riscv.h (EF_RISCV_RVE): New define.
This commit is contained in:
Jim Wilson
parent
400174b12a
commit
7f99954970
@ -1,3 +1,8 @@
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2018-05-18 Kito Cheng <kito.cheng@gmail.com>
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* elfnn-riscv.c (_bfd_riscv_elf_merge_private_bfd_data): Handle
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EF_RISCV_RVE.
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2018-05-18 Jim Wilson <jimw@sifive.com>
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* elfnn-riscv.c (allocate_dynrelocs): Discard dynamic relocations if
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@ -2625,6 +2625,14 @@ _bfd_riscv_elf_merge_private_bfd_data (bfd *ibfd, struct bfd_link_info *info)
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goto fail;
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}
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/* Disallow linking RVE and non-RVE. */
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if ((old_flags ^ new_flags) & EF_RISCV_RVE)
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{
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(*_bfd_error_handler)
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(_("%pB: can't link RVE with other target"), ibfd);
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goto fail;
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}
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/* Allow linking RVC and non-RVC, and keep the RVC flag. */
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elf_elfheader (obfd)->e_flags |= new_flags & EF_RISCV_RVC;
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@ -1,3 +1,7 @@
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2018-05-18 Kito Cheng <kito.cheng@gmail.com>
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* readelf.c (get_machine_flags): Handle EF_RISCV_RVE.
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2018-05-18 John Darrington <john@darrington.wattle.id.au>
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* readelf.c: Add support for s12z architecture.
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@ -3472,6 +3472,9 @@ get_machine_flags (Filedata * filedata, unsigned e_flags, unsigned e_machine)
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if (e_flags & EF_RISCV_RVC)
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strcat (buf, ", RVC");
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if (e_flags & EF_RISCV_RVE)
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strcat (buf, ", RVE");
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switch (e_flags & EF_RISCV_FLOAT_ABI)
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{
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case EF_RISCV_FLOAT_ABI_SOFT:
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@ -1,3 +1,18 @@
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2018-05-18 Kito Cheng <kito.cheng@gmail.com>
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Monk Chiang <sh.chiang04@gmail.com>
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Jim Wilson <jimw@sifive.com>
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* config/tc-riscv.c (rve_abi): New.
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(riscv_set_options): Add rve field. Initialize it.
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(riscv_set_rve) New function.
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(riscv_set_arch): Support 'e' ISA subset.
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(reg_lookup_internal): If rve, check register is available.
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(riscv_set_abi): New parameter rve.
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(md_parse_option): Pass new argument to riscv_set_abi.
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(riscv_after_parse_args): Call riscv_set_rve. If rve_abi, set
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EF_RISCV_RVE.
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* doc/c-riscv.texi (-mabi): Document new ilp32e argument.
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2018-05-18 John Darrington <john@darrington.wattle.id.au>
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* Makefile.am: Add support for s12z target.
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@ -63,6 +63,7 @@ static const char default_arch[] = DEFAULT_ARCH;
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static unsigned xlen = 0; /* width of an x-register */
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static unsigned abi_xlen = 0; /* width of a pointer in the ABI */
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static bfd_boolean rve_abi = FALSE;
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#define LOAD_ADDRESS_INSN (abi_xlen == 64 ? "ld" : "lw")
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#define ADD32_INSN (xlen == 64 ? "addiw" : "addi")
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@ -75,6 +76,7 @@ struct riscv_set_options
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{
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int pic; /* Generate position-independent code. */
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int rvc; /* Generate RVC code. */
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int rve; /* Generate RVE code. */
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int relax; /* Emit relocs the linker is allowed to relax. */
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};
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@ -82,6 +84,7 @@ static struct riscv_set_options riscv_opts =
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{
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0, /* pic */
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0, /* rvc */
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0, /* rve */
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1, /* relax */
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};
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@ -94,6 +97,12 @@ riscv_set_rvc (bfd_boolean rvc_value)
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riscv_opts.rvc = rvc_value;
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}
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static void
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riscv_set_rve (bfd_boolean rve_value)
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{
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riscv_opts.rve = rve_value;
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}
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struct riscv_subset
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{
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const char *name;
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@ -171,6 +180,16 @@ riscv_set_arch (const char *s)
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case 'i':
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break;
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case 'e':
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p++;
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riscv_add_subset ("e");
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riscv_add_subset ("i");
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if (xlen > 32)
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as_fatal ("-march=%s: rv%de is not a valid base ISA", s, xlen);
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break;
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case 'g':
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p++;
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for ( ; *all_subsets != 'q'; all_subsets++)
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@ -181,7 +200,7 @@ riscv_set_arch (const char *s)
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break;
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default:
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as_fatal ("-march=%s: first ISA subset must be `i' or `g'", s);
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as_fatal ("-march=%s: first ISA subset must be `e', `i' or `g'", s);
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}
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while (*p)
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@ -215,6 +234,18 @@ riscv_set_arch (const char *s)
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as_fatal ("-march=%s: unsupported ISA subset `%c'", s, *p);
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}
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if (riscv_subset_supports ("e") && riscv_subset_supports ("f"))
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as_fatal ("-march=%s: rv32e does not support the `f' extension", s);
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if (riscv_subset_supports ("d") && !riscv_subset_supports ("f"))
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as_fatal ("-march=%s: `d' extension requires `f' extension", s);
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if (riscv_subset_supports ("q") && !riscv_subset_supports ("d"))
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as_fatal ("-march=%s: `q' extension requires `d' extension", s);
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if (riscv_subset_supports ("q") && xlen < 64)
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as_fatal ("-march=%s: rv32 does not support the `q' extension", s);
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free (extension);
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}
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@ -546,6 +577,10 @@ reg_lookup_internal (const char *s, enum reg_class class)
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if (r == NULL || DECODE_REG_CLASS (r) != class)
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return -1;
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if (riscv_opts.rve && class == RCLASS_GPR && DECODE_REG_NUM (r) > 15)
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return -1;
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return DECODE_REG_NUM (r);
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}
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@ -2165,10 +2200,11 @@ enum float_abi {
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static enum float_abi float_abi = FLOAT_ABI_DEFAULT;
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static void
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riscv_set_abi (unsigned new_xlen, enum float_abi new_float_abi)
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riscv_set_abi (unsigned new_xlen, enum float_abi new_float_abi, bfd_boolean rve)
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{
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abi_xlen = new_xlen;
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float_abi = new_float_abi;
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rve_abi = rve;
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}
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int
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@ -2190,21 +2226,23 @@ md_parse_option (int c, const char *arg)
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case OPTION_MABI:
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if (strcmp (arg, "ilp32") == 0)
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riscv_set_abi (32, FLOAT_ABI_SOFT);
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riscv_set_abi (32, FLOAT_ABI_SOFT, FALSE);
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else if (strcmp (arg, "ilp32e") == 0)
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riscv_set_abi (32, FLOAT_ABI_SOFT, TRUE);
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else if (strcmp (arg, "ilp32f") == 0)
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riscv_set_abi (32, FLOAT_ABI_SINGLE);
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riscv_set_abi (32, FLOAT_ABI_SINGLE, FALSE);
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else if (strcmp (arg, "ilp32d") == 0)
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riscv_set_abi (32, FLOAT_ABI_DOUBLE);
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riscv_set_abi (32, FLOAT_ABI_DOUBLE, FALSE);
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else if (strcmp (arg, "ilp32q") == 0)
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riscv_set_abi (32, FLOAT_ABI_QUAD);
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riscv_set_abi (32, FLOAT_ABI_QUAD, FALSE);
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else if (strcmp (arg, "lp64") == 0)
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riscv_set_abi (64, FLOAT_ABI_SOFT);
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riscv_set_abi (64, FLOAT_ABI_SOFT, FALSE);
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else if (strcmp (arg, "lp64f") == 0)
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riscv_set_abi (64, FLOAT_ABI_SINGLE);
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riscv_set_abi (64, FLOAT_ABI_SINGLE, FALSE);
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else if (strcmp (arg, "lp64d") == 0)
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riscv_set_abi (64, FLOAT_ABI_DOUBLE);
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riscv_set_abi (64, FLOAT_ABI_DOUBLE, FALSE);
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else if (strcmp (arg, "lp64q") == 0)
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riscv_set_abi (64, FLOAT_ABI_QUAD);
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riscv_set_abi (64, FLOAT_ABI_QUAD, FALSE);
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else
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return 0;
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break;
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@ -2247,6 +2285,11 @@ riscv_after_parse_args (void)
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else
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riscv_add_subset ("c");
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/* Enable RVE if specified by the -march option. */
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riscv_set_rve (FALSE);
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if (riscv_subset_supports ("e"))
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riscv_set_rve (TRUE);
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/* Infer ABI from ISA if not specified on command line. */
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if (abi_xlen == 0)
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abi_xlen = xlen;
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@ -2271,6 +2314,9 @@ riscv_after_parse_args (void)
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}
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}
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if (rve_abi)
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elf_flags |= EF_RISCV_RVE;
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/* Insert float_abi into the EF_RISCV_FLOAT_ABI field of elf_flags. */
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elf_flags |= float_abi * (EF_RISCV_FLOAT_ABI & ~(EF_RISCV_FLOAT_ABI << 1));
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}
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@ -46,7 +46,8 @@ Select the base isa, as specified by ISA. For example -march=rv32ima.
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Selects the ABI, which is either "ilp32" or "lp64", optionally followed
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by "f", "d", or "q" to indicate single-precision, double-precision, or
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quad-precision floating-point calling convention, or none to indicate
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the soft-float calling convention.
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the soft-float calling convention. Also, "ilp32" can optionally be followed
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by "e" to indicate the RVE ABI, which is always soft-float.
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@cindex @samp{-mrelax} option, RISC-V
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@item -mrelax
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@ -1,3 +1,7 @@
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2018-05-18 Kito Cheng <kito.cheng@gmail.com>
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* elf/riscv.h (EF_RISCV_RVE): New define.
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2018-05-18 John Darrington <john@darrington.wattle.id.au>
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* elf/s12z.h: New header.
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@ -110,6 +110,9 @@ END_RELOC_NUMBERS (R_RISCV_max)
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/* File uses the quad-float ABI. */
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#define EF_RISCV_FLOAT_ABI_QUAD 0x0006
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/* File uses the 32E base integer instruction. */
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#define EF_RISCV_RVE 0x0008
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/* The name of the global pointer symbol. */
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#define RISCV_GP_SYMBOL "__global_pointer$"
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