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[binutils][aarch64] SVE2 feature extension flags.

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Include all feature flag macros.

The "sve2" extension that enables the core sve2 instructions.
This also enables the sve extension, since sve is a requirement of sve2.

Extra optional sve2 features are the bitperm, sm4, aes, and sha3 extensions.
These are all given extra feature flags, "bitperm", "sve2-sm4",
"sve2-aes", and "sve2-sha3" respectively.
The sm4, aes, and sha3 extensions are explicitly marked as sve2
extensions to distinguish them from the corresponding NEON extensions.

Rather than continue extending the current feature flag numbers, I used
some bits that have been skipped.

gas/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

	* config/tc-aarch64.c: Add command line architecture feature flags
	"sve2", "sve2-sm4", "sve2-aes", "sve2-sha3", "bitperm".
	* doc/c-aarch64.texi: Document new architecture feature flags.

include/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

	* opcode/aarch64.h (AARCH64_FEATURE_SVE2
	AARCH64_FEATURE_SVE2_AES, AARCH64_FEATURE_SVE2_BITPERM,
	AARCH64_FEATURE_SVE2_SM4, AARCH64_FEATURE_SVE2_SHA3): New
	feature macros.

opcodes/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

	* aarch64-tbl.h
	(aarch64_feature_sve2, aarch64_feature_sve2aes,
	aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
	aarch64_feature_sve2bitperm): New feature sets.
	(SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
	for feature set addresses.
	(SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
	SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
This commit is contained in:
Matthew Malcomson 2019-05-09 10:29:12 +01:00
parent dd3189990b
commit 7ce2460a77
7 changed files with 90 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
gas/ChangeLog
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@ -1,3 +1,9 @@
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-aarch64.c: Add command line architecture feature flags
"sve2", "sve2-sm4", "sve2-aes", "sve2-sha3", "bitperm".
* doc/c-aarch64.texi: Document new architecture feature flags.
2019-05-08 Alan Modra <amodra@gmail.com>
* testsuite/gas/elf/dwarf2-1.s,

13
gas/config/tc-aarch64.c
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@ -8874,6 +8874,19 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
AARCH64_ARCH_NONE},
{"memtag", AARCH64_FEATURE (AARCH64_FEATURE_MEMTAG, 0),
AARCH64_ARCH_NONE},
{"sve2", AARCH64_FEATURE (AARCH64_FEATURE_SVE2, 0),
AARCH64_FEATURE (AARCH64_FEATURE_SVE, 0)},
{"sve2-sm4", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_SM4, 0),
AARCH64_FEATURE (AARCH64_FEATURE_SVE2
| AARCH64_FEATURE_SM4, 0)},
{"sve2-aes", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_AES, 0),
AARCH64_FEATURE (AARCH64_FEATURE_SVE2
| AARCH64_FEATURE_AES, 0)},
{"sve2-sha3", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_SHA3, 0),
AARCH64_FEATURE (AARCH64_FEATURE_SVE2
| AARCH64_FEATURE_SHA3, 0)},
{"bitperm", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_BITPERM, 0),
AARCH64_FEATURE (AARCH64_FEATURE_SVE2, 0)},
{NULL, AARCH64_ARCH_NONE, AARCH64_ARCH_NONE},
};

10
gas/doc/c-aarch64.texi
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@ -196,6 +196,16 @@ automatically cause those extensions to be disabled.
@tab Enable ARMv8.5-A Memory Tagging Extensions.
@item @code{tme} @tab ARMv8-A @tab No
@tab Enable Transactional Memory Extensions.
@item @code{sve2} @tab ARMv8-A @tab No
@tab Enable the SVE2 Extension.
@item @code{bitperm} @tab ARMv8-A @tab No
@tab Enable SVE2 BITPERM Extension.
@item @code{sve2-sm4} @tab ARMv8-A @tab No
@tab Enable SVE2 SM4 Extension.
@item @code{sve2-aes} @tab ARMv8-A @tab No
@tab Enable SVE2 AES Extension.
@item @code{sve2-sha3} @tab ARMv8-A @tab No
@tab Enable SVE2 SHA3 Extension.
@end multitable
@node AArch64 Syntax

7
include/ChangeLog
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@ -1,3 +1,10 @@
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_SVE2
AARCH64_FEATURE_SVE2_AES, AARCH64_FEATURE_SVE2_BITPERM,
AARCH64_FEATURE_SVE2_SM4, AARCH64_FEATURE_SVE2_SHA3): New
feature macros.
2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
Faraz Shahbazker <fshahbazker@wavecomp.com>

7
include/opcode/aarch64.h
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@ -89,6 +89,13 @@ typedef uint32_t aarch64_insn;
/* Transactional Memory Extension. */
#define AARCH64_FEATURE_TME 0x2000000000000ULL
/* SVE2 instructions. */
#define AARCH64_FEATURE_SVE2 0x000000010
#define AARCH64_FEATURE_SVE2_AES 0x000000080
#define AARCH64_FEATURE_SVE2_BITPERM 0x000000100
#define AARCH64_FEATURE_SVE2_SM4 0x000000200
#define AARCH64_FEATURE_SVE2_SHA3 0x000000400
/* Architectures are the sum of the base and extensions. */
#define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
AARCH64_FEATURE_FP \

11
opcodes/ChangeLog
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@ -1,3 +1,14 @@
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-tbl.h
(aarch64_feature_sve2, aarch64_feature_sve2aes,
aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
aarch64_feature_sve2bitperm): New feature sets.
(SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
for feature set addresses.
(SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
Faraz Shahbazker <fshahbazker@wavecomp.com>

36
opcodes/aarch64-tbl.h
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@ -2206,6 +2206,16 @@ static const aarch64_feature_set aarch64_feature_memtag =
AARCH64_FEATURE (AARCH64_FEATURE_V8_5 | AARCH64_FEATURE_MEMTAG, 0);
static const aarch64_feature_set aarch64_feature_tme =
AARCH64_FEATURE (AARCH64_FEATURE_TME, 0);
static const aarch64_feature_set aarch64_feature_sve2 =
AARCH64_FEATURE (AARCH64_FEATURE_SVE2, 0);
static const aarch64_feature_set aarch64_feature_sve2aes =
AARCH64_FEATURE (AARCH64_FEATURE_SVE2 | AARCH64_FEATURE_SVE2_AES, 0);
static const aarch64_feature_set aarch64_feature_sve2sha3 =
AARCH64_FEATURE (AARCH64_FEATURE_SVE2 | AARCH64_FEATURE_SVE2_SHA3, 0);
static const aarch64_feature_set aarch64_feature_sve2sm4 =
AARCH64_FEATURE (AARCH64_FEATURE_SVE2 | AARCH64_FEATURE_SVE2_SM4, 0);
static const aarch64_feature_set aarch64_feature_sve2bitperm =
AARCH64_FEATURE (AARCH64_FEATURE_SVE2 | AARCH64_FEATURE_SVE2_BITPERM, 0);
#define CORE &aarch64_feature_v8
@ -2242,6 +2252,11 @@ static const aarch64_feature_set aarch64_feature_tme =
#define BTI &aarch64_feature_bti
#define MEMTAG &aarch64_feature_memtag
#define TME &aarch64_feature_tme
#define SVE2 &aarch64_feature_sve2
#define SVE2_AES &aarch64_feature_sve2aes
#define SVE2_SHA3 &aarch64_feature_sve2sha3
#define SVE2_SM4 &aarch64_feature_sve2sm4
#define SVE2_BITPERM &aarch64_feature_sve2bitperm
#define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL }
@ -2311,6 +2326,27 @@ static const aarch64_feature_set aarch64_feature_tme =
{ NAME, OPCODE, MASK, CLASS, 0, MEMTAG, OPS, QUALS, FLAGS, 0, 0, NULL }
#define _TME_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, OP, TME, OPS, QUALS, FLAGS, 0, 0, NULL }
#define SVE2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
{ NAME, OPCODE, MASK, CLASS, OP, SVE2, OPS, QUALS, \
FLAGS | F_STRICT, 0, TIED, NULL }
#define SVE2_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \
{ NAME, OPCODE, MASK, CLASS, OP, SVE2, OPS, QUALS, \
FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL }
#define SVE2AES_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
{ NAME, OPCODE, MASK, CLASS, OP, SVE2_AES, OPS, QUALS, \
FLAGS | F_STRICT, 0, TIED, NULL }
#define SVE2SHA3_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
{ NAME, OPCODE, MASK, CLASS, OP, SVE2_SHA3, OPS, QUALS, \
FLAGS | F_STRICT, 0, TIED, NULL }
#define SVE2SM4_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
{ NAME, OPCODE, MASK, CLASS, OP, SVE2_SM4, OPS, QUALS, \
FLAGS | F_STRICT, 0, TIED, NULL }
#define SVE2SM4_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \
{ NAME, OPCODE, MASK, CLASS, OP, SVE2_SM4, OPS, QUALS, \
FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL }
#define SVE2BITPERM_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
{ NAME, OPCODE, MASK, CLASS, OP, SVE2_BITPERM, OPS, QUALS, \
FLAGS | F_STRICT, 0, TIED, NULL }
struct aarch64_opcode aarch64_opcode_table[] =
{