mirror of
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aarch64: Add support for sme2.1 zero instructions.
This patch adds support for following sme2.1 zero instructions and the spec is available here [1]. 1. ZERO (single-vector). 2. ZERO (double-vector). 3. ZERO (quad-vector). The VECTOR GROUP symbols VGx2 and VGx4 are optional for the assembler for most of the sme and sve instructions. But for few of the sme2.1 zero instruction variants VECTOR GROUP symbols VGx2 and VGx4 are mandatory. To address this a bit "F_VG_REQ" is introduced in this patch, on setting F_VG_REQ bit in flags of aarch64_opcode forces the assembler to accept instruction operand only having VECTOR GROUP symbols. [1]: https://developer.arm.com/documentation/ddi0602/2024-03/SME-Instructions?lang=en
This commit is contained in:
Srinath Parvathaneni
Richard Earnshaw
parent
6ab366f264
commit
7bdb051fd6
@ -1,5 +1,5 @@
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[^:]*: Assembler messages:
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[^:]*:[0-9]+: Error: expected '{' at operand 1 -- `zero za'
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[^:]*:[0-9]+: Error: expected '\[' at operand 1 -- `zero za'
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[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `zero {za8\.d}'
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[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `zero {za0\.d,za8.d}'
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[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `zero {za2\.h}'
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4
gas/testsuite/gas/aarch64/sme2p1-5-bad.d
Normal file
4
gas/testsuite/gas/aarch64/sme2p1-5-bad.d
Normal file
@ -0,0 +1,4 @@
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#name: Negative test of SME2.1 ZERO instructions.
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#as: -march=armv9.4-a+sme2p1
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#source: sme2p1-5-bad.s
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#error_output: sme2p1-5-bad.l
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103
gas/testsuite/gas/aarch64/sme2p1-5-bad.l
Normal file
103
gas/testsuite/gas/aarch64/sme2p1-5-bad.l
Normal file
@ -0,0 +1,103 @@
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.*: Assembler messages:
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.*: Error: operand mismatch -- `zero za.s\[w8,0,vgx2\]'
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.*: Info: did you mean this\?
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.*: Info: zero za.d\[w8, 0, vgx2\]
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.*: Error: operand mismatch -- `zero za.b\[w14,0,vgx2\]'
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.*: Info: did you mean this\?
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.*: Info: zero za.d\[w14, 0, vgx2\]
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.*: Error: expected a selection register in the range w8-w11 at operand 1 -- `zero za.d\[w2,7,vgx2\]'
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.*: Error: immediate offset out of range 0 to 7 at operand 1 -- `zero za.d\[w11,17,vgx2\]'
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.*: Error: invalid vector group size at operand 1 -- `zero za.d\[w9,4,vgx3\]'
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.*: Error: operand mismatch -- `zero za.h\[w10,3\]'
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.*: Info: did you mean this\?
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.*: Info: zero za.d\[w10, 3\]
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.*: Error: operand mismatch -- `zero za.s\[w18,0,vgx4\]'
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.*: Info: did you mean this\?
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.*: Info: zero za.d\[w18, 0, vgx4\]
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.*: Error: operand mismatch -- `zero za.b\[w1,0,vgx4\]'
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.*: Info: did you mean this\?
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.*: Info: zero za.d\[w1, 0, vgx4\]
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.*: Error: operand mismatch -- `zero za.q\[w8,17,vgx2\]'
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.*: Info: did you mean this\?
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.*: Info: zero za.d\[w8, 17, vgx2\]
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.*: Error: invalid vector group size at operand 1 -- `zero za.h\[w11,7,vgx3\]'
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.*: Error: expected a constant immediate offset at operand 1 -- `zero za.s\[w9,vg\]'
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.*: Error: operand mismatch -- `zero za.b\[w10,3\]'
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.*: Info: did you mean this\?
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.*: Info: zero za.d\[w10, 3\]
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.*: Error: operand mismatch -- `zero za.s\[w18,0:1\]'
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.*: Info: did you mean this\?
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.*: Info: zero za.d\[w18, 0:1\]
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.*: Error: operand mismatch -- `zero za.s\[w1,0:1\]'
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.*: Info: did you mean this\?
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.*: Info: zero za.d\[w1, 0:1\]
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.*: Error: operand mismatch -- `zero za.b\[w8,4:5\]'
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.*: Info: did you mean this\?
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.*: Info: zero za.d\[w8, 4:5\]
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.*: Error: operand mismatch -- `zero za.b\[w11,1:5\]'
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.*: Info: did you mean this\?
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.*: Info: zero za.d\[w11, 1:5\]
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.*: Error: operand mismatch -- `zero za.h\[w9,2:13\]'
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.*: Info: did you mean this\?
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.*: Info: zero za.d\[w9, 2:13\]
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.*: Error: the last offset is less than the first offset at operand 1 -- `zero za.h\[w10,16:7\]'
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.*: Error: operand mismatch -- `zero za.s\[w18,0:3,vgx2\]'
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.*: Info: did you mean this\?
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.*: Info: zero za.d\[w18, 0:3, vgx2\]
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.*: Error: operand mismatch -- `zero za.b\[w1,0:1,vgx4\]'
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.*: Info: did you mean this\?
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.*: Info: zero za.d\[w1, 0:1, vgx4\]
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.*: Error: invalid vector group size at operand 1 -- `zero za.h\[w8,6:7,vg\]'
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.*: Error: invalid vector group size at operand 1 -- `zero za.q\[w9,12:13,vgx3\]'
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.*: Error: operand mismatch -- `zero za.s\[w18,0:1,vgx4\]'
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.*: Info: did you mean this\?
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.*: Info: zero za.d\[w18, 0:1, vgx4\]
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.*: Error: invalid vector group size at operand 1 -- `zero za.h\[w1,0:1,vgx3\]'
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.*: Error: operand mismatch -- `zero za.b\[w8,16:17,vgx4\]'
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.*: Info: did you mean this\?
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.*: Info: zero za.d\[w8, 16:17, vgx4\]
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.*: Error: operand mismatch -- `zero za.q\[w9,12:13\]'
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.*: Info: did you mean this\?
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.*: Info: zero za.d\[w9, 12:13\]
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.*: Error: invalid vector group size at operand 1 -- `zero za.s\[w18,0:3,\]'
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.*: Error: operand mismatch -- `zero za.s\[w1,0:3\]'
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.*: Info: did you mean this\?
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.*: Info: zero za.d\[w1, 0:3\]
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.*: Error: operand mismatch -- `zero za.b\[w8,8:11\]'
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.*: Info: did you mean this\?
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.*: Info: zero za.d\[w8, 8:11\]
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.*: Error: the last offset is less than the first offset at operand 1 -- `zero za.b\[w11,18:1,vgx3\]'
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.*: Error: operand mismatch -- `zero za.h\[w9,4\]'
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.*: Info: did you mean this\?
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.*: Info: zero za.d\[w9, 4\]
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.*: Error: operand mismatch -- `zero za.h\[w10,10:13\]'
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.*: Info: did you mean this\?
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.*: Info: zero za.d\[w10, 10:13\]
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.*: Error: operand mismatch -- `zero za.s\[w18,0:3,vgx2\]'
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.*: Info: did you mean this\?
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.*: Info: zero za.d\[w18, 0:3, vgx2\]
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.*: Error: operand mismatch -- `zero za.s\[w1,0:3,vgx2\]'
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.*: Info: did you mean this\?
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.*: Info: zero za.d\[w1, 0:3, vgx2\]
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.*: Error: operand mismatch -- `zero za.b\[w8,14:17,vgx2\]'
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.*: Info: did you mean this\?
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.*: Info: zero za.d\[w8, 14:17, vgx2\]
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.*: Error: invalid vector group size at operand 1 -- `zero za.b\[w11,4:7,vg\]'
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.*: Error: operand mismatch -- `zero za.h\[w9,0:3\]'
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.*: Info: did you mean this\?
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.*: Info: zero za.d\[w9, 0:3\]
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.*: Error: expected a constant immediate offset at operand 1 -- `zero za.q\[w10,vgx2\]'
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.*: Error: operand mismatch -- `zero za.s\[w18,0:3,vgx4\]'
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.*: Info: did you mean this\?
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.*: Info: zero za.d\[w18, 0:3, vgx4\]
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.*: Error: operand mismatch -- `zero za.s\[w1,0:3,vgx4\]'
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.*: Info: did you mean this\?
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.*: Info: zero za.d\[w1, 0:3, vgx4\]
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.*: Error: operand mismatch -- `zero za.b\[w8,14:17,vgx4\]'
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.*: Info: did you mean this\?
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.*: Info: zero za.d\[w8, 14:17, vgx4\]
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.*: Error: invalid vector group size at operand 1 -- `zero za.b\[w11,4:7,vg\]'
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.*: Error: invalid vector group size at operand 1 -- `zero za.h\[w9,0:3,vgx3\]'
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.*: Error: operand mismatch -- `zero za.q\[w10,4\]'
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.*: Info: did you mean this\?
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.*: Info: zero za.d\[w10, 4\]
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54
gas/testsuite/gas/aarch64/sme2p1-5-bad.s
Normal file
54
gas/testsuite/gas/aarch64/sme2p1-5-bad.s
Normal file
@ -0,0 +1,54 @@
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/* ZERO (single-vector). */
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zero za.s[w8, 0, vgx2]
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zero za.b[w14, 0, vgx2]
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zero za.d[w2, 7, vgx2]
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zero za.d[w11, 17, vgx2]
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zero za.d[w9, 4, vgx3]
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zero za.h[w10, 3]
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zero za.s[w18, 0, vgx4]
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zero za.b[w1, 0, vgx4]
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zero za.q[w8, 17, vgx2]
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zero za.h[w11, 7, vgx3]
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zero za.s[w9, vg]
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zero za.b[w10, 3]
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/* ZERO (double-vector). */
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zero za.s[w18, 0:1]
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zero za.s[w1, 0:1]
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zero za.b[w8, 4:5]
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zero za.b[w11, 1:5]
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zero za.h[w9, 2:13]
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zero za.h[w10, 16:7]
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zero za.s[w18, 0:3, vgx2]
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zero za.b[w1, 0:1, vgx4]
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zero za.h[w8, 6:7, vg]
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zero za.q[w9, 12:13, vgx3]
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zero za.s[w18, 0:1, vgx4]
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zero za.h[w1, 0:1, vgx3]
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zero za.b[w8, 16:17, vgx4]
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zero za.q[w9, 12:13]
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/* ZERO (quad-vector). */
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zero za.s[w18, 0:3,]
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zero za.s[w1, 0:3]
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zero za.b[w8, 8:11]
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zero za.b[w11, 18:1, vgx3]
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zero za.h[w9, 4]
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zero za.h[w10, 10:13]
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zero za.s[w18, 0:3, vgx2]
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zero za.s[w1, 0:3, vgx2]
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zero za.b[w8, 14:17, vgx2]
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zero za.b[w11, 4:7, vg]
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zero za.h[w9, 0:3]
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zero za.q[w10, vgx2]
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zero za.s[w18, 0:3, vgx4]
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zero za.s[w1, 0:3, vgx4]
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zero za.b[w8, 14:17, vgx4]
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zero za.b[w11, 4:7, vg]
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zero za.h[w9, 0:3, vgx3]
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zero za.q[w10, 4]
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54
gas/testsuite/gas/aarch64/sme2p1-5.d
Normal file
54
gas/testsuite/gas/aarch64/sme2p1-5.d
Normal file
@ -0,0 +1,54 @@
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#name: Test of SME2.1 ZERO instructions.
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#as: -march=armv9.4-a+sme2p1
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#objdump: -dr
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[^:]+: file format .*
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[^:]+:
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[^:]+:
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.*: c00c0000 zero za.d\[w8, 0, vgx2\]
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.*: c00c6000 zero za.d\[w11, 0, vgx2\]
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.*: c00c0007 zero za.d\[w8, 7, vgx2\]
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.*: c00c6007 zero za.d\[w11, 7, vgx2\]
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.*: c00c2004 zero za.d\[w9, 4, vgx2\]
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.*: c00c4003 zero za.d\[w10, 3, vgx2\]
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.*: c00e0000 zero za.d\[w8, 0, vgx4\]
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.*: c00e6000 zero za.d\[w11, 0, vgx4\]
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.*: c00e0007 zero za.d\[w8, 7, vgx4\]
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.*: c00e6007 zero za.d\[w11, 7, vgx4\]
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.*: c00e2004 zero za.d\[w9, 4, vgx4\]
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.*: c00e4003 zero za.d\[w10, 3, vgx4\]
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.*: c00c8000 zero za.d\[w8, 0:1\]
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.*: c00ce000 zero za.d\[w11, 0:1\]
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.*: c00c8007 zero za.d\[w8, 14:15\]
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.*: c00ce007 zero za.d\[w11, 14:15\]
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.*: c00ca001 zero za.d\[w9, 2:3\]
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.*: c00cc003 zero za.d\[w10, 6:7\]
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.*: c00d0000 zero za.d\[w8, 0:1, vgx2\]
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.*: c00d6000 zero za.d\[w11, 0:1, vgx2\]
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.*: c00d0003 zero za.d\[w8, 6:7, vgx2\]
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.*: c00d2001 zero za.d\[w9, 2:3, vgx2\]
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.*: c00d8000 zero za.d\[w8, 0:1, vgx4\]
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.*: c00de000 zero za.d\[w11, 0:1, vgx4\]
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.*: c00d8003 zero za.d\[w8, 6:7, vgx4\]
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.*: c00da001 zero za.d\[w9, 2:3, vgx4\]
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.*: c00e8000 zero za.d\[w8, 0:3\]
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.*: c00ee000 zero za.d\[w11, 0:3\]
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.*: c00e8002 zero za.d\[w8, 8:11\]
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.*: c00ee002 zero za.d\[w11, 8:11\]
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.*: c00ea001 zero za.d\[w9, 4:7\]
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.*: c00ec000 zero za.d\[w10, 0:3\]
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.*: c00f0000 zero za.d\[w8, 0:3, vgx2\]
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.*: c00f6000 zero za.d\[w11, 0:3, vgx2\]
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.*: c00f0001 zero za.d\[w8, 4:7, vgx2\]
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.*: c00f6001 zero za.d\[w11, 4:7, vgx2\]
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.*: c00f2000 zero za.d\[w9, 0:3, vgx2\]
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.*: c00f4001 zero za.d\[w10, 4:7, vgx2\]
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.*: c00f8000 zero za.d\[w8, 0:3, vgx4\]
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.*: c00fe000 zero za.d\[w11, 0:3, vgx4\]
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.*: c00f8001 zero za.d\[w8, 4:7, vgx4\]
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.*: c00fe001 zero za.d\[w11, 4:7, vgx4\]
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.*: c00fa000 zero za.d\[w9, 0:3, vgx4\]
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.*: c00fc001 zero za.d\[w10, 4:7, vgx4\]
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54
gas/testsuite/gas/aarch64/sme2p1-5.s
Normal file
54
gas/testsuite/gas/aarch64/sme2p1-5.s
Normal file
@ -0,0 +1,54 @@
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/* ZERO (single-vector). */
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zero za.d[w8, 0, vgx2]
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zero za.d[w11, 0, vgx2]
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zero za.d[w8, 7, vgx2]
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zero za.d[w11, 7, vgx2]
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zero za.d[w9, 4, vgx2]
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zero za.d[w10, 3, vgx2]
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zero za.d[w8, 0, vgx4]
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zero za.d[w11, 0, vgx4]
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zero za.d[w8, 7, vgx4]
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zero za.d[w11, 7, vgx4]
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zero za.d[w9, 4, vgx4]
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zero za.d[w10, 3, vgx4]
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/* ZERO (double-vector). */
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zero za.d[w8, 0:1]
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zero za.d[w11, 0:1]
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zero za.d[w8, 14:15]
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zero za.d[w11, 14:15]
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zero za.d[w9, 2:3]
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zero za.d[w10, 6:7]
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zero za.d[w8, 0:1, vgx2]
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zero za.d[w11, 0:1, vgx2]
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zero za.d[w8, 6:7, vgx2]
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zero za.d[w9, 2:3, vgx2]
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zero za.d[w8, 0:1, vgx4]
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zero za.d[w11, 0:1, vgx4]
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zero za.d[w8, 6:7, vgx4]
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zero za.d[w9, 2:3, vgx4]
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/* ZERO (quad-vector). */
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zero za.d[w8, 0:3]
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zero za.d[w11, 0:3]
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zero za.d[w8, 8:11]
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zero za.d[w11, 8:11]
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zero za.d[w9, 4:7]
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zero za.d[w10, 0:3]
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zero za.d[w8, 0:3, vgx2]
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zero za.d[w11, 0:3, vgx2]
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zero za.d[w8, 4:7, vgx2]
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zero za.d[w11, 4:7, vgx2]
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zero za.d[w9, 0:3, vgx2]
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zero za.d[w10, 4:7, vgx2]
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zero za.d[w8, 0:3, vgx4]
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zero za.d[w11, 0:3, vgx4]
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zero za.d[w8, 4:7, vgx4]
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zero za.d[w11, 4:7, vgx4]
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zero za.d[w9, 0:3, vgx4]
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zero za.d[w10, 4:7, vgx4]
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@ -1387,7 +1387,10 @@ extern const aarch64_opcode aarch64_opcode_table[];
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#define F_OPD_SIZE (1ULL << 34)
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/* RCPC3 instruction has the field of 'size'. */
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#define F_RCPC3_SIZE (1ULL << 35)
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/* Next bit is 36. */
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/* This instruction need VGx2 or VGx4 mandatorily in the operand passed to
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assembler. */
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#define F_VG_REQ (1ULL << 36)
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/* Next bit is 37. */
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/* Instruction constraints. */
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/* This instruction has a predication constraint on the instruction at PC+4. */
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@ -1450,6 +1453,12 @@ get_opcode_dependent_value (const aarch64_opcode *opcode)
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return (opcode->flags >> 24) & 0x7;
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}
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static inline bool
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get_opcode_dependent_vg_status (const aarch64_opcode *opcode)
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{
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return (opcode->flags >> 36) & 0x1;
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}
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static inline bool
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opcode_has_special_coder (const aarch64_opcode *opcode)
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{
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File diff suppressed because it is too large
Load Diff
@ -1629,13 +1629,14 @@ check_reglist (const aarch64_opnd_info *opnd,
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- an initial immediate offset that is a multiple of RANGE_SIZE
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in the range [0, MAX_VALUE * RANGE_SIZE]
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- a vector group size of GROUP_SIZE. */
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- a vector group size of GROUP_SIZE.
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- STATUS_VG for cases where VGx2 or VGx4 is mandatory. */
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static bool
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check_za_access (const aarch64_opnd_info *opnd,
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aarch64_operand_error *mismatch_detail, int idx,
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int min_wreg, int max_value, unsigned int range_size,
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int group_size)
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int group_size, bool status_vg)
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{
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if (!value_in_range_p (opnd->indexed_za.index.regno, min_wreg, min_wreg + 3))
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{
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@ -1687,8 +1688,8 @@ check_za_access (const aarch64_opnd_info *opnd,
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}
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/* The vector group specifier is optional in assembly code. */
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if (opnd->indexed_za.group_size != 0
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&& opnd->indexed_za.group_size != group_size)
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if (opnd->indexed_za.group_size != group_size
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&& (status_vg || opnd->indexed_za.group_size != 0 ))
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{
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set_invalid_vg_size (mismatch_detail, idx, group_size);
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return false;
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@ -1923,7 +1924,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
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size = aarch64_get_qualifier_esize (opnd->qualifier);
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max_value = 16 / size - 1;
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if (!check_za_access (opnd, mismatch_detail, idx,
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12, max_value, 1, 0))
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12, max_value, 1, 0, get_opcode_dependent_value (opcode)))
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return 0;
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break;
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@ -1993,93 +1994,108 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
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size = aarch64_get_qualifier_esize (opnd->qualifier);
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max_value = 16 / size - 1;
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if (!check_za_access (opnd, mismatch_detail, idx, 12, max_value, 1,
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get_opcode_dependent_value (opcode)))
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get_opcode_dependent_value (opcode),
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get_opcode_dependent_vg_status (opcode)))
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return 0;
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break;
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case AARCH64_OPND_SME_ZA_array_off4:
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if (!check_za_access (opnd, mismatch_detail, idx, 12, 15, 1,
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get_opcode_dependent_value (opcode)))
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get_opcode_dependent_value (opcode),
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get_opcode_dependent_vg_status (opcode)))
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return 0;
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break;
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case AARCH64_OPND_SME_ZA_array_off3_0:
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case AARCH64_OPND_SME_ZA_array_off3_5:
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if (!check_za_access (opnd, mismatch_detail, idx, 8, 7, 1,
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get_opcode_dependent_value (opcode)))
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get_opcode_dependent_value (opcode),
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get_opcode_dependent_vg_status (opcode)))
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return 0;
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break;
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case AARCH64_OPND_SME_ZA_array_off1x4:
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if (!check_za_access (opnd, mismatch_detail, idx, 8, 1, 4,
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get_opcode_dependent_value (opcode)))
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get_opcode_dependent_value (opcode),
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get_opcode_dependent_vg_status (opcode)))
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return 0;
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break;
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case AARCH64_OPND_SME_ZA_array_off2x2:
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if (!check_za_access (opnd, mismatch_detail, idx, 8, 3, 2,
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get_opcode_dependent_value (opcode)))
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get_opcode_dependent_value (opcode),
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get_opcode_dependent_vg_status (opcode)))
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return 0;
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break;
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case AARCH64_OPND_SME_ZA_array_off2x4:
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if (!check_za_access (opnd, mismatch_detail, idx, 8, 3, 4,
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get_opcode_dependent_value (opcode)))
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get_opcode_dependent_value (opcode),
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get_opcode_dependent_vg_status (opcode)))
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return 0;
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break;
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case AARCH64_OPND_SME_ZA_array_off3x2:
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if (!check_za_access (opnd, mismatch_detail, idx, 8, 7, 2,
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get_opcode_dependent_value (opcode)))
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get_opcode_dependent_value (opcode),
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get_opcode_dependent_vg_status (opcode)))
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return 0;
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break;
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case AARCH64_OPND_SME_ZA_array_vrsb_1:
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if (!check_za_access (opnd, mismatch_detail, idx, 12, 7, 2,
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get_opcode_dependent_value (opcode)))
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get_opcode_dependent_value (opcode),
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get_opcode_dependent_vg_status (opcode)))
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return 0;
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break;
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case AARCH64_OPND_SME_ZA_array_vrsh_1:
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if (!check_za_access (opnd, mismatch_detail, idx, 12, 3, 2,
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get_opcode_dependent_value (opcode)))
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get_opcode_dependent_value (opcode),
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get_opcode_dependent_vg_status (opcode)))
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return 0;
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break;
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case AARCH64_OPND_SME_ZA_array_vrss_1:
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if (!check_za_access (opnd, mismatch_detail, idx, 12, 1, 2,
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get_opcode_dependent_value (opcode)))
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get_opcode_dependent_value (opcode),
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get_opcode_dependent_vg_status (opcode)))
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return 0;
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break;
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case AARCH64_OPND_SME_ZA_array_vrsd_1:
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if (!check_za_access (opnd, mismatch_detail, idx, 12, 0, 2,
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get_opcode_dependent_value (opcode)))
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get_opcode_dependent_value (opcode),
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get_opcode_dependent_vg_status (opcode)))
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return 0;
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break;
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case AARCH64_OPND_SME_ZA_array_vrsb_2:
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if (!check_za_access (opnd, mismatch_detail, idx, 12, 3, 4,
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get_opcode_dependent_value (opcode)))
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get_opcode_dependent_value (opcode),
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get_opcode_dependent_vg_status (opcode)))
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return 0;
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break;
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case AARCH64_OPND_SME_ZA_array_vrsh_2:
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if (!check_za_access (opnd, mismatch_detail, idx, 12, 1, 4,
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get_opcode_dependent_value (opcode)))
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get_opcode_dependent_value (opcode),
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get_opcode_dependent_vg_status (opcode)))
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return 0;
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break;
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case AARCH64_OPND_SME_ZA_ARRAY4:
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if (!check_za_access (opnd, mismatch_detail, idx, 12, 15, 1,
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get_opcode_dependent_value (opcode)))
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get_opcode_dependent_value (opcode),
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get_opcode_dependent_vg_status (opcode)))
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return 0;
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break;
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case AARCH64_OPND_SME_ZA_array_vrss_2:
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case AARCH64_OPND_SME_ZA_array_vrsd_2:
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if (!check_za_access (opnd, mismatch_detail, idx, 12, 0, 4,
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get_opcode_dependent_value (opcode)))
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get_opcode_dependent_value (opcode),
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get_opcode_dependent_vg_status (opcode)))
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return 0;
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break;
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@ -2090,8 +2106,8 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
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max_value = 16 / num / size;
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if (max_value > 0)
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max_value -= 1;
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if (!check_za_access (opnd, mismatch_detail, idx,
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12, max_value, num, 0))
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if (!check_za_access (opnd, mismatch_detail, idx, 12, max_value, num,
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0, get_opcode_dependent_value (opcode)))
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return 0;
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break;
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@ -1606,6 +1606,10 @@
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{ \
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QLF3(S_B,P_Z,NIL), \
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}
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#define OP_SVE_D \
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{ \
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QLF1(S_D), \
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}
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#define OP_SVE_DD \
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{ \
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QLF2(S_D,S_D), \
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@ -6668,6 +6672,20 @@ const struct aarch64_opcode aarch64_opcode_table[] =
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SME2p1_INSN ("movaz", 0xc0c20200, 0xffff1e00, sme2_movaz, 0, OP2 (SVE_Zd, SME_ZA_ARRAY4), OP_SVE_DD, 0, 0),
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SME2p1_INSN ("movaz", 0xc0c30200, 0xffff1e00, sme2_movaz, 0, OP2 (SVE_Zd, SME_ZA_ARRAY4), OP_SVE_QQ, 0, 0),
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/* ZERO (single-vector). */
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SME2p1_INSN ("zero", 0xc00c0000, 0xffff9ff8, sme2_movaz, 0, OP1 (SME_ZA_array_off3_0), OP_SVE_D, F_OD (2) | F_VG_REQ, 0),
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SME2p1_INSN ("zero", 0xc00e0000, 0xffff9ff8, sme2_movaz, 0, OP1 (SME_ZA_array_off3_0), OP_SVE_D, F_OD (4) | F_VG_REQ, 0),
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/* ZERO (double-vector). */
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SME2p1_INSN ("zero", 0xc00c8000, 0xffff9ff8, sme2_movaz, 0, OP1 (SME_ZA_array_off3x2), OP_SVE_D, 0, 0),
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SME2p1_INSN ("zero", 0xc00d0000, 0xffff9ffc, sme2_movaz, 0, OP1 (SME_ZA_array_off2x2), OP_SVE_D, F_OD (2) | F_VG_REQ, 0),
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SME2p1_INSN ("zero", 0xc00d8000, 0xffff9ffc, sme2_movaz, 0, OP1 (SME_ZA_array_off2x2), OP_SVE_D, F_OD (4) | F_VG_REQ, 0),
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/* ZERO (quad-vector). */
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SME2p1_INSN ("zero", 0xc00e8000, 0xffff9ffc, sme2_movaz, 0, OP1 (SME_ZA_array_off2x4), OP_SVE_D, 0, 0),
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SME2p1_INSN ("zero", 0xc00f0000, 0xffff9ffe, sme2_movaz, 0, OP1 (SME_ZA_array_off1x4), OP_SVE_D, F_OD (2) | F_VG_REQ, 0),
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SME2p1_INSN ("zero", 0xc00f8000, 0xffff9ffe, sme2_movaz, 0, OP1 (SME_ZA_array_off1x4), OP_SVE_D, F_OD (4) | F_VG_REQ, 0),
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/* SVE2p1 Instructions. */
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SVE2p1_INSN("addqv",0x04052000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, 0),
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SVE2p1_INSN("andqv",0x041e2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, 0),
|
||||
|
||||
Loading…
Reference in New Issue
Block a user