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RISC-V: Assign DWARF numbers to vector registers
This commit assigns DWARF register numbers to vector registers (v0-v31: 96..127) to implement RISC-V DWARF Specification version 1.0-rc4 (now in the frozen state): https://github.com/riscv-non-isa/riscv-elf-psabi-doc/releases/tag/v1.0-rc4 binutils/ChangeLog: * dwarf.c (dwarf_regnames_riscv): Assign DWARF register numbers 96..127 to vector registers v0-v31. gas/ChangeLog: * config/tc-riscv.c (tc_riscv_regname_to_dw2regnum): Support vector registers. * testsuite/gas/riscv/dw-regnums.s: Add vector registers to the DWARF register number test. * testsuite/gas/riscv/dw-regnums.d: Likewise.
This commit is contained in:
Tsukasa OI
parent
61233edc75
commit
7b4f240762
@ -8540,16 +8540,24 @@ init_dwarf_regnames_s390 (void)
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static const char *const dwarf_regnames_riscv[] =
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{
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"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", /* 0 - 7 */
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"s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", /* 8 - 15 */
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"a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", /* 16 - 23 */
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"s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", /* 24 - 31 */
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"ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7", /* 32 - 39 */
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"fs0", "fs1", /* 40 - 41 */
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"fa0", "fa1", "fa2", "fa3", "fa4", "fa5", "fa6", "fa7", /* 42 - 49 */
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"fs2", "fs3", "fs4", "fs5", "fs6", "fs7", "fs8", "fs9", /* 50 - 57 */
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"fs10", "fs11", /* 58 - 59 */
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"ft8", "ft9", "ft10", "ft11" /* 60 - 63 */
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"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", /* 0 - 7 */
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"s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", /* 8 - 15 */
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"a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", /* 16 - 23 */
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"s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", /* 24 - 31 */
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"ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7", /* 32 - 39 */
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"fs0", "fs1", /* 40 - 41 */
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"fa0", "fa1", "fa2", "fa3", "fa4", "fa5", "fa6", "fa7", /* 42 - 49 */
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"fs2", "fs3", "fs4", "fs5", "fs6", "fs7", "fs8", "fs9", /* 50 - 57 */
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"fs10", "fs11", /* 58 - 59 */
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"ft8", "ft9", "ft10", "ft11", /* 60 - 63 */
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* 64 - 71 */
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* 72 - 79 */
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* 80 - 87 */
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* 88 - 95 */
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"v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", /* 96 - 103 */
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"v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", /* 104 - 111 */
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"v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", /* 112 - 119 */
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"v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", /* 120 - 127 */
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};
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/* A RISC-V replacement for REGNAME_INTERNAL_BY_TABLE_ONLY which handles
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@ -4406,6 +4406,9 @@ tc_riscv_regname_to_dw2regnum (char *regname)
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if ((reg = reg_lookup_internal (regname, RCLASS_FPR)) >= 0)
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return reg + 32;
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if ((reg = reg_lookup_internal (regname, RCLASS_VECR)) >= 0)
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return reg + 96;
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/* CSRs are numbered 4096 -> 8191. */
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if ((reg = reg_lookup_internal (regname, RCLASS_CSR)) >= 0)
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return reg + 4096;
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@ -1,4 +1,4 @@
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#as: -march=rv32if
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#as: -march=rv32iv
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#objdump: --dwarf=frames
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@ -145,4 +145,36 @@ Contents of the .* section:
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DW_CFA_offset_extended_sf: r61 \(ft9\) at cfa\+248
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DW_CFA_offset_extended_sf: r62 \(ft10\) at cfa\+252
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DW_CFA_offset_extended_sf: r63 \(ft11\) at cfa\+256
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DW_CFA_offset_extended_sf: r96 \(v0\) at cfa\+388
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DW_CFA_offset_extended_sf: r97 \(v1\) at cfa\+392
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DW_CFA_offset_extended_sf: r98 \(v2\) at cfa\+396
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DW_CFA_offset_extended_sf: r99 \(v3\) at cfa\+400
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DW_CFA_offset_extended_sf: r100 \(v4\) at cfa\+404
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DW_CFA_offset_extended_sf: r101 \(v5\) at cfa\+408
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DW_CFA_offset_extended_sf: r102 \(v6\) at cfa\+412
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DW_CFA_offset_extended_sf: r103 \(v7\) at cfa\+416
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DW_CFA_offset_extended_sf: r104 \(v8\) at cfa\+420
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DW_CFA_offset_extended_sf: r105 \(v9\) at cfa\+424
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DW_CFA_offset_extended_sf: r106 \(v10\) at cfa\+428
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DW_CFA_offset_extended_sf: r107 \(v11\) at cfa\+432
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DW_CFA_offset_extended_sf: r108 \(v12\) at cfa\+436
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DW_CFA_offset_extended_sf: r109 \(v13\) at cfa\+440
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DW_CFA_offset_extended_sf: r110 \(v14\) at cfa\+444
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DW_CFA_offset_extended_sf: r111 \(v15\) at cfa\+448
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DW_CFA_offset_extended_sf: r112 \(v16\) at cfa\+452
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DW_CFA_offset_extended_sf: r113 \(v17\) at cfa\+456
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DW_CFA_offset_extended_sf: r114 \(v18\) at cfa\+460
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DW_CFA_offset_extended_sf: r115 \(v19\) at cfa\+464
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DW_CFA_offset_extended_sf: r116 \(v20\) at cfa\+468
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DW_CFA_offset_extended_sf: r117 \(v21\) at cfa\+472
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DW_CFA_offset_extended_sf: r118 \(v22\) at cfa\+476
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DW_CFA_offset_extended_sf: r119 \(v23\) at cfa\+480
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DW_CFA_offset_extended_sf: r120 \(v24\) at cfa\+484
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DW_CFA_offset_extended_sf: r121 \(v25\) at cfa\+488
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DW_CFA_offset_extended_sf: r122 \(v26\) at cfa\+492
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DW_CFA_offset_extended_sf: r123 \(v27\) at cfa\+496
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DW_CFA_offset_extended_sf: r124 \(v28\) at cfa\+500
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DW_CFA_offset_extended_sf: r125 \(v29\) at cfa\+504
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DW_CFA_offset_extended_sf: r126 \(v30\) at cfa\+508
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DW_CFA_offset_extended_sf: r127 \(v31\) at cfa\+512
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#...
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@ -1,6 +1,8 @@
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# Check that CFI directives can accept all of the register names (including
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# aliases). The results for this test also ensures that the DWARF
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# register numbers for the GPRs/FPRs registers shouldn't change.
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# register numbers for the GPRs/FPRs/vector registers shouldn't change.
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# Note that, because vector register size is "variable" in principle,
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# vector registers are very unlikely to be used within .cfi_offset directive.
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.text
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.global _start
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@ -144,5 +146,39 @@ _start:
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.cfi_offset f30, 252
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.cfi_offset f31, 256
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# Vector registers (numeric only)
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.cfi_offset v0, 388
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.cfi_offset v1, 392
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.cfi_offset v2, 396
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.cfi_offset v3, 400
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.cfi_offset v4, 404
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.cfi_offset v5, 408
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.cfi_offset v6, 412
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.cfi_offset v7, 416
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.cfi_offset v8, 420
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.cfi_offset v9, 424
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.cfi_offset v10, 428
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.cfi_offset v11, 432
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.cfi_offset v12, 436
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.cfi_offset v13, 440
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.cfi_offset v14, 444
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.cfi_offset v15, 448
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.cfi_offset v16, 452
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.cfi_offset v17, 456
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.cfi_offset v18, 460
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.cfi_offset v19, 464
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.cfi_offset v20, 468
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.cfi_offset v21, 472
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.cfi_offset v22, 476
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.cfi_offset v23, 480
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.cfi_offset v24, 484
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.cfi_offset v25, 488
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.cfi_offset v26, 492
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.cfi_offset v27, 496
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.cfi_offset v28, 500
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.cfi_offset v29, 504
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.cfi_offset v30, 508
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.cfi_offset v31, 512
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nop
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.cfi_endproc
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