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x86: Rename VexOpcode to OpcodePrefix
Rename VexOpcode to OpcodePrefix so that OpcodePrefix can be used for regular encoding prefix. gas/ * config/tc-i386.c (build_vex_prefix): Replace vexopcode with opcodeprefix. (build_evex_prefix): Likewise. (is_any_vex_encoding): Don't check vexopcode. (output_insn): Handle opcodeprefix. opcodes/ * i386-gen.c (opcode_modifiers): Replace VexOpcode with OpcodePrefix. * i386-opc.h (VexOpcode): Renamed to ... (OpcodePrefix): This. (PREFIX_NONE): New. (PREFIX_0X66): Likewise. (PREFIX_0XF2): Likewise. (PREFIX_0XF3): Likewise. * i386-opc.tbl (Prefix_0X66): New. (Prefix_0XF2): Likewise. (Prefix_0XF3): Likewise. Replace VexOpcode= with OpcodePrefix=. Use Prefix_0X66 on xorpd. Use Prefix_0XF3 on cvtdq2pd. Use Prefix_0XF2 on cvtpd2dq. * i386-tbl.h: Regenerated.
This commit is contained in:
H.J. Lu
parent
6248f5e4fc
commit
7b47a31256
@ -1,3 +1,11 @@
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2020-10-13 H.J. Lu <hongjiu.lu@intel.com>
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* config/tc-i386.c (build_vex_prefix): Replace vexopcode with
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opcodeprefix.
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(build_evex_prefix): Likewise.
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(is_any_vex_encoding): Don't check vexopcode.
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(output_insn): Handle opcodeprefix.
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2020-10-09 H.J. Lu <hongjiu.lu@intel.com>
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PR gas/26703
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@ -3588,7 +3588,7 @@ build_vex_prefix (const insn_template *t)
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&& i.dir_encoding == dir_encoding_default
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&& i.operands == i.reg_operands
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&& operand_type_equal (&i.types[0], &i.types[i.operands - 1])
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&& i.tm.opcode_modifier.vexopcode == VEX0F
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&& i.tm.opcode_modifier.opcodeprefix == VEX0F
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&& (i.tm.opcode_modifier.load || i.tm.opcode_modifier.d)
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&& i.rex == REX_B)
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{
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@ -3633,7 +3633,7 @@ build_vex_prefix (const insn_template *t)
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union i386_op temp_op;
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i386_operand_type temp_type;
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gas_assert (i.tm.opcode_modifier.vexopcode == VEX0F);
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gas_assert (i.tm.opcode_modifier.opcodeprefix == VEX0F);
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gas_assert (!i.tm.opcode_modifier.sae);
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gas_assert (operand_type_equal (&i.types[i.operands - 2],
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&i.types[i.operands - 3]));
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@ -3704,7 +3704,7 @@ build_vex_prefix (const insn_template *t)
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/* Use 2-byte VEX prefix if possible. */
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if (w == 0
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&& i.vec_encoding != vex_encoding_vex3
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&& i.tm.opcode_modifier.vexopcode == VEX0F
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&& i.tm.opcode_modifier.opcodeprefix == VEX0F
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&& (i.rex & (REX_W | REX_X | REX_B)) == 0)
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{
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/* 2-byte VEX prefix. */
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@ -3727,7 +3727,7 @@ build_vex_prefix (const insn_template *t)
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i.vex.length = 3;
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switch (i.tm.opcode_modifier.vexopcode)
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switch (i.tm.opcode_modifier.opcodeprefix)
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{
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case VEX0F:
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m = 0x1;
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@ -3779,8 +3779,7 @@ is_evex_encoding (const insn_template *t)
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static INLINE bfd_boolean
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is_any_vex_encoding (const insn_template *t)
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{
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return t->opcode_modifier.vex || t->opcode_modifier.vexopcode
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|| is_evex_encoding (t);
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return t->opcode_modifier.vex || is_evex_encoding (t);
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}
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/* Build the EVEX prefix. */
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@ -3842,7 +3841,7 @@ build_evex_prefix (void)
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i.vex.bytes[0] = 0x62;
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/* mmmm bits. */
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switch (i.tm.opcode_modifier.vexopcode)
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switch (i.tm.opcode_modifier.opcodeprefix)
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{
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case VEX0F:
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m = 1;
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@ -4403,7 +4402,7 @@ load_insn_p (void)
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/* vldmxcsr. */
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if (i.tm.base_opcode == 0xae
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&& i.tm.opcode_modifier.vex
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&& i.tm.opcode_modifier.vexopcode == VEX0F
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&& i.tm.opcode_modifier.opcodeprefix == VEX0F
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&& i.tm.extension_opcode == 2)
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return 1;
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}
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@ -9374,33 +9373,49 @@ output_insn (void)
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don't need the explicit prefix. */
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if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
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{
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switch (i.tm.opcode_length)
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switch (i.tm.opcode_modifier.opcodeprefix)
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{
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case 3:
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if (i.tm.base_opcode & 0xff000000)
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case PREFIX_0X66:
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add_prefix (0x66);
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break;
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case PREFIX_0XF2:
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add_prefix (0xf2);
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break;
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case PREFIX_0XF3:
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add_prefix (0xf3);
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break;
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case PREFIX_NONE:
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switch (i.tm.opcode_length)
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{
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prefix = (i.tm.base_opcode >> 24) & 0xff;
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if (!i.tm.cpu_flags.bitfield.cpupadlock
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|| prefix != REPE_PREFIX_OPCODE
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|| (i.prefix[REP_PREFIX] != REPE_PREFIX_OPCODE))
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add_prefix (prefix);
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case 3:
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if (i.tm.base_opcode & 0xff000000)
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{
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prefix = (i.tm.base_opcode >> 24) & 0xff;
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if (!i.tm.cpu_flags.bitfield.cpupadlock
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|| prefix != REPE_PREFIX_OPCODE
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|| (i.prefix[REP_PREFIX] != REPE_PREFIX_OPCODE))
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add_prefix (prefix);
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}
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break;
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case 2:
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if ((i.tm.base_opcode & 0xff0000) != 0)
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{
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prefix = (i.tm.base_opcode >> 16) & 0xff;
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add_prefix (prefix);
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}
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break;
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case 1:
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break;
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case 0:
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/* Check for pseudo prefixes. */
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as_bad_where (insn_start_frag->fr_file,
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insn_start_frag->fr_line,
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_("pseudo prefix without instruction"));
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return;
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default:
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abort ();
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}
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break;
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case 2:
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if ((i.tm.base_opcode & 0xff0000) != 0)
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{
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prefix = (i.tm.base_opcode >> 16) & 0xff;
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add_prefix (prefix);
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}
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break;
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case 1:
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break;
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case 0:
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/* Check for pseudo prefixes. */
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as_bad_where (insn_start_frag->fr_file,
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insn_start_frag->fr_line,
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_("pseudo prefix without instruction"));
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return;
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default:
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abort ();
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}
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@ -1,3 +1,20 @@
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2020-10-13 H.J. Lu <hongjiu.lu@intel.com>
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* i386-gen.c (opcode_modifiers): Replace VexOpcode with
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OpcodePrefix.
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* i386-opc.h (VexOpcode): Renamed to ...
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(OpcodePrefix): This.
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(PREFIX_NONE): New.
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(PREFIX_0X66): Likewise.
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(PREFIX_0XF2): Likewise.
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(PREFIX_0XF3): Likewise.
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* i386-opc.tbl (Prefix_0X66): New.
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(Prefix_0XF2): Likewise.
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(Prefix_0XF3): Likewise.
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Replace VexOpcode= with OpcodePrefix=. Use Prefix_0X66 on xorpd.
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Use Prefix_0XF3 on cvtdq2pd. Use Prefix_0XF2 on cvtpd2dq.
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* i386-tbl.h: Regenerated.
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2020-10-05 Samanta Navarro <ferivoz@riseup.net>
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* cgen-asm.c: Fix spelling mistakes.
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@ -695,7 +695,7 @@ static bitfield opcode_modifiers[] =
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BITFIELD (Vex),
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BITFIELD (VexVVVV),
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BITFIELD (VexW),
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BITFIELD (VexOpcode),
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BITFIELD (OpcodePrefix),
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BITFIELD (VexSources),
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BITFIELD (SIB),
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BITFIELD (SSE2AVX),
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@ -561,6 +561,16 @@ enum
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#define VEXW1 2
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#define VEXWIG 3
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VexW,
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/* Regular opcode prefix:
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0: None
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1: Add 0x66 opcode prefix.
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2: Add 0xf2 opcode prefix.
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3: Add 0xf3 opcode prefix.
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*/
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#define PREFIX_NONE 0
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#define PREFIX_0X66 1
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#define PREFIX_0XF2 2
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#define PREFIX_0XF3 3
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/* VEX opcode prefix:
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0: VEX 0x0F opcode prefix.
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1: VEX 0x0F38 opcode prefix.
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@ -575,7 +585,7 @@ enum
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#define XOP08 3
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#define XOP09 4
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#define XOP0A 5
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VexOpcode,
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OpcodePrefix,
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/* number of VEX source operands:
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0: <= 2 source operands.
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1: 2 XOP source operands.
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@ -720,7 +730,7 @@ typedef struct i386_opcode_modifier
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unsigned int vex:2;
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unsigned int vexvvvv:2;
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unsigned int vexw:2;
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unsigned int vexopcode:3;
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unsigned int opcodeprefix:3;
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unsigned int vexsources:2;
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unsigned int sib:3;
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unsigned int sse2avx:1;
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4128
opcodes/i386-opc.tbl
4128
opcodes/i386-opc.tbl
File diff suppressed because it is too large
Load Diff
@ -15526,7 +15526,7 @@ const insn_template i386_optab[] =
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0, 1, 0, 0, 0, 1, 0 } },
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{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 1, 0, 0, 0, 0, 0 } } } },
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{ "xorpd", 0x660f57, None, 2, 2,
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{ "xorpd", 0xf57, None, 2, 2,
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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@ -15534,7 +15534,7 @@ const insn_template i386_optab[] =
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
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{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
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{ { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0,
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0, 1, 0, 0, 0, 1, 0 } },
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@ -15554,7 +15554,7 @@ const insn_template i386_optab[] =
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0, 1, 0, 0, 0, 1, 0 } },
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{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 1, 0, 0, 0, 0, 0 } } } },
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{ "cvtdq2pd", 0xf30fe6, None, 2, 2,
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{ "cvtdq2pd", 0xfe6, None, 2, 2,
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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@ -15562,7 +15562,7 @@ const insn_template i386_optab[] =
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
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{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 3, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
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{ { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 1,
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0, 1, 0, 0, 0, 1, 0 } },
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@ -15582,7 +15582,7 @@ const insn_template i386_optab[] =
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0, 1, 0, 0, 0, 1, 0 } },
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{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 1, 0, 0, 0, 0, 0 } } } },
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{ "cvtpd2dq", 0xf20fe6, None, 2, 2,
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{ "cvtpd2dq", 0xfe6, None, 2, 2,
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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@ -15590,7 +15590,7 @@ const insn_template i386_optab[] =
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
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{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
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{ { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0,
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0, 1, 0, 0, 0, 1, 0 } },
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