mirror/binutils-gdb
2
0
Fork 0
mirror of https://sourceware.org/git/binutils-gdb.git synced 2024-12-09 04:21:49 +08:00
Code Issues Packages Projects Releases Wiki Activity

[Cell/B.E.] Make parse_spufs_run more robust

Browse Source 
With recent changes to inferior handling, parse_spufs_run needs to be
more careful in assumptions it makes.  In particular, this patch:

- Bails out early if the current inferior has not yet been registered
  (e.g. during fork procession) to avoid assertion failures in register
  cache code.

- Sets inferior_ptid to the current ptid while calling target_read_memory
  to make sure the correct process is accessed if parse_spufs_run is
  called early when inferior_ptid has not yet been switched by the caller.

ChangeLog:

	* spu-multiarch.c (parse_spufs_run): Bail out if inferior is not
	registered yet.  Set inferior_ptid while calling target_read_memory.
This commit is contained in:
Ulrich Weigand 2015-08-27 19:27:40 +02:00
parent 1db33b5a02
commit 791bb1f4a6
2 changed files with 16 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
gdb/ChangeLog
View File

@ -1,3 +1,8 @@
2015-08-08 Ulrich Weigand <uweigand@de.ibm.com>
* spu-multiarch.c (parse_spufs_run): Bail out if inferior is not
registered yet. Set inferior_ptid while calling target_read_memory.
2015-08-08 Ulrich Weigand <uweigand@de.ibm.com>
* nat/linux-ptrace.h (GDB_ARCH_TRAP_BRKPT): Replace by ...

12
gdb/spu-multiarch.c
View File

@ -56,6 +56,7 @@ static int
parse_spufs_run (ptid_t ptid, int *fd, CORE_ADDR *addr)
{
enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ());
struct cleanup *old_chain;
struct gdbarch_tdep *tdep;
struct regcache *regcache;
gdb_byte buf[4];
@ -65,12 +66,21 @@ parse_spufs_run (ptid_t ptid, int *fd, CORE_ADDR *addr)
if (gdbarch_bfd_arch_info (target_gdbarch ())->arch != bfd_arch_powerpc)
return 0;
/* If we're called too early (e.g. after fork), we cannot
access the inferior yet. */
if (find_inferior_ptid (ptid) == NULL)
return 0;
/* Get PPU-side registers. */
regcache = get_thread_arch_regcache (ptid, target_gdbarch ());
tdep = gdbarch_tdep (target_gdbarch ());
/* Fetch instruction preceding current NIP. */
if (target_read_memory (regcache_read_pc (regcache) - 4, buf, 4) != 0)
old_chain = save_inferior_ptid ();
inferior_ptid = ptid;
regval = target_read_memory (regcache_read_pc (regcache) - 4, buf, 4);
do_cleanups (old_chain);
if (regval != 0)
return 0;
/* It should be a "sc" instruction. */
if (extract_unsigned_integer (buf, 4, byte_order) != INSTR_SC)