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Add missing break statemenets.

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This commit is contained in:
Anthony Green 2009-05-10 13:25:57 +00:00
parent bd518e6be4
commit 77176dfc67
2 changed files with 6 additions and 0 deletions
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4
sim/moxie/ChangeLog
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@ -1,3 +1,7 @@
2009-05-09 Anthony Green <green@moxielogic.com>
* interp.c (sim_resume): Add missing breaks in switch.
2008-10-03 Anthony Green <green@moxielogic.com>
* interp.c (sim_resume): Add support for ldo.b, sto.b, ldo.s, sto.s.

2
sim/moxie/interp.c
View File

@ -460,6 +460,7 @@ sim_resume (sd, step, siggnal)
TRACE("gsr");
cpu.asregs.regs[a] = cpu.asregs.sregs[v];
}
break;
case 0x03: /* ssr */
{
int a = (inst >> 8) & 0xf;
@ -467,6 +468,7 @@ sim_resume (sd, step, siggnal)
TRACE("ssr");
cpu.asregs.sregs[v] = cpu.asregs.regs[a];
}
break;
default:
TRACE("SIGILL2");
cpu.asregs.exception = SIGILL;