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2009-09-21 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c: Remove white spaces.
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@ -1,3 +1,7 @@
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2009-09-21 H.J. Lu <hongjiu.lu@intel.com>
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* config/tc-i386.c: Remove white spaces.
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2009-09-21 Ben Elliston <bje@au.ibm.com>
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2009-09-21 Ben Elliston <bje@au.ibm.com>
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Peter Bergner <bergner@vnet.ibm.com>
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Peter Bergner <bergner@vnet.ibm.com>
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@ -1062,7 +1062,7 @@ i386_align_code (fragS *fragP, int count)
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ones. Otherwise, we use a jump instruction and adjust
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ones. Otherwise, we use a jump instruction and adjust
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its offset. */
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its offset. */
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int limit;
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int limit;
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/* For 64bit, the limit is 3 bytes. */
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/* For 64bit, the limit is 3 bytes. */
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if (flag_code == CODE_64BIT
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if (flag_code == CODE_64BIT
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&& fragP->tc_frag_data.isa_flags.bitfield.cpulm)
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&& fragP->tc_frag_data.isa_flags.bitfield.cpulm)
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@ -1986,7 +1986,7 @@ check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
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if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
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if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
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|| new_flag.bitfield.cpul1om)
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|| new_flag.bitfield.cpul1om)
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return;
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return;
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as_bad (_("`%s' is not supported on `%s'"), name, arch);
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as_bad (_("`%s' is not supported on `%s'"), name, arch);
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#endif
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#endif
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}
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}
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@ -4884,8 +4884,8 @@ build_modrm_byte (void)
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dest = i.operands - 1;
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dest = i.operands - 1;
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nds = dest - 1;
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nds = dest - 1;
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/* This instruction must have 4 register operands
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/* This instruction must have 4 register operands
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or 3 register operands plus 1 memory operand.
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or 3 register operands plus 1 memory operand.
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It must have VexNDS and VexImmExt. */
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It must have VexNDS and VexImmExt. */
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gas_assert ((i.reg_operands == 4
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gas_assert ((i.reg_operands == 4
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|| (i.reg_operands == 3 && i.mem_operands == 1))
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|| (i.reg_operands == 3 && i.mem_operands == 1))
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@ -4911,7 +4911,7 @@ build_modrm_byte (void)
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{
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{
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source = 1;
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source = 1;
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reg = 0;
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reg = 0;
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}
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}
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/* FMA4 swaps REG and NDS. */
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/* FMA4 swaps REG and NDS. */
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if (i.tm.cpu_flags.bitfield.cpufma4)
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if (i.tm.cpu_flags.bitfield.cpufma4)
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{
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{
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@ -4919,17 +4919,17 @@ build_modrm_byte (void)
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tmp = reg;
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tmp = reg;
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reg = nds;
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reg = nds;
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nds = tmp;
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nds = tmp;
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}
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}
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gas_assert ((operand_type_equal (&i.tm.operand_types[reg], ®xmm)
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gas_assert ((operand_type_equal (&i.tm.operand_types[reg], ®xmm)
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|| operand_type_equal (&i.tm.operand_types[reg],
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|| operand_type_equal (&i.tm.operand_types[reg],
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®ymm))
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®ymm))
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&& (operand_type_equal (&i.tm.operand_types[nds], ®xmm)
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&& (operand_type_equal (&i.tm.operand_types[nds], ®xmm)
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|| operand_type_equal (&i.tm.operand_types[nds],
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|| operand_type_equal (&i.tm.operand_types[nds],
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®ymm)));
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®ymm)));
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exp->X_op = O_constant;
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exp->X_op = O_constant;
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exp->X_add_number
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exp->X_add_number
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= ((i.op[reg].regs->reg_num
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= ((i.op[reg].regs->reg_num
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+ ((i.op[reg].regs->reg_flags & RegRex) ? 8 : 0)) << 4);
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+ ((i.op[reg].regs->reg_flags & RegRex) ? 8 : 0)) << 4);
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i.vex.register_specifier = i.op[nds].regs;
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i.vex.register_specifier = i.op[nds].regs;
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}
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}
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else
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else
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@ -5319,7 +5319,7 @@ build_modrm_byte (void)
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gas_assert (i.reg_operands == 2);
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gas_assert (i.reg_operands == 2);
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if (!operand_type_equal (&i.tm.operand_types[vex_reg],
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if (!operand_type_equal (&i.tm.operand_types[vex_reg],
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& regxmm)
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®xmm)
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&& !operand_type_equal (&i.tm.operand_types[vex_reg],
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&& !operand_type_equal (&i.tm.operand_types[vex_reg],
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®ymm))
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®ymm))
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abort ();
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abort ();
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