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sim: m68hc11: migrate to standard uintXX_t types
This old port setup its own uintXX types, but since we require C11 now, we can assume the standard uintXX_t types exist and use them. Also migrate off the sim-specific unsignedXX types.
This commit is contained in:
Mike Frysinger
parent
eae126cb7e
commit
7606e1a390
@ -122,14 +122,14 @@ static const OPTION m68hc11_options[] =
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struct input_osc
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{
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signed64 on_time;
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signed64 off_time;
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signed64 repeat;
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int64_t on_time;
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int64_t off_time;
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int64_t repeat;
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struct hw_event *event;
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const char *name;
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uint8 mask;
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uint8 value;
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uint16 addr;
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uint8_t mask;
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uint8_t value;
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uint16_t addr;
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};
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#define NR_PORT_A_OSC (4)
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@ -209,7 +209,7 @@ static hw_ioctl_method m68hc11_ioctl;
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static hw_port_event_method m68hc11cpu_port_event;
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static void make_oscillator (struct m68hc11cpu *controller,
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const char *id, uint16 addr, uint8 mask);
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const char *id, uint16_t addr, uint8_t mask);
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static struct input_osc *find_oscillator (struct m68hc11cpu *controller,
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const char *id);
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static void reset_oscillators (struct hw *me);
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@ -412,7 +412,7 @@ deliver_m68hc11cpu_interrupt (struct hw *me, void *data)
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static void
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make_oscillator (struct m68hc11cpu *controller, const char *name,
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uint16 addr, uint8 mask)
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uint16_t addr, uint8_t mask)
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{
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struct input_osc *osc;
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@ -445,8 +445,8 @@ oscillator_handler (struct hw *me, void *data)
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struct input_osc *osc = (struct input_osc*) data;
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SIM_DESC sd;
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sim_cpu *cpu;
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signed64 dt;
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uint8 val;
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int64_t dt;
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uint8_t val;
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sd = hw_system (me);
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cpu = STATE_CPU (sd, 0);
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@ -593,10 +593,10 @@ static void
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m68hc11_info (struct hw *me)
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{
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SIM_DESC sd;
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uint16 base = 0;
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uint16_t base = 0;
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sim_cpu *cpu;
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struct m68hc11sio *controller;
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uint8 val;
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uint8_t val;
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sd = hw_system (me);
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cpu = STATE_CPU (sd, 0);
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@ -634,8 +634,8 @@ m68hc11_info (struct hw *me)
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val = cpu->ios[M6811_INIT];
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print_io_byte (sd, "INIT ", 0, val, base + M6811_INIT);
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sim_io_printf (sd, "Ram = 0x%04x IO = 0x%04x\n",
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(((uint16) (val & 0xF0)) << 8),
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(((uint16) (val & 0x0F)) << 12));
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(((uint16_t) (val & 0xF0)) << 8),
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(((uint16_t) (val & 0x0F)) << 12));
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cpu_info (sd, cpu);
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@ -662,7 +662,7 @@ m68hc11_ioctl (struct hw *me,
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stops. */
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int
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m68hc11cpu_set_oscillator (SIM_DESC sd, const char *port,
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double ton, double toff, signed64 repeat)
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double ton, double toff, int64_t repeat)
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{
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sim_cpu *cpu;
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struct input_osc *osc;
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@ -677,13 +677,13 @@ m68hc11cpu_set_oscillator (SIM_DESC sd, const char *port,
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/* Compute the ON time in cpu cycles. */
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f = (double) (cpu->cpu_frequency) * ton;
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osc->on_time = (signed64) (f / 4.0);
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osc->on_time = (int64_t) (f / 4.0);
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if (osc->on_time < 1)
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osc->on_time = 1;
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/* Compute the OFF time in cpu cycles. */
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f = (double) (cpu->cpu_frequency) * toff;
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osc->off_time = (signed64) (f / 4.0);
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osc->off_time = (int64_t) (f / 4.0);
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if (osc->off_time < 1)
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osc->off_time = 1;
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@ -777,7 +777,7 @@ m68hc11_option_handler (SIM_DESC sd, sim_cpu *cpu,
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case OPTION_OSC_INFO:
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for (i = 0; i < controller->last_oscillator; i++)
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{
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signed64 t;
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int64_t t;
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struct input_osc *osc;
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osc = &controller->oscillators[i];
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@ -878,10 +878,10 @@ m68hc11cpu_io_read_buffer (struct hw *me,
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void
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m68hc11cpu_set_port (struct hw *me, sim_cpu *cpu,
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unsigned addr, uint8 val)
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unsigned addr, uint8_t val)
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{
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uint8 mask;
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uint8 delta;
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uint8_t mask;
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uint8_t delta;
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int check_interrupts = 0;
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int i;
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@ -925,11 +925,11 @@ m68hc11cpu_set_port (struct hw *me, sim_cpu *cpu,
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/* Scan IC3, IC2 and IC1. Bit number is 3 - i. */
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for (i = 0; i < 3; i++)
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{
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uint8 mask = (1 << i);
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uint8_t mask = (1 << i);
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if (delta & mask)
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{
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uint8 edge;
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uint8_t edge;
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int captured;
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edge = cpu->ios[M6811_TCTL2];
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@ -983,7 +983,7 @@ m68hc11cpu_set_port (struct hw *me, sim_cpu *cpu,
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static void
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m68hc11cpu_io_write (struct hw *me, sim_cpu *cpu,
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unsigned_word addr, uint8 val)
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unsigned_word addr, uint8_t val)
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{
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switch (addr)
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{
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@ -1022,7 +1022,7 @@ m68hc11cpu_io_write (struct hw *me, sim_cpu *cpu,
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/* Change the RAM and I/O mapping. */
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case M6811_INIT:
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{
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uint8 old_bank = cpu->ios[M6811_INIT];
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uint8_t old_bank = cpu->ios[M6811_INIT];
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cpu->ios[M6811_INIT] = val;
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@ -1111,11 +1111,11 @@ m68hc11cpu_io_write_buffer (struct hw *me,
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byte = 0;
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while (nr_bytes)
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{
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uint8 val;
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uint8_t val;
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if (base >= controller->attach_size)
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break;
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val = *((uint8*) source);
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val = *((uint8_t*) source);
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m68hc11cpu_io_write (me, cpu, base, val);
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source = (char*) source + 1;
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base++;
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@ -112,11 +112,11 @@ struct m68hc11eepr
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located at the end of the EEPROM (eeprom size + 1). It is not mapped
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in memory but it's saved in the EEPROM file. */
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unsigned long eeprom_wcycle;
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uint16 eeprom_waddr;
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uint8 eeprom_wbyte;
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uint8 eeprom_wmode;
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uint16_t eeprom_waddr;
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uint8_t eeprom_wbyte;
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uint8_t eeprom_wmode;
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uint8* eeprom;
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uint8_t* eeprom;
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/* Minimum time in CPU cycles for programming the EEPROM. */
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unsigned long eeprom_min_cycles;
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@ -339,10 +339,10 @@ static void
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m68hc11eepr_info (struct hw *me)
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{
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SIM_DESC sd;
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uint16 base = 0;
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uint16_t base = 0;
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sim_cpu *cpu;
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struct m68hc11eepr *controller;
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uint8 val;
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uint8_t val;
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sd = hw_system (me);
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cpu = STATE_CPU (sd, 0);
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@ -418,13 +418,13 @@ m68hc11eepr_io_read_buffer (struct hw *me,
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{
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case M6811_PPROG:
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case M6811_CONFIG:
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*((uint8*) dest) = cpu->ios[base];
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*((uint8_t*) dest) = cpu->ios[base];
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break;
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default:
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hw_abort (me, "reading wrong register 0x%04x", base);
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}
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dest = (uint8*) (dest) + 1;
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dest = (uint8_t*) (dest) + 1;
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base++;
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nr_bytes--;
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cnt++;
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@ -456,7 +456,7 @@ m68hc11eepr_io_write_buffer (struct hw *me,
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SIM_DESC sd;
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struct m68hc11eepr *controller;
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sim_cpu *cpu;
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uint8 val;
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uint8_t val;
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HW_TRACE ((me, "write 0x%08lx %d", (long) base, (int) nr_bytes));
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@ -475,13 +475,13 @@ m68hc11eepr_io_write_buffer (struct hw *me,
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if (nr_bytes != 1)
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hw_abort (me, "Cannot write more than 1 byte to EEPROM device at a time");
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val = *((const uint8*) source);
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val = *((const uint8_t*) source);
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/* Write to the EEPROM control register. */
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if (space == io_map && base == M6811_PPROG)
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{
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uint8 wrong_bits;
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uint16 addr;
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uint8_t wrong_bits;
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uint16_t addr;
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addr = base + cpu_get_io_base (cpu);
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@ -184,7 +184,7 @@ m68hc11sio_port_event (struct hw *me,
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SIM_DESC sd;
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struct m68hc11sio *controller;
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sim_cpu *cpu;
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unsigned8 val;
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uint8_t val;
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controller = hw_data (me);
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sd = hw_system (me);
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@ -421,10 +421,10 @@ static void
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m68hc11sio_info (struct hw *me)
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{
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SIM_DESC sd;
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uint16 base = 0;
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uint16_t base = 0;
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sim_cpu *cpu;
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struct m68hc11sio *controller;
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uint8 val;
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uint8_t val;
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long clock_cycle;
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sd = hw_system (me);
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@ -457,7 +457,7 @@ m68hc11sio_info (struct hw *me)
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if (controller->tx_poll_event)
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{
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signed64 t;
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int64_t t;
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int n;
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t = hw_event_remain_time (me, controller->tx_poll_event);
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@ -469,7 +469,7 @@ m68hc11sio_info (struct hw *me)
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}
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if (controller->rx_poll_event)
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{
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signed64 t;
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int64_t t;
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t = hw_event_remain_time (me, controller->rx_poll_event);
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sim_io_printf (sd, " Receive finished in %s\n",
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@ -499,7 +499,7 @@ m68hc11sio_io_read_buffer (struct hw *me,
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SIM_DESC sd;
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struct m68hc11sio *controller;
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sim_cpu *cpu;
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unsigned8 val;
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uint8_t val;
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HW_TRACE ((me, "read 0x%08lx %d", (long) base, (int) nr_bytes));
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@ -530,7 +530,7 @@ m68hc11sio_io_read_buffer (struct hw *me,
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default:
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return 0;
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}
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*((unsigned8*) dest) = val;
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*((uint8_t*) dest) = val;
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return 1;
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}
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@ -544,7 +544,7 @@ m68hc11sio_io_write_buffer (struct hw *me,
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SIM_DESC sd;
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struct m68hc11sio *controller;
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sim_cpu *cpu;
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unsigned8 val;
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uint8_t val;
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HW_TRACE ((me, "write 0x%08lx %d", (long) base, (int) nr_bytes));
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@ -552,7 +552,7 @@ m68hc11sio_io_write_buffer (struct hw *me,
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cpu = STATE_CPU (sd, 0);
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controller = hw_data (me);
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val = *((const unsigned8*) source);
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val = *((const uint8_t*) source);
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switch (base)
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{
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case M6811_BAUD:
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@ -159,7 +159,7 @@ m68hc11spi_port_event (struct hw *me,
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SIM_DESC sd;
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struct m68hc11spi *controller;
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sim_cpu *cpu;
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unsigned8 val;
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uint8_t val;
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controller = hw_data (me);
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sd = hw_system (me);
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@ -193,7 +193,7 @@ m68hc11spi_port_event (struct hw *me,
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static void
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set_bit_port (struct hw *me, sim_cpu *cpu, int port, int mask, int value)
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{
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uint8 val;
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uint8_t val;
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if (value)
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val = cpu->ios[port] | mask;
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@ -330,10 +330,10 @@ static void
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m68hc11spi_info (struct hw *me)
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{
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SIM_DESC sd;
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uint16 base = 0;
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uint16_t base = 0;
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sim_cpu *cpu;
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struct m68hc11spi *controller;
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uint8 val;
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uint8_t val;
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sd = hw_system (me);
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cpu = STATE_CPU (sd, 0);
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@ -353,7 +353,7 @@ m68hc11spi_info (struct hw *me)
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if (controller->spi_event)
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{
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signed64 t;
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int64_t t;
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sim_io_printf (sd, " SPI has %d bits to send\n",
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controller->tx_bit + 1);
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@ -388,7 +388,7 @@ m68hc11spi_io_read_buffer (struct hw *me,
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SIM_DESC sd;
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struct m68hc11spi *controller;
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sim_cpu *cpu;
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unsigned8 val;
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uint8_t val;
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HW_TRACE ((me, "read 0x%08lx %d", (long) base, (int) nr_bytes));
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@ -419,7 +419,7 @@ m68hc11spi_io_read_buffer (struct hw *me,
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default:
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return 0;
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}
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*((unsigned8*) dest) = val;
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*((uint8_t*) dest) = val;
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return 1;
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}
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@ -433,7 +433,7 @@ m68hc11spi_io_write_buffer (struct hw *me,
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SIM_DESC sd;
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struct m68hc11spi *controller;
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sim_cpu *cpu;
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unsigned8 val;
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uint8_t val;
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HW_TRACE ((me, "write 0x%08lx %d", (long) base, (int) nr_bytes));
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@ -441,7 +441,7 @@ m68hc11spi_io_write_buffer (struct hw *me,
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cpu = STATE_CPU (sd, 0);
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controller = hw_data (me);
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val = *((const unsigned8*) source);
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val = *((const uint8_t*) source);
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switch (base)
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{
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case M6811_SPCR:
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@ -84,10 +84,10 @@ struct m68hc11tim
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unsigned long cop_delay;
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unsigned long rti_delay;
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unsigned long ovf_delay;
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signed64 clock_prescaler;
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signed64 tcnt_adjust;
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signed64 cop_prev_interrupt;
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signed64 rti_prev_interrupt;
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int64_t clock_prescaler;
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int64_t tcnt_adjust;
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int64_t cop_prev_interrupt;
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int64_t rti_prev_interrupt;
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/* Periodic timers. */
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struct hw_event *rti_timer_event;
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@ -158,8 +158,8 @@ m68hc11tim_port_event (struct hw *me,
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SIM_DESC sd;
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struct m68hc11tim *controller;
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sim_cpu *cpu;
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unsigned8 val;
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unsigned16 tcnt;
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uint8_t val;
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uint16_t tcnt;
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controller = hw_data (me);
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sd = hw_system (me);
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@ -207,7 +207,7 @@ m68hc11tim_port_event (struct hw *me,
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}
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case CAPTURE:
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tcnt = (uint16) ((cpu->cpu_absolute_cycle - controller->tcnt_adjust)
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tcnt = (uint16_t) ((cpu->cpu_absolute_cycle - controller->tcnt_adjust)
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/ controller->clock_prescaler);
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switch (level)
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{
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@ -252,8 +252,8 @@ m68hc11tim_timer_event (struct hw *me, void *data)
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unsigned flags;
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unsigned long tcnt_internal;
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unsigned long tcnt, tcnt_prev;
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signed64 tcnt_insn_end;
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signed64 tcnt_insn_start;
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int64_t tcnt_insn_end;
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int64_t tcnt_insn_start;
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int i;
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sim_events *events;
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@ -471,13 +471,13 @@ io_reg_desc pactl_desc[] = {
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};
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static double
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to_realtime (sim_cpu *cpu, signed64 t)
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to_realtime (sim_cpu *cpu, int64_t t)
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{
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return (double) (t) / (double) (cpu->cpu_frequency / 4);
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}
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const char*
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cycle_to_string (sim_cpu *cpu, signed64 t, int flags)
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cycle_to_string (sim_cpu *cpu, int64_t t, int flags)
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{
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char time_buf[32];
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char cycle_buf[32];
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@ -520,7 +520,7 @@ m68hc11tim_print_timer (struct hw *me, const char *name,
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}
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else
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{
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signed64 t;
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int64_t t;
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sim_cpu *cpu;
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cpu = STATE_CPU (sd, 0);
|
||||
@ -535,11 +535,11 @@ static void
|
||||
m68hc11tim_info (struct hw *me)
|
||||
{
|
||||
SIM_DESC sd;
|
||||
uint16 base = 0;
|
||||
uint16_t base = 0;
|
||||
sim_cpu *cpu;
|
||||
struct m68hc11tim *controller;
|
||||
uint8 val;
|
||||
uint16 val16;
|
||||
uint8_t val;
|
||||
uint16_t val16;
|
||||
|
||||
sd = hw_system (me);
|
||||
cpu = STATE_CPU (sd, 0);
|
||||
@ -643,7 +643,7 @@ m68hc11tim_io_read_buffer (struct hw *me,
|
||||
SIM_DESC sd;
|
||||
struct m68hc11tim *controller;
|
||||
sim_cpu *cpu;
|
||||
unsigned8 val;
|
||||
uint8_t val;
|
||||
unsigned cnt = 0;
|
||||
|
||||
HW_TRACE ((me, "read 0x%08lx %d", (long) base, (int) nr_bytes));
|
||||
@ -660,12 +660,12 @@ m68hc11tim_io_read_buffer (struct hw *me,
|
||||
Reading in a 16-bit register will be split in two accesses
|
||||
but this will be atomic within the simulator. */
|
||||
case M6811_TCTN_H:
|
||||
val = (uint8) ((cpu->cpu_absolute_cycle - controller->tcnt_adjust)
|
||||
val = (uint8_t) ((cpu->cpu_absolute_cycle - controller->tcnt_adjust)
|
||||
/ (controller->clock_prescaler * 256));
|
||||
break;
|
||||
|
||||
case M6811_TCTN_L:
|
||||
val = (uint8) ((cpu->cpu_absolute_cycle - controller->tcnt_adjust)
|
||||
val = (uint8_t) ((cpu->cpu_absolute_cycle - controller->tcnt_adjust)
|
||||
/ controller->clock_prescaler);
|
||||
break;
|
||||
|
||||
@ -673,7 +673,7 @@ m68hc11tim_io_read_buffer (struct hw *me,
|
||||
val = cpu->ios[base];
|
||||
break;
|
||||
}
|
||||
*((unsigned8*) dest) = val;
|
||||
*((uint8_t*) dest) = val;
|
||||
dest = (char*) dest + 1;
|
||||
base++;
|
||||
nr_bytes--;
|
||||
@ -692,8 +692,8 @@ m68hc11tim_io_write_buffer (struct hw *me,
|
||||
SIM_DESC sd;
|
||||
struct m68hc11tim *controller;
|
||||
sim_cpu *cpu;
|
||||
unsigned8 val, n;
|
||||
signed64 adj;
|
||||
uint8_t val, n;
|
||||
int64_t adj;
|
||||
int reset_compare = 0;
|
||||
int reset_overflow = 0;
|
||||
int cnt = 0;
|
||||
@ -706,7 +706,7 @@ m68hc11tim_io_write_buffer (struct hw *me,
|
||||
|
||||
while (nr_bytes)
|
||||
{
|
||||
val = *((const unsigned8*) source);
|
||||
val = *((const uint8_t*) source);
|
||||
switch (base)
|
||||
{
|
||||
/* Set the timer counter low part, trying to preserve the low part.
|
||||
@ -715,10 +715,10 @@ m68hc11tim_io_write_buffer (struct hw *me,
|
||||
in 64-bit to avoid overflow problems. */
|
||||
case M6811_TCTN_L:
|
||||
adj = ((cpu->cpu_absolute_cycle - controller->tcnt_adjust)
|
||||
/ (controller->clock_prescaler * (signed64) 256)) & 0x0FF;
|
||||
/ (controller->clock_prescaler * (int64_t) 256)) & 0x0FF;
|
||||
adj = cpu->cpu_absolute_cycle
|
||||
- (adj * controller->clock_prescaler * (signed64) 256)
|
||||
- ((signed64) adj * controller->clock_prescaler);
|
||||
- (adj * controller->clock_prescaler * (int64_t) 256)
|
||||
- ((int64_t) adj * controller->clock_prescaler);
|
||||
controller->tcnt_adjust = adj;
|
||||
reset_compare = 1;
|
||||
reset_overflow = 1;
|
||||
@ -728,7 +728,7 @@ m68hc11tim_io_write_buffer (struct hw *me,
|
||||
adj = ((cpu->cpu_absolute_cycle - controller->tcnt_adjust)
|
||||
/ controller->clock_prescaler) & 0x0ff;
|
||||
adj = cpu->cpu_absolute_cycle
|
||||
- ((signed64) val * controller->clock_prescaler * (signed64) 256)
|
||||
- ((int64_t) val * controller->clock_prescaler * (int64_t) 256)
|
||||
- (adj * controller->clock_prescaler);
|
||||
controller->tcnt_adjust = adj;
|
||||
reset_compare = 1;
|
||||
|
||||
@ -106,7 +106,7 @@ struct nvram
|
||||
{
|
||||
address_word base_address; /* Base address of ram. */
|
||||
unsigned size; /* Size of ram. */
|
||||
unsigned8 *data; /* Pointer to ram memory. */
|
||||
uint8_t *data; /* Pointer to ram memory. */
|
||||
const char *file_name; /* Path of ram file. */
|
||||
int fd; /* File description of opened ram file. */
|
||||
enum nvram_mode mode; /* How load/save ram file. */
|
||||
|
||||
@ -107,7 +107,7 @@ emul_write (sim_cpu *cpu)
|
||||
cpu->cpu_running = 0;
|
||||
while (size)
|
||||
{
|
||||
uint8 val = memory_read8 (cpu, addr);
|
||||
uint8_t val = memory_read8 (cpu, addr);
|
||||
|
||||
if (write (0, &val, 1) != 1)
|
||||
printf ("write failed: %s\n", strerror (errno));
|
||||
|
||||
@ -134,7 +134,7 @@ struct m6811_opcode_pattern m6811_opcode_patterns[] = {
|
||||
{ "rts11", "addr = cpu_m68hc11_pop_uint16 (cpu); cpu_set_pc (cpu, addr); cpu_return (cpu)" },
|
||||
{ "rts12", "addr = cpu_m68hc12_pop_uint16 (cpu); cpu_set_pc (cpu, addr); cpu_return (cpu)" },
|
||||
|
||||
{ "mul16", "dst16 = ((uint16) src8 & 0x0FF) * ((uint16) dst8 & 0x0FF)",
|
||||
{ "mul16", "dst16 = ((uint16_t) src8 & 0x0FF) * ((uint16_t) dst8 & 0x0FF)",
|
||||
"cpu_set_ccr_C (cpu, src8 & 0x80)" },
|
||||
{ "neg8", "dst8 = - src8",
|
||||
"cpu_set_ccr_C (cpu, src8 == 0); cpu_ccr_update_tst8 (cpu, dst8)" },
|
||||
@ -227,7 +227,7 @@ dst16 = dst16 + src16", 0 },
|
||||
{ "txys16", "dst16 = src16 - 1;"},
|
||||
|
||||
/* Add b to X or Y with an unsigned extension 8->16. Flags not changed. */
|
||||
{ "abxy16","dst16 = dst16 + (uint16) src8"},
|
||||
{ "abxy16","dst16 = dst16 + (uint16_t) src8"},
|
||||
|
||||
/* After 'daa', the Z flag is undefined. Mark it as changed. */
|
||||
{ "daa8", "cpu_special (cpu, M6811_DAA)" },
|
||||
@ -256,8 +256,8 @@ cpu_set_ccr_V (cpu, 1);\n\
|
||||
cpu_set_ccr_C (cpu, dst16 == 0);\n\
|
||||
}\nelse\n{\n\
|
||||
unsigned long l = (unsigned long) (dst16) << 16;\n\
|
||||
cpu_set_d (cpu, (uint16) (l % (unsigned long) (src16)));\n\
|
||||
dst16 = (uint16) (l / (unsigned long) (src16));\n\
|
||||
cpu_set_d (cpu, (uint16_t) (l % (unsigned long) (src16)));\n\
|
||||
dst16 = (uint16_t) (l / (unsigned long) (src16));\n\
|
||||
cpu_set_ccr_V (cpu, 0);\n\
|
||||
cpu_set_ccr_C (cpu, 0);\n\
|
||||
cpu_set_ccr_Z (cpu, dst16 == 0);\n\
|
||||
@ -289,8 +289,8 @@ cpu_set_ccr_Z (cpu, dst16 == 0);\n\
|
||||
{ "call_ind", "cpu_special (cpu, M6812_CALL_INDIRECT)" },
|
||||
{ "dbcc8", "cpu_dbcc (cpu)" },
|
||||
{ "ediv", "cpu_special (cpu, M6812_EDIV)" },
|
||||
{ "emul", "{ uint32 src1 = (uint32) cpu_get_d (cpu);\
|
||||
uint32 src2 = (uint32) cpu_get_y (cpu);\
|
||||
{ "emul", "{ uint32_t src1 = (uint32_t) cpu_get_d (cpu);\
|
||||
uint32_t src2 = (uint32_t) cpu_get_y (cpu);\
|
||||
src1 *= src2;\
|
||||
cpu_set_d (cpu, src1);\
|
||||
cpu_set_y (cpu, src1 >> 16);\
|
||||
@ -1284,9 +1284,9 @@ print (FILE *fp, int col, const char *msg, ...)
|
||||
- End of input operands.
|
||||
|
||||
Example:
|
||||
(x),a->a addr = x + (uint16) (fetch8 (cpu));
|
||||
(x),a->a addr = x + (uint16_t) (fetch8 (cpu));
|
||||
src8 = a
|
||||
*,#,r addr = (uint16) (fetch8 (cpu)) <- Temporary 'addr'
|
||||
*,#,r addr = (uint16_t) (fetch8 (cpu)) <- Temporary 'addr'
|
||||
src8 = read_mem8 (cpu, addr)
|
||||
dst8 = fetch8 (cpu)
|
||||
addr = fetch_relbranch (cpu) <- Final 'addr'
|
||||
@ -1357,7 +1357,7 @@ gen_fetch_operands (FILE *fp, int col,
|
||||
|
||||
addr_set = 1;
|
||||
current_insn_size += 1;
|
||||
print (fp, col, "addr = (uint16) cpu_fetch8 (cpu);");
|
||||
print (fp, col, "addr = (uint16_t) cpu_fetch8 (cpu);");
|
||||
print (fp, col, "%s%s = memory_read%s (cpu, addr);",
|
||||
vars[cur_var], operand_size, operand_size);
|
||||
break;
|
||||
@ -1370,13 +1370,13 @@ gen_fetch_operands (FILE *fp, int col,
|
||||
if (strncmp (operands, "(x)", 3) == 0)
|
||||
{
|
||||
current_insn_size += 1;
|
||||
print (fp, col, "addr = cpu_get_x (cpu) + (uint16) cpu_fetch8 (cpu);");
|
||||
print (fp, col, "addr = cpu_get_x (cpu) + (uint16_t) cpu_fetch8 (cpu);");
|
||||
operands += 3;
|
||||
}
|
||||
else if (strncmp (operands, "(y)", 3) == 0)
|
||||
{
|
||||
current_insn_size += 1;
|
||||
print (fp, col, "addr = cpu_get_y (cpu) + (uint16) cpu_fetch8 (cpu);");
|
||||
print (fp, col, "addr = cpu_get_y (cpu) + (uint16_t) cpu_fetch8 (cpu);");
|
||||
operands += 3;
|
||||
}
|
||||
else if (strncmp (operands, "()", 2) == 0)
|
||||
@ -1408,7 +1408,7 @@ gen_fetch_operands (FILE *fp, int col,
|
||||
{
|
||||
addr_set = 1;
|
||||
current_insn_size += 1;
|
||||
print (fp, col, "addr = cpu_get_x (cpu) + (uint16) cpu_fetch8 (cpu);");
|
||||
print (fp, col, "addr = cpu_get_x (cpu) + (uint16_t) cpu_fetch8 (cpu);");
|
||||
print (fp, col, "%s%s = memory_read%s (cpu, addr);",
|
||||
vars[cur_var], operand_size, operand_size);
|
||||
operands += 2;
|
||||
@ -1417,7 +1417,7 @@ gen_fetch_operands (FILE *fp, int col,
|
||||
{
|
||||
addr_set = 1;
|
||||
current_insn_size += 1;
|
||||
print (fp, col, "addr = cpu_get_y (cpu) + (uint16) cpu_fetch8 (cpu);");
|
||||
print (fp, col, "addr = cpu_get_y (cpu) + (uint16_t) cpu_fetch8 (cpu);");
|
||||
print (fp, col, "%s%s = memory_read%s (cpu, addr);",
|
||||
vars[cur_var], operand_size, operand_size);
|
||||
operands += 2;
|
||||
@ -1668,7 +1668,7 @@ gen_save_result (FILE *fp, int col,
|
||||
if (addr_set == 0)
|
||||
{
|
||||
current_insn_size += 1;
|
||||
print (fp, col, "addr = (uint16) cpu_fetch8 (cpu);");
|
||||
print (fp, col, "addr = (uint16_t) cpu_fetch8 (cpu);");
|
||||
}
|
||||
result_size = operand_size;
|
||||
print (fp, col, "memory_write%s (cpu, addr, dst%s);",
|
||||
@ -1995,11 +1995,11 @@ gen_function_entry (FILE *fp, const char *name, int locals)
|
||||
|
||||
/* Interpretor local variables. */
|
||||
print (fp, indent_level, "unsigned char op;");
|
||||
print (fp, indent_level, "uint16 addr, src16, dst16;");
|
||||
print (fp, indent_level, "uint16_t addr, src16, dst16;");
|
||||
if (locals & USE_SRC8)
|
||||
print (fp, indent_level, "uint8 src8;\n");
|
||||
print (fp, indent_level, "uint8_t src8;\n");
|
||||
if (locals & USE_DST8)
|
||||
print (fp, indent_level, "uint8 dst8;\n");
|
||||
print (fp, indent_level, "uint8_t dst8;\n");
|
||||
}
|
||||
|
||||
void
|
||||
|
||||
@ -533,7 +533,7 @@ sim_create_inferior (SIM_DESC sd, struct bfd *abfd,
|
||||
static int
|
||||
m68hc11_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
|
||||
{
|
||||
uint16 val;
|
||||
uint16_t val;
|
||||
int size = 2;
|
||||
|
||||
switch (rn)
|
||||
@ -597,7 +597,7 @@ m68hc11_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
|
||||
static int
|
||||
m68hc11_reg_store (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
|
||||
{
|
||||
uint16 val;
|
||||
uint16_t val;
|
||||
|
||||
val = *memory++;
|
||||
if (length == 2)
|
||||
|
||||
@ -95,7 +95,7 @@ struct interrupt_def idefs[] = {
|
||||
#endif
|
||||
};
|
||||
|
||||
#define CYCLES_MAX ((((signed64) 1) << 62) - 1)
|
||||
#define CYCLES_MAX ((((int64_t) 1) << 62) - 1)
|
||||
|
||||
enum
|
||||
{
|
||||
@ -174,7 +174,7 @@ interrupts_reset (struct interrupts *interrupts)
|
||||
if (interrupts->cpu->cpu_mode == M6811_SMOD)
|
||||
{
|
||||
bfd_vma addr = interrupts->vectors_addr;
|
||||
uint16 vector = 0x0100 - 3 * (M6811_INT_NUMBER - 1);
|
||||
uint16_t vector = 0x0100 - 3 * (M6811_INT_NUMBER - 1);
|
||||
for (i = 0; i < M6811_INT_NUMBER; i++)
|
||||
{
|
||||
memory_write16 (interrupts->cpu, addr, vector);
|
||||
@ -285,7 +285,7 @@ void
|
||||
interrupts_update_pending (struct interrupts *interrupts)
|
||||
{
|
||||
int i;
|
||||
uint8 *ioregs;
|
||||
uint8_t *ioregs;
|
||||
unsigned long clear_mask;
|
||||
unsigned long set_mask;
|
||||
|
||||
@ -296,7 +296,7 @@ interrupts_update_pending (struct interrupts *interrupts)
|
||||
for (i = 0; i < ARRAY_SIZE (idefs); i++)
|
||||
{
|
||||
struct interrupt_def *idef = &idefs[i];
|
||||
uint8 data;
|
||||
uint8_t data;
|
||||
|
||||
/* Look if the interrupt is enabled. */
|
||||
if (idef->enable_paddr)
|
||||
@ -332,7 +332,7 @@ interrupts_update_pending (struct interrupts *interrupts)
|
||||
Also implements the breakpoint-on-interrupt. */
|
||||
if (set_mask)
|
||||
{
|
||||
signed64 cycle = cpu_current_cycle (interrupts->cpu);
|
||||
int64_t cycle = cpu_current_cycle (interrupts->cpu);
|
||||
int must_stop = 0;
|
||||
|
||||
for (i = 0; i < M6811_INT_NUMBER; i++)
|
||||
@ -427,7 +427,7 @@ int
|
||||
interrupts_process (struct interrupts *interrupts)
|
||||
{
|
||||
int id;
|
||||
uint8 ccr;
|
||||
uint8_t ccr;
|
||||
|
||||
/* See if interrupts are enabled/disabled and keep track of the
|
||||
number of cycles the interrupts are masked. Such information is
|
||||
@ -441,7 +441,7 @@ interrupts_process (struct interrupts *interrupts)
|
||||
else if (interrupts->start_mask_cycle >= 0
|
||||
&& (ccr & M6811_I_BIT) == 0)
|
||||
{
|
||||
signed64 t = cpu_current_cycle (interrupts->cpu);
|
||||
int64_t t = cpu_current_cycle (interrupts->cpu);
|
||||
|
||||
t -= interrupts->start_mask_cycle;
|
||||
if (t < interrupts->min_mask_cycles)
|
||||
@ -460,7 +460,7 @@ interrupts_process (struct interrupts *interrupts)
|
||||
else if (interrupts->xirq_start_mask_cycle >= 0
|
||||
&& (ccr & M6811_X_BIT) == 0)
|
||||
{
|
||||
signed64 t = cpu_current_cycle (interrupts->cpu);
|
||||
int64_t t = cpu_current_cycle (interrupts->cpu);
|
||||
|
||||
t -= interrupts->xirq_start_mask_cycle;
|
||||
if (t < interrupts->xirq_min_mask_cycles)
|
||||
@ -474,7 +474,7 @@ interrupts_process (struct interrupts *interrupts)
|
||||
id = interrupts_get_current (interrupts);
|
||||
if (id >= 0)
|
||||
{
|
||||
uint16 addr;
|
||||
uint16_t addr;
|
||||
struct interrupt_history *h;
|
||||
|
||||
/* Implement the breakpoint-on-interrupt. */
|
||||
@ -533,7 +533,7 @@ interrupts_raise (struct interrupts *interrupts, enum M6811_INT number)
|
||||
void
|
||||
interrupts_info (SIM_DESC sd, struct interrupts *interrupts)
|
||||
{
|
||||
signed64 t, prev_interrupt;
|
||||
int64_t t, prev_interrupt;
|
||||
int i;
|
||||
|
||||
sim_io_printf (sd, "Interrupts Info:\n");
|
||||
@ -621,7 +621,7 @@ interrupts_info (SIM_DESC sd, struct interrupts *interrupts)
|
||||
{
|
||||
int which;
|
||||
struct interrupt_history *h;
|
||||
signed64 dt;
|
||||
int64_t dt;
|
||||
|
||||
which = interrupts->history_index - i - 1;
|
||||
if (which < 0)
|
||||
|
||||
@ -88,10 +88,10 @@ struct interrupt_history
|
||||
enum M6811_INT type;
|
||||
|
||||
/* CPU cycle when interrupt handler is called. */
|
||||
signed64 taken_cycle;
|
||||
int64_t taken_cycle;
|
||||
|
||||
/* CPU cycle when the interrupt is first raised by the device. */
|
||||
signed64 raised_cycle;
|
||||
int64_t raised_cycle;
|
||||
};
|
||||
|
||||
#define SIM_STOP_WHEN_RAISED 1
|
||||
@ -101,7 +101,7 @@ struct interrupt_history
|
||||
struct interrupt
|
||||
{
|
||||
/* CPU cycle when the interrupt is raised by the device. */
|
||||
signed64 cpu_cycle;
|
||||
int64_t cpu_cycle;
|
||||
|
||||
/* Number of times the interrupt was raised. */
|
||||
unsigned long raised_count;
|
||||
@ -129,7 +129,7 @@ struct interrupts {
|
||||
|
||||
/* Address of vector table. This is set depending on the
|
||||
68hc11 init mode. */
|
||||
uint16 vectors_addr;
|
||||
uint16_t vectors_addr;
|
||||
|
||||
/* Priority order of interrupts. This is controlled by setting the HPRIO
|
||||
IO register. */
|
||||
@ -139,16 +139,16 @@ struct interrupts {
|
||||
/* Simulator statistics to report useful debug information to users. */
|
||||
|
||||
/* - Max/Min number of CPU cycles executed with interrupts masked. */
|
||||
signed64 start_mask_cycle;
|
||||
signed64 min_mask_cycles;
|
||||
signed64 max_mask_cycles;
|
||||
signed64 last_mask_cycles;
|
||||
int64_t start_mask_cycle;
|
||||
int64_t min_mask_cycles;
|
||||
int64_t max_mask_cycles;
|
||||
int64_t last_mask_cycles;
|
||||
|
||||
/* - Same for XIRQ. */
|
||||
signed64 xirq_start_mask_cycle;
|
||||
signed64 xirq_min_mask_cycles;
|
||||
signed64 xirq_max_mask_cycles;
|
||||
signed64 xirq_last_mask_cycles;
|
||||
int64_t xirq_start_mask_cycle;
|
||||
int64_t xirq_min_mask_cycles;
|
||||
int64_t xirq_max_mask_cycles;
|
||||
int64_t xirq_last_mask_cycles;
|
||||
|
||||
/* - Total number of interrupts raised. */
|
||||
unsigned long nb_interrupts_raised;
|
||||
|
||||
@ -101,7 +101,7 @@ cpu_option_handler (SIM_DESC sd, sim_cpu *cpu,
|
||||
|
||||
|
||||
void
|
||||
cpu_call (sim_cpu *cpu, uint16 addr)
|
||||
cpu_call (sim_cpu *cpu, uint16_t addr)
|
||||
{
|
||||
|
||||
cpu_set_pc (cpu, addr);
|
||||
@ -114,13 +114,13 @@ cpu_return (sim_cpu *cpu)
|
||||
|
||||
/* Set the stack pointer and re-compute the current frame. */
|
||||
void
|
||||
cpu_set_sp (sim_cpu *cpu, uint16 val)
|
||||
cpu_set_sp (sim_cpu *cpu, uint16_t val)
|
||||
{
|
||||
cpu->cpu_regs.sp = val;
|
||||
}
|
||||
|
||||
static uint16
|
||||
cpu_get_reg (sim_cpu *cpu, uint8 reg)
|
||||
static uint16_t
|
||||
cpu_get_reg (sim_cpu *cpu, uint8_t reg)
|
||||
{
|
||||
switch (reg)
|
||||
{
|
||||
@ -141,8 +141,8 @@ cpu_get_reg (sim_cpu *cpu, uint8 reg)
|
||||
}
|
||||
}
|
||||
|
||||
static uint16
|
||||
cpu_get_src_reg (sim_cpu *cpu, uint8 reg)
|
||||
static uint16_t
|
||||
cpu_get_src_reg (sim_cpu *cpu, uint8_t reg)
|
||||
{
|
||||
switch (reg)
|
||||
{
|
||||
@ -176,7 +176,7 @@ cpu_get_src_reg (sim_cpu *cpu, uint8 reg)
|
||||
}
|
||||
|
||||
static void
|
||||
cpu_set_dst_reg (sim_cpu *cpu, uint8 reg, uint16 val)
|
||||
cpu_set_dst_reg (sim_cpu *cpu, uint8_t reg, uint16_t val)
|
||||
{
|
||||
switch (reg)
|
||||
{
|
||||
@ -218,7 +218,7 @@ cpu_set_dst_reg (sim_cpu *cpu, uint8 reg, uint16 val)
|
||||
}
|
||||
|
||||
static void
|
||||
cpu_set_reg (sim_cpu *cpu, uint8 reg, uint16 val)
|
||||
cpu_set_reg (sim_cpu *cpu, uint8_t reg, uint16_t val)
|
||||
{
|
||||
switch (reg)
|
||||
{
|
||||
@ -245,13 +245,13 @@ cpu_set_reg (sim_cpu *cpu, uint8 reg, uint16 val)
|
||||
|
||||
/* Returns the address of a 68HC12 indexed operand.
|
||||
Pre and post modifications are handled on the source register. */
|
||||
uint16
|
||||
uint16_t
|
||||
cpu_get_indexed_operand_addr (sim_cpu *cpu, int restricted)
|
||||
{
|
||||
uint8 reg;
|
||||
uint16 sval;
|
||||
uint16 addr;
|
||||
uint8 code;
|
||||
uint8_t reg;
|
||||
uint16_t sval;
|
||||
uint16_t addr;
|
||||
uint8_t code;
|
||||
|
||||
code = cpu_fetch8 (cpu);
|
||||
|
||||
@ -350,29 +350,29 @@ cpu_get_indexed_operand_addr (sim_cpu *cpu, int restricted)
|
||||
return addr;
|
||||
}
|
||||
|
||||
static uint8
|
||||
static uint8_t
|
||||
cpu_get_indexed_operand8 (sim_cpu *cpu, int restricted)
|
||||
{
|
||||
uint16 addr;
|
||||
uint16_t addr;
|
||||
|
||||
addr = cpu_get_indexed_operand_addr (cpu, restricted);
|
||||
return memory_read8 (cpu, addr);
|
||||
}
|
||||
|
||||
static uint16
|
||||
static uint16_t
|
||||
cpu_get_indexed_operand16 (sim_cpu *cpu, int restricted)
|
||||
{
|
||||
uint16 addr;
|
||||
uint16_t addr;
|
||||
|
||||
addr = cpu_get_indexed_operand_addr (cpu, restricted);
|
||||
return memory_read16 (cpu, addr);
|
||||
}
|
||||
|
||||
void
|
||||
cpu_move8 (sim_cpu *cpu, uint8 code)
|
||||
cpu_move8 (sim_cpu *cpu, uint8_t code)
|
||||
{
|
||||
uint8 src;
|
||||
uint16 addr;
|
||||
uint8_t src;
|
||||
uint16_t addr;
|
||||
|
||||
switch (code)
|
||||
{
|
||||
@ -416,10 +416,10 @@ cpu_move8 (sim_cpu *cpu, uint8 code)
|
||||
}
|
||||
|
||||
void
|
||||
cpu_move16 (sim_cpu *cpu, uint8 code)
|
||||
cpu_move16 (sim_cpu *cpu, uint8_t code)
|
||||
{
|
||||
uint16 src;
|
||||
uint16 addr;
|
||||
uint16_t src;
|
||||
uint16_t addr;
|
||||
|
||||
switch (code)
|
||||
{
|
||||
@ -530,7 +530,7 @@ cpu_reset (sim_cpu *cpu)
|
||||
int
|
||||
cpu_restart (sim_cpu *cpu)
|
||||
{
|
||||
uint16 addr;
|
||||
uint16_t addr;
|
||||
|
||||
/* Get CPU starting address depending on the CPU mode. */
|
||||
if (cpu->cpu_use_elf_start == 0)
|
||||
@ -591,7 +591,7 @@ print_io_reg_desc (SIM_DESC sd, io_reg_desc *desc, int val, int mode)
|
||||
|
||||
void
|
||||
print_io_byte (SIM_DESC sd, const char *name, io_reg_desc *desc,
|
||||
uint8 val, uint16 addr)
|
||||
uint8_t val, uint16_t addr)
|
||||
{
|
||||
sim_io_printf (sd, " %-9.9s @ 0x%04x 0x%02x ", name, addr, val);
|
||||
if (desc)
|
||||
@ -600,7 +600,7 @@ print_io_byte (SIM_DESC sd, const char *name, io_reg_desc *desc,
|
||||
|
||||
void
|
||||
print_io_word (SIM_DESC sd, const char *name, io_reg_desc *desc,
|
||||
uint16 val, uint16 addr)
|
||||
uint16_t val, uint16_t addr)
|
||||
{
|
||||
sim_io_printf (sd, " %-9.9s @ 0x%04x 0x%04x ", name, addr, val);
|
||||
if (desc)
|
||||
@ -608,7 +608,7 @@ print_io_word (SIM_DESC sd, const char *name, io_reg_desc *desc,
|
||||
}
|
||||
|
||||
void
|
||||
cpu_ccr_update_tst8 (sim_cpu *cpu, uint8 val)
|
||||
cpu_ccr_update_tst8 (sim_cpu *cpu, uint8_t val)
|
||||
{
|
||||
cpu_set_ccr_V (cpu, 0);
|
||||
cpu_set_ccr_N (cpu, val & 0x80 ? 1 : 0);
|
||||
@ -616,10 +616,10 @@ cpu_ccr_update_tst8 (sim_cpu *cpu, uint8 val)
|
||||
}
|
||||
|
||||
|
||||
uint16
|
||||
uint16_t
|
||||
cpu_fetch_relbranch (sim_cpu *cpu)
|
||||
{
|
||||
uint16 addr = (uint16) cpu_fetch8 (cpu);
|
||||
uint16_t addr = (uint16_t) cpu_fetch8 (cpu);
|
||||
|
||||
if (addr & 0x0080)
|
||||
{
|
||||
@ -629,10 +629,10 @@ cpu_fetch_relbranch (sim_cpu *cpu)
|
||||
return addr;
|
||||
}
|
||||
|
||||
uint16
|
||||
uint16_t
|
||||
cpu_fetch_relbranch16 (sim_cpu *cpu)
|
||||
{
|
||||
uint16 addr = cpu_fetch16 (cpu);
|
||||
uint16_t addr = cpu_fetch16 (cpu);
|
||||
|
||||
addr += cpu->cpu_regs.pc;
|
||||
return addr;
|
||||
@ -664,10 +664,10 @@ cpu_push_all (sim_cpu *cpu)
|
||||
void
|
||||
cpu_dbcc (sim_cpu *cpu)
|
||||
{
|
||||
uint8 code;
|
||||
uint16 addr;
|
||||
uint16 inc;
|
||||
uint16 reg;
|
||||
uint8_t code;
|
||||
uint16_t addr;
|
||||
uint16_t inc;
|
||||
uint16_t reg;
|
||||
|
||||
code = cpu_fetch8 (cpu);
|
||||
switch (code & 0xc0)
|
||||
@ -703,11 +703,11 @@ cpu_dbcc (sim_cpu *cpu)
|
||||
}
|
||||
|
||||
void
|
||||
cpu_exg (sim_cpu *cpu, uint8 code)
|
||||
cpu_exg (sim_cpu *cpu, uint8_t code)
|
||||
{
|
||||
uint8 r1, r2;
|
||||
uint16 src1;
|
||||
uint16 src2;
|
||||
uint8_t r1, r2;
|
||||
uint16_t src1;
|
||||
uint16_t src2;
|
||||
|
||||
r1 = (code >> 4) & 0x07;
|
||||
r2 = code & 0x07;
|
||||
@ -741,7 +741,7 @@ cpu_special (sim_cpu *cpu, enum M6811_Special special)
|
||||
{
|
||||
case M6811_RTI:
|
||||
{
|
||||
uint8 ccr;
|
||||
uint8_t ccr;
|
||||
|
||||
ccr = cpu_m68hc11_pop_uint8 (cpu);
|
||||
cpu_set_ccr (cpu, ccr);
|
||||
@ -755,7 +755,7 @@ cpu_special (sim_cpu *cpu, enum M6811_Special special)
|
||||
|
||||
case M6812_RTI:
|
||||
{
|
||||
uint8 ccr;
|
||||
uint8_t ccr;
|
||||
|
||||
ccr = cpu_m68hc12_pop_uint8 (cpu);
|
||||
cpu_set_ccr (cpu, ccr);
|
||||
@ -791,7 +791,7 @@ cpu_special (sim_cpu *cpu, enum M6811_Special special)
|
||||
case M6811_ILLEGAL:
|
||||
if (cpu->cpu_emul_syscall)
|
||||
{
|
||||
uint8 op = memory_read8 (cpu,
|
||||
uint8_t op = memory_read8 (cpu,
|
||||
cpu_get_pc (cpu) - 1);
|
||||
if (op == 0x41)
|
||||
{
|
||||
@ -833,8 +833,8 @@ cpu_special (sim_cpu *cpu, enum M6811_Special special)
|
||||
|
||||
case M6812_IDIVS:
|
||||
{
|
||||
int32 src1 = (int16) cpu_get_d (cpu);
|
||||
int32 src2 = (int16) cpu_get_x (cpu);
|
||||
int32_t src1 = (int16_t) cpu_get_d (cpu);
|
||||
int32_t src2 = (int16_t) cpu_get_x (cpu);
|
||||
|
||||
if (src2 == 0)
|
||||
{
|
||||
@ -855,9 +855,9 @@ cpu_special (sim_cpu *cpu, enum M6811_Special special)
|
||||
|
||||
case M6812_EDIV:
|
||||
{
|
||||
uint32 src1 = (uint32) cpu_get_x (cpu);
|
||||
uint32 src2 = (uint32) (cpu_get_y (cpu) << 16)
|
||||
| (uint32) (cpu_get_d (cpu));
|
||||
uint32_t src1 = (uint32_t) cpu_get_x (cpu);
|
||||
uint32_t src2 = (uint32_t) (cpu_get_y (cpu) << 16)
|
||||
| (uint32_t) (cpu_get_d (cpu));
|
||||
|
||||
if (src1 == 0)
|
||||
{
|
||||
@ -878,9 +878,9 @@ cpu_special (sim_cpu *cpu, enum M6811_Special special)
|
||||
|
||||
case M6812_EDIVS:
|
||||
{
|
||||
int32 src1 = (int16) cpu_get_x (cpu);
|
||||
int32 src2 = (uint32) (cpu_get_y (cpu) << 16)
|
||||
| (uint32) (cpu_get_d (cpu));
|
||||
int32_t src1 = (int16_t) cpu_get_x (cpu);
|
||||
int32_t src2 = (uint32_t) (cpu_get_y (cpu) << 16)
|
||||
| (uint32_t) (cpu_get_d (cpu));
|
||||
|
||||
if (src1 == 0)
|
||||
{
|
||||
@ -901,10 +901,10 @@ cpu_special (sim_cpu *cpu, enum M6811_Special special)
|
||||
|
||||
case M6812_EMULS:
|
||||
{
|
||||
int32 src1, src2;
|
||||
int32_t src1, src2;
|
||||
|
||||
src1 = (int16) cpu_get_d (cpu);
|
||||
src2 = (int16) cpu_get_y (cpu);
|
||||
src1 = (int16_t) cpu_get_d (cpu);
|
||||
src2 = (int16_t) cpu_get_y (cpu);
|
||||
src1 = src1 * src2;
|
||||
cpu_set_d (cpu, src1 & 0x0ffff);
|
||||
cpu_set_y (cpu, src1 >> 16);
|
||||
@ -916,15 +916,15 @@ cpu_special (sim_cpu *cpu, enum M6811_Special special)
|
||||
|
||||
case M6812_EMACS:
|
||||
{
|
||||
int32 src1, src2;
|
||||
uint16 addr;
|
||||
int32_t src1, src2;
|
||||
uint16_t addr;
|
||||
|
||||
addr = cpu_fetch16 (cpu);
|
||||
src1 = (int16) memory_read16 (cpu, cpu_get_x (cpu));
|
||||
src2 = (int16) memory_read16 (cpu, cpu_get_y (cpu));
|
||||
src1 = (int16_t) memory_read16 (cpu, cpu_get_x (cpu));
|
||||
src2 = (int16_t) memory_read16 (cpu, cpu_get_y (cpu));
|
||||
src1 = src1 * src2;
|
||||
src2 = (((uint32) memory_read16 (cpu, addr)) << 16)
|
||||
| (uint32) memory_read16 (cpu, addr + 2);
|
||||
src2 = (((uint32_t) memory_read16 (cpu, addr)) << 16)
|
||||
| (uint32_t) memory_read16 (cpu, addr + 2);
|
||||
|
||||
memory_write16 (cpu, addr, (src1 + src2) >> 16);
|
||||
memory_write16 (cpu, addr + 2, (src1 + src2));
|
||||
@ -935,8 +935,8 @@ cpu_special (sim_cpu *cpu, enum M6811_Special special)
|
||||
|
||||
case M6812_CALL:
|
||||
{
|
||||
uint8 page;
|
||||
uint16 addr;
|
||||
uint8_t page;
|
||||
uint16_t addr;
|
||||
|
||||
addr = cpu_fetch16 (cpu);
|
||||
page = cpu_fetch8 (cpu);
|
||||
@ -951,9 +951,9 @@ cpu_special (sim_cpu *cpu, enum M6811_Special special)
|
||||
|
||||
case M6812_CALL_INDIRECT:
|
||||
{
|
||||
uint8 code;
|
||||
uint16 addr;
|
||||
uint8 page;
|
||||
uint8_t code;
|
||||
uint16_t addr;
|
||||
uint8_t page;
|
||||
|
||||
code = memory_read8 (cpu, cpu_get_pc (cpu));
|
||||
/* Indirect addressing call has the page specified in the
|
||||
@ -979,8 +979,8 @@ cpu_special (sim_cpu *cpu, enum M6811_Special special)
|
||||
|
||||
case M6812_RTC:
|
||||
{
|
||||
uint8 page = cpu_m68hc12_pop_uint8 (cpu);
|
||||
uint16 addr = cpu_m68hc12_pop_uint16 (cpu);
|
||||
uint8_t page = cpu_m68hc12_pop_uint8 (cpu);
|
||||
uint16_t addr = cpu_m68hc12_pop_uint16 (cpu);
|
||||
|
||||
cpu_set_page (cpu, page);
|
||||
cpu_set_pc (cpu, addr);
|
||||
@ -1019,7 +1019,7 @@ cpu_single_step (sim_cpu *cpu)
|
||||
/* VARARGS */
|
||||
void
|
||||
sim_memory_error (sim_cpu *cpu, SIM_SIGNAL excep,
|
||||
uint16 addr, const char *message, ...)
|
||||
uint16_t addr, const char *message, ...)
|
||||
{
|
||||
char buf[1024];
|
||||
va_list args;
|
||||
@ -1035,7 +1035,7 @@ sim_memory_error (sim_cpu *cpu, SIM_SIGNAL excep,
|
||||
|
||||
void
|
||||
cpu_memory_exception (sim_cpu *cpu, SIM_SIGNAL excep,
|
||||
uint16 addr, const char *message)
|
||||
uint16_t addr, const char *message)
|
||||
{
|
||||
if (cpu->cpu_running == 0)
|
||||
return;
|
||||
|
||||
@ -32,14 +32,6 @@ along with this program. If not, see <http://www.gnu.org/licenses/>. */
|
||||
#include "sim-signal.h"
|
||||
#include "sim-types.h"
|
||||
|
||||
typedef unsigned8 uint8;
|
||||
typedef unsigned16 uint16;
|
||||
typedef signed16 int16;
|
||||
typedef unsigned32 uint32;
|
||||
typedef signed32 int32;
|
||||
typedef unsigned64 uint64;
|
||||
typedef signed64 int64;
|
||||
|
||||
struct _sim_cpu;
|
||||
|
||||
#include "interrupts.h"
|
||||
@ -98,9 +90,9 @@ typedef struct io_reg_desc io_reg_desc;
|
||||
extern void print_io_reg_desc (SIM_DESC sd, io_reg_desc *desc, int val,
|
||||
int mode);
|
||||
extern void print_io_byte (SIM_DESC sd, const char *name,
|
||||
io_reg_desc *desc, uint8 val, uint16 addr);
|
||||
io_reg_desc *desc, uint8_t val, uint16_t addr);
|
||||
extern void print_io_word (SIM_DESC sd, const char *name,
|
||||
io_reg_desc *desc, uint16 val, uint16 addr);
|
||||
io_reg_desc *desc, uint16_t val, uint16_t addr);
|
||||
|
||||
|
||||
/* List of special 68HC11&68HC12 instructions that are not handled by the
|
||||
@ -161,11 +153,11 @@ struct _sim_cpu {
|
||||
/* CPU absolute cycle time. The cycle time is updated after
|
||||
each instruction, by the number of cycles taken by the instruction.
|
||||
It is cleared only when reset occurs. */
|
||||
signed64 cpu_absolute_cycle;
|
||||
int64_t cpu_absolute_cycle;
|
||||
|
||||
/* Number of cycles to increment after the current instruction.
|
||||
This is also the number of ticks for the generic event scheduler. */
|
||||
uint8 cpu_current_cycle;
|
||||
uint8_t cpu_current_cycle;
|
||||
int cpu_emul_syscall;
|
||||
int cpu_is_initialized;
|
||||
int cpu_running;
|
||||
@ -182,7 +174,7 @@ struct _sim_cpu {
|
||||
/* The starting address specified in ELF header. */
|
||||
int cpu_elf_start;
|
||||
|
||||
uint16 cpu_insn_pc;
|
||||
uint16_t cpu_insn_pc;
|
||||
|
||||
/* CPU frequency. This is the quartz frequency. It is divided by 4 to
|
||||
get the cycle time. This is used for the timer rate and for the baud
|
||||
@ -197,15 +189,15 @@ struct _sim_cpu {
|
||||
enum cpu_type cpu_type;
|
||||
|
||||
/* Initial value of the CONFIG register. */
|
||||
uint8 cpu_config;
|
||||
uint8 cpu_use_local_config;
|
||||
uint8_t cpu_config;
|
||||
uint8_t cpu_use_local_config;
|
||||
|
||||
uint8 ios[MAX_PORTS];
|
||||
uint8_t ios[MAX_PORTS];
|
||||
|
||||
/* Memory bank parameters which describe how the memory bank window
|
||||
is mapped in memory and how to convert it in virtual address. */
|
||||
uint16 bank_start;
|
||||
uint16 bank_end;
|
||||
uint16_t bank_start;
|
||||
uint16_t bank_end;
|
||||
address_word bank_virtual;
|
||||
unsigned bank_shift;
|
||||
|
||||
@ -219,14 +211,14 @@ struct _sim_cpu {
|
||||
/* Returns the cpu absolute cycle time (A virtual counter incremented
|
||||
at each 68HC11 E clock). */
|
||||
#define cpu_current_cycle(cpu) ((cpu)->cpu_absolute_cycle)
|
||||
#define cpu_add_cycles(cpu, T) ((cpu)->cpu_current_cycle += (signed64) (T))
|
||||
#define cpu_add_cycles(cpu, T) ((cpu)->cpu_current_cycle += (int64_t) (T))
|
||||
#define cpu_is_running(cpu) ((cpu)->cpu_running)
|
||||
|
||||
/* Get the IO/RAM base addresses depending on the M6811_INIT register. */
|
||||
#define cpu_get_io_base(cpu) \
|
||||
(((uint16)(((cpu)->ios[M6811_INIT]) & 0x0F)) << 12)
|
||||
(((uint16_t)(((cpu)->ios[M6811_INIT]) & 0x0F)) << 12)
|
||||
#define cpu_get_reg_base(cpu) \
|
||||
(((uint16)(((cpu)->ios[M6811_INIT]) & 0xF0)) << 8)
|
||||
(((uint16_t)(((cpu)->ios[M6811_INIT]) & 0xF0)) << 8)
|
||||
|
||||
/* Returns the different CPU registers. */
|
||||
#define cpu_get_ccr(cpu) ((cpu)->cpu_regs.ccr)
|
||||
@ -288,7 +280,7 @@ struct _sim_cpu {
|
||||
|
||||
extern void cpu_memory_exception (sim_cpu *cpu,
|
||||
SIM_SIGNAL excep,
|
||||
uint16 addr,
|
||||
uint16_t addr,
|
||||
const char *message);
|
||||
|
||||
STATIC_INLINE UNUSED address_word
|
||||
@ -302,10 +294,10 @@ phys_to_virt (sim_cpu *cpu, address_word addr)
|
||||
return (address_word) (addr);
|
||||
}
|
||||
|
||||
STATIC_INLINE UNUSED uint8
|
||||
memory_read8 (sim_cpu *cpu, uint16 addr)
|
||||
STATIC_INLINE UNUSED uint8_t
|
||||
memory_read8 (sim_cpu *cpu, uint16_t addr)
|
||||
{
|
||||
uint8 val;
|
||||
uint8_t val;
|
||||
|
||||
if (sim_core_read_buffer (CPU_STATE (cpu), cpu, 0, &val, addr, 1) != 1)
|
||||
{
|
||||
@ -316,7 +308,7 @@ memory_read8 (sim_cpu *cpu, uint16 addr)
|
||||
}
|
||||
|
||||
STATIC_INLINE UNUSED void
|
||||
memory_write8 (sim_cpu *cpu, uint16 addr, uint8 val)
|
||||
memory_write8 (sim_cpu *cpu, uint16_t addr, uint8_t val)
|
||||
{
|
||||
if (sim_core_write_buffer (CPU_STATE (cpu), cpu, 0, &val, addr, 1) != 1)
|
||||
{
|
||||
@ -325,23 +317,23 @@ memory_write8 (sim_cpu *cpu, uint16 addr, uint8 val)
|
||||
}
|
||||
}
|
||||
|
||||
STATIC_INLINE UNUSED uint16
|
||||
memory_read16 (sim_cpu *cpu, uint16 addr)
|
||||
STATIC_INLINE UNUSED uint16_t
|
||||
memory_read16 (sim_cpu *cpu, uint16_t addr)
|
||||
{
|
||||
uint8 b[2];
|
||||
uint8_t b[2];
|
||||
|
||||
if (sim_core_read_buffer (CPU_STATE (cpu), cpu, 0, b, addr, 2) != 2)
|
||||
{
|
||||
cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
|
||||
"Read error");
|
||||
}
|
||||
return (((uint16) (b[0])) << 8) | ((uint16) b[1]);
|
||||
return (((uint16_t) (b[0])) << 8) | ((uint16_t) b[1]);
|
||||
}
|
||||
|
||||
STATIC_INLINE UNUSED void
|
||||
memory_write16 (sim_cpu *cpu, uint16 addr, uint16 val)
|
||||
memory_write16 (sim_cpu *cpu, uint16_t addr, uint16_t val)
|
||||
{
|
||||
uint8 b[2];
|
||||
uint8_t b[2];
|
||||
|
||||
b[0] = val >> 8;
|
||||
b[1] = val;
|
||||
@ -352,10 +344,10 @@ memory_write16 (sim_cpu *cpu, uint16 addr, uint16 val)
|
||||
}
|
||||
}
|
||||
extern void
|
||||
cpu_ccr_update_tst8 (sim_cpu *cpu, uint8 val);
|
||||
cpu_ccr_update_tst8 (sim_cpu *cpu, uint8_t val);
|
||||
|
||||
STATIC_INLINE UNUSED void
|
||||
cpu_ccr_update_tst16 (sim_cpu *cpu, uint16 val)
|
||||
cpu_ccr_update_tst16 (sim_cpu *cpu, uint16_t val)
|
||||
{
|
||||
cpu_set_ccr_V (cpu, 0);
|
||||
cpu_set_ccr_N (cpu, val & 0x8000 ? 1 : 0);
|
||||
@ -363,7 +355,7 @@ cpu_ccr_update_tst16 (sim_cpu *cpu, uint16 val)
|
||||
}
|
||||
|
||||
STATIC_INLINE UNUSED void
|
||||
cpu_ccr_update_shift8 (sim_cpu *cpu, uint8 val)
|
||||
cpu_ccr_update_shift8 (sim_cpu *cpu, uint8_t val)
|
||||
{
|
||||
cpu_set_ccr_N (cpu, val & 0x80 ? 1 : 0);
|
||||
cpu_set_ccr_Z (cpu, val == 0 ? 1 : 0);
|
||||
@ -371,7 +363,7 @@ cpu_ccr_update_shift8 (sim_cpu *cpu, uint8 val)
|
||||
}
|
||||
|
||||
STATIC_INLINE UNUSED void
|
||||
cpu_ccr_update_shift16 (sim_cpu *cpu, uint16 val)
|
||||
cpu_ccr_update_shift16 (sim_cpu *cpu, uint16_t val)
|
||||
{
|
||||
cpu_set_ccr_N (cpu, val & 0x8000 ? 1 : 0);
|
||||
cpu_set_ccr_Z (cpu, val == 0 ? 1 : 0);
|
||||
@ -379,7 +371,7 @@ cpu_ccr_update_shift16 (sim_cpu *cpu, uint16 val)
|
||||
}
|
||||
|
||||
STATIC_INLINE UNUSED void
|
||||
cpu_ccr_update_add8 (sim_cpu *cpu, uint8 r, uint8 a, uint8 b)
|
||||
cpu_ccr_update_add8 (sim_cpu *cpu, uint8_t r, uint8_t a, uint8_t b)
|
||||
{
|
||||
cpu_set_ccr_C (cpu, ((a & b) | (b & ~r) | (a & ~r)) & 0x80 ? 1 : 0);
|
||||
cpu_set_ccr_V (cpu, ((a & b & ~r) | (~a & ~b & r)) & 0x80 ? 1 : 0);
|
||||
@ -389,7 +381,7 @@ cpu_ccr_update_add8 (sim_cpu *cpu, uint8 r, uint8 a, uint8 b)
|
||||
|
||||
|
||||
STATIC_INLINE UNUSED void
|
||||
cpu_ccr_update_sub8 (sim_cpu *cpu, uint8 r, uint8 a, uint8 b)
|
||||
cpu_ccr_update_sub8 (sim_cpu *cpu, uint8_t r, uint8_t a, uint8_t b)
|
||||
{
|
||||
cpu_set_ccr_C (cpu, ((~a & b) | (b & r) | (~a & r)) & 0x80 ? 1 : 0);
|
||||
cpu_set_ccr_V (cpu, ((a & ~b & ~r) | (~a & b & r)) & 0x80 ? 1 : 0);
|
||||
@ -398,7 +390,7 @@ cpu_ccr_update_sub8 (sim_cpu *cpu, uint8 r, uint8 a, uint8 b)
|
||||
}
|
||||
|
||||
STATIC_INLINE UNUSED void
|
||||
cpu_ccr_update_add16 (sim_cpu *cpu, uint16 r, uint16 a, uint16 b)
|
||||
cpu_ccr_update_add16 (sim_cpu *cpu, uint16_t r, uint16_t a, uint16_t b)
|
||||
{
|
||||
cpu_set_ccr_C (cpu, ((a & b) | (b & ~r) | (a & ~r)) & 0x8000 ? 1 : 0);
|
||||
cpu_set_ccr_V (cpu, ((a & b & ~r) | (~a & ~b & r)) & 0x8000 ? 1 : 0);
|
||||
@ -407,7 +399,7 @@ cpu_ccr_update_add16 (sim_cpu *cpu, uint16 r, uint16 a, uint16 b)
|
||||
}
|
||||
|
||||
STATIC_INLINE UNUSED void
|
||||
cpu_ccr_update_sub16 (sim_cpu *cpu, uint16 r, uint16 a, uint16 b)
|
||||
cpu_ccr_update_sub16 (sim_cpu *cpu, uint16_t r, uint16_t a, uint16_t b)
|
||||
{
|
||||
cpu_set_ccr_C (cpu, ((~a & b) | (b & r) | (~a & r)) & 0x8000 ? 1 : 0);
|
||||
cpu_set_ccr_V (cpu, ((a & ~b & ~r) | (~a & b & r)) & 0x8000 ? 1 : 0);
|
||||
@ -417,39 +409,39 @@ cpu_ccr_update_sub16 (sim_cpu *cpu, uint16 r, uint16 a, uint16 b)
|
||||
|
||||
/* Push and pop instructions for 68HC11 (next-available stack mode). */
|
||||
STATIC_INLINE UNUSED void
|
||||
cpu_m68hc11_push_uint8 (sim_cpu *cpu, uint8 val)
|
||||
cpu_m68hc11_push_uint8 (sim_cpu *cpu, uint8_t val)
|
||||
{
|
||||
uint16 addr = cpu->cpu_regs.sp;
|
||||
uint16_t addr = cpu->cpu_regs.sp;
|
||||
|
||||
memory_write8 (cpu, addr, val);
|
||||
cpu->cpu_regs.sp = addr - 1;
|
||||
}
|
||||
|
||||
STATIC_INLINE UNUSED void
|
||||
cpu_m68hc11_push_uint16 (sim_cpu *cpu, uint16 val)
|
||||
cpu_m68hc11_push_uint16 (sim_cpu *cpu, uint16_t val)
|
||||
{
|
||||
uint16 addr = cpu->cpu_regs.sp - 1;
|
||||
uint16_t addr = cpu->cpu_regs.sp - 1;
|
||||
|
||||
memory_write16 (cpu, addr, val);
|
||||
cpu->cpu_regs.sp = addr - 1;
|
||||
}
|
||||
|
||||
STATIC_INLINE UNUSED uint8
|
||||
STATIC_INLINE UNUSED uint8_t
|
||||
cpu_m68hc11_pop_uint8 (sim_cpu *cpu)
|
||||
{
|
||||
uint16 addr = cpu->cpu_regs.sp;
|
||||
uint8 val;
|
||||
uint16_t addr = cpu->cpu_regs.sp;
|
||||
uint8_t val;
|
||||
|
||||
val = memory_read8 (cpu, addr + 1);
|
||||
cpu->cpu_regs.sp = addr + 1;
|
||||
return val;
|
||||
}
|
||||
|
||||
STATIC_INLINE UNUSED uint16
|
||||
STATIC_INLINE UNUSED uint16_t
|
||||
cpu_m68hc11_pop_uint16 (sim_cpu *cpu)
|
||||
{
|
||||
uint16 addr = cpu->cpu_regs.sp;
|
||||
uint16 val;
|
||||
uint16_t addr = cpu->cpu_regs.sp;
|
||||
uint16_t val;
|
||||
|
||||
val = memory_read16 (cpu, addr + 1);
|
||||
cpu->cpu_regs.sp = addr + 2;
|
||||
@ -458,9 +450,9 @@ cpu_m68hc11_pop_uint16 (sim_cpu *cpu)
|
||||
|
||||
/* Push and pop instructions for 68HC12 (last-used stack mode). */
|
||||
STATIC_INLINE UNUSED void
|
||||
cpu_m68hc12_push_uint8 (sim_cpu *cpu, uint8 val)
|
||||
cpu_m68hc12_push_uint8 (sim_cpu *cpu, uint8_t val)
|
||||
{
|
||||
uint16 addr = cpu->cpu_regs.sp;
|
||||
uint16_t addr = cpu->cpu_regs.sp;
|
||||
|
||||
addr --;
|
||||
memory_write8 (cpu, addr, val);
|
||||
@ -468,31 +460,31 @@ cpu_m68hc12_push_uint8 (sim_cpu *cpu, uint8 val)
|
||||
}
|
||||
|
||||
STATIC_INLINE UNUSED void
|
||||
cpu_m68hc12_push_uint16 (sim_cpu *cpu, uint16 val)
|
||||
cpu_m68hc12_push_uint16 (sim_cpu *cpu, uint16_t val)
|
||||
{
|
||||
uint16 addr = cpu->cpu_regs.sp;
|
||||
uint16_t addr = cpu->cpu_regs.sp;
|
||||
|
||||
addr -= 2;
|
||||
memory_write16 (cpu, addr, val);
|
||||
cpu->cpu_regs.sp = addr;
|
||||
}
|
||||
|
||||
STATIC_INLINE UNUSED uint8
|
||||
STATIC_INLINE UNUSED uint8_t
|
||||
cpu_m68hc12_pop_uint8 (sim_cpu *cpu)
|
||||
{
|
||||
uint16 addr = cpu->cpu_regs.sp;
|
||||
uint8 val;
|
||||
uint16_t addr = cpu->cpu_regs.sp;
|
||||
uint8_t val;
|
||||
|
||||
val = memory_read8 (cpu, addr);
|
||||
cpu->cpu_regs.sp = addr + 1;
|
||||
return val;
|
||||
}
|
||||
|
||||
STATIC_INLINE UNUSED uint16
|
||||
STATIC_INLINE UNUSED uint16_t
|
||||
cpu_m68hc12_pop_uint16 (sim_cpu *cpu)
|
||||
{
|
||||
uint16 addr = cpu->cpu_regs.sp;
|
||||
uint16 val;
|
||||
uint16_t addr = cpu->cpu_regs.sp;
|
||||
uint16_t val;
|
||||
|
||||
val = memory_read16 (cpu, addr);
|
||||
cpu->cpu_regs.sp = addr + 2;
|
||||
@ -500,37 +492,37 @@ cpu_m68hc12_pop_uint16 (sim_cpu *cpu)
|
||||
}
|
||||
|
||||
/* Fetch a 8/16 bit value and update the PC. */
|
||||
STATIC_INLINE UNUSED uint8
|
||||
STATIC_INLINE UNUSED uint8_t
|
||||
cpu_fetch8 (sim_cpu *cpu)
|
||||
{
|
||||
uint16 addr = cpu->cpu_regs.pc;
|
||||
uint8 val;
|
||||
uint16_t addr = cpu->cpu_regs.pc;
|
||||
uint8_t val;
|
||||
|
||||
val = memory_read8 (cpu, addr);
|
||||
cpu->cpu_regs.pc = addr + 1;
|
||||
return val;
|
||||
}
|
||||
|
||||
STATIC_INLINE UNUSED uint16
|
||||
STATIC_INLINE UNUSED uint16_t
|
||||
cpu_fetch16 (sim_cpu *cpu)
|
||||
{
|
||||
uint16 addr = cpu->cpu_regs.pc;
|
||||
uint16 val;
|
||||
uint16_t addr = cpu->cpu_regs.pc;
|
||||
uint16_t val;
|
||||
|
||||
val = memory_read16 (cpu, addr);
|
||||
cpu->cpu_regs.pc = addr + 2;
|
||||
return val;
|
||||
}
|
||||
|
||||
extern void cpu_call (sim_cpu *cpu, uint16 addr);
|
||||
extern void cpu_exg (sim_cpu *cpu, uint8 code);
|
||||
extern void cpu_call (sim_cpu *cpu, uint16_t addr);
|
||||
extern void cpu_exg (sim_cpu *cpu, uint8_t code);
|
||||
extern void cpu_dbcc (sim_cpu *cpu);
|
||||
extern void cpu_special (sim_cpu *cpu, enum M6811_Special special);
|
||||
extern void cpu_move8 (sim_cpu *cpu, uint8 op);
|
||||
extern void cpu_move16 (sim_cpu *cpu, uint8 op);
|
||||
extern void cpu_move8 (sim_cpu *cpu, uint8_t op);
|
||||
extern void cpu_move16 (sim_cpu *cpu, uint8_t op);
|
||||
|
||||
extern uint16 cpu_fetch_relbranch (sim_cpu *cpu);
|
||||
extern uint16 cpu_fetch_relbranch16 (sim_cpu *cpu);
|
||||
extern uint16_t cpu_fetch_relbranch (sim_cpu *cpu);
|
||||
extern uint16_t cpu_fetch_relbranch16 (sim_cpu *cpu);
|
||||
extern void cpu_push_all (sim_cpu *cpu);
|
||||
extern void cpu_single_step (sim_cpu *cpu);
|
||||
|
||||
@ -540,30 +532,30 @@ extern int cpu_initialize (SIM_DESC sd, sim_cpu *cpu);
|
||||
|
||||
/* Returns the address of a 68HC12 indexed operand.
|
||||
Pre and post modifications are handled on the source register. */
|
||||
extern uint16 cpu_get_indexed_operand_addr (sim_cpu *cpu, int restricted);
|
||||
extern uint16_t cpu_get_indexed_operand_addr (sim_cpu *cpu, int restricted);
|
||||
|
||||
extern void cpu_return (sim_cpu *cpu);
|
||||
extern void cpu_set_sp (sim_cpu *cpu, uint16 val);
|
||||
extern void cpu_set_sp (sim_cpu *cpu, uint16_t val);
|
||||
extern int cpu_reset (sim_cpu *cpu);
|
||||
extern int cpu_restart (sim_cpu *cpu);
|
||||
extern void sim_memory_error (sim_cpu *cpu, SIM_SIGNAL excep,
|
||||
uint16 addr, const char *message, ...);
|
||||
uint16_t addr, const char *message, ...);
|
||||
extern void emul_os (int op, sim_cpu *cpu);
|
||||
extern void cpu_interp_m6811 (sim_cpu *cpu);
|
||||
extern void cpu_interp_m6812 (sim_cpu *cpu);
|
||||
|
||||
extern int m68hc11cpu_set_oscillator (SIM_DESC sd, const char *port,
|
||||
double ton, double toff,
|
||||
signed64 repeat);
|
||||
int64_t repeat);
|
||||
extern int m68hc11cpu_clear_oscillator (SIM_DESC sd, const char *port);
|
||||
extern void m68hc11cpu_set_port (struct hw *me, sim_cpu *cpu,
|
||||
unsigned addr, uint8 val);
|
||||
unsigned addr, uint8_t val);
|
||||
|
||||
extern void sim_board_reset (SIM_DESC sd);
|
||||
|
||||
#define PRINT_TIME 0x01
|
||||
#define PRINT_CYCLE 0x02
|
||||
extern const char *cycle_to_string (sim_cpu *cpu, signed64 t, int flags);
|
||||
extern const char *cycle_to_string (sim_cpu *cpu, int64_t t, int flags);
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user