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* gas/config/tc-arm.c (NEON_ENC_TAB): Add vmaxnm, vminnm entries.
(vfp_or_neon_is_neon_bits): Add NEON_CHECK_ARCH8 enumerator. (vfp_or_neon_is_neon): Add check for SIMD for ARMv8. (do_maxnm): New function. (insns): Add vmaxnm, vminnm entries. * gas/testsuite/gas/testsuite/gas/armv8-a+fp.d: Update testcase. * gas/testsuite/gas/testsuite/gas/armv8-a+fp.s: Likewise. * gas/testsuite/gas/testsuite/gas/armv8-a+simd.d: New testcase. * gas/testsuite/gas/testsuite/gas/armv8-a+simd.s: Likewise. * opcodes/arm-dis.c (coprocessor_opcodes): Add VMAXNM/VMINNM. (neon_opcodes): Likewise.
This commit is contained in:
Matthew Gretton-Dann
parent
33399f071c
commit
73924fbcf8
@ -1,3 +1,11 @@
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2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
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* config/tc-arm.c (NEON_ENC_TAB): Add vmaxnm, vminnm entries.
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(vfp_or_neon_is_neon_bits): Add NEON_CHECK_ARCH8 enumerator.
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(vfp_or_neon_is_neon): Add check for SIMD for ARMv8.
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(do_maxnm): New function.
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(insns): Add vmaxnm, vminnm entries.
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2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
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* config/tc-arm.c (NEON_ENC_TAB): Add entries for VSEL.
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@ -12345,7 +12345,9 @@ struct neon_tab_entry
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X(vseleq, 0xe000a00, N_INV, N_INV), \
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X(vselvs, 0xe100a00, N_INV, N_INV), \
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X(vselge, 0xe200a00, N_INV, N_INV), \
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X(vselgt, 0xe300a00, N_INV, N_INV)
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X(vselgt, 0xe300a00, N_INV, N_INV), \
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X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
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X(vminnm, 0xe800a40, 0x3200f10, N_INV)
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enum neon_opc
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{
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@ -13982,7 +13984,8 @@ do_neon_dyadic_if_i_d (void)
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enum vfp_or_neon_is_neon_bits
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{
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NEON_CHECK_CC = 1,
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NEON_CHECK_ARCH = 2
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NEON_CHECK_ARCH = 2,
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NEON_CHECK_ARCH8 = 4
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};
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/* Call this function if an instruction which may have belonged to the VFP or
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@ -14020,7 +14023,14 @@ vfp_or_neon_is_neon (unsigned check)
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}
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if ((check & NEON_CHECK_ARCH)
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&& !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1))
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&& !mark_feature_used (&fpu_neon_ext_v1))
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{
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first_error (_(BAD_FPU));
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return FAIL;
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}
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if ((check & NEON_CHECK_ARCH8)
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&& !mark_feature_used (&fpu_neon_ext_armv8))
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{
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first_error (_(BAD_FPU));
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return FAIL;
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@ -15874,6 +15884,20 @@ do_vsel (void)
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first_error (_("invalid instruction shape"));
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}
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static void
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do_vmaxnm (void)
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{
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set_it_insn_type (OUTSIDE_IT_INSN);
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if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8) == SUCCESS)
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return;
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if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH8) == FAIL)
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return;
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neon_dyadic_misc (NT_untyped, N_F32, 0);
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}
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/* Overall per-instruction processing. */
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@ -18087,6 +18111,8 @@ static const struct asm_opcode insns[] =
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nUF(vselvs, _vselvs, 3, (RVSD, RVSD, RVSD), vsel),
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nUF(vselge, _vselge, 3, (RVSD, RVSD, RVSD), vsel),
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nUF(vselgt, _vselgt, 3, (RVSD, RVSD, RVSD), vsel),
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nUF(vmaxnm, _vmaxnm, 3, (RNSDQ, oRNSDQ, RNSDQ), vmaxnm),
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nUF(vminnm, _vminnm, 3, (RNSDQ, oRNSDQ, RNSDQ), vmaxnm),
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#undef ARM_VARIANT
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#define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
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@ -1,3 +1,10 @@
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2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
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* gas/testsuite/gas/armv8-a+fp.d: Update testcase.
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* gas/testsuite/gas/armv8-a+fp.s: Likewise.
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* gas/testsuite/gas/armv8-a+simd.d: New testcase.
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* gas/testsuite/gas/armv8-a+simd.s: Likewise.
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2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
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* gas/arm/armv8-a+fp.d: New testcase.
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@ -12,6 +12,22 @@ Disassembly of section .text:
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0[0-9a-f]+ <[^>]+> fe500ba0 vselvs.f64 d16, d16, d16
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0[0-9a-f]+ <[^>]+> fe2ffb0f vselge.f64 d15, d15, d15
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0[0-9a-f]+ <[^>]+> fe7ffbaf vselgt.f64 d31, d31, d31
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0[0-9a-f]+ <[^>]+> fe800a00 vmaxnm.f32 s0, s0, s0
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0[0-9a-f]+ <[^>]+> fec00aa0 vmaxnm.f32 s1, s1, s1
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0[0-9a-f]+ <[^>]+> fe8ffa0f vmaxnm.f32 s30, s30, s30
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0[0-9a-f]+ <[^>]+> fecffaaf vmaxnm.f32 s31, s31, s31
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0[0-9a-f]+ <[^>]+> fe800b00 vmaxnm.f64 d0, d0, d0
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0[0-9a-f]+ <[^>]+> fec00ba0 vmaxnm.f64 d16, d16, d16
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0[0-9a-f]+ <[^>]+> fe8ffb0f vmaxnm.f64 d15, d15, d15
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0[0-9a-f]+ <[^>]+> fecffbaf vmaxnm.f64 d31, d31, d31
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0[0-9a-f]+ <[^>]+> fe800a40 vminnm.f32 s0, s0, s0
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0[0-9a-f]+ <[^>]+> fec00ae0 vminnm.f32 s1, s1, s1
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0[0-9a-f]+ <[^>]+> fe8ffa4f vminnm.f32 s30, s30, s30
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0[0-9a-f]+ <[^>]+> fecffaef vminnm.f32 s31, s31, s31
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0[0-9a-f]+ <[^>]+> fe800b40 vminnm.f64 d0, d0, d0
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0[0-9a-f]+ <[^>]+> fec00be0 vminnm.f64 d16, d16, d16
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0[0-9a-f]+ <[^>]+> fe8ffb4f vminnm.f64 d15, d15, d15
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0[0-9a-f]+ <[^>]+> fecffbef vminnm.f64 d31, d31, d31
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0[0-9a-f]+ <[^>]+> fe00 0a00 vseleq.f32 s0, s0, s0
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0[0-9a-f]+ <[^>]+> fe50 0aa0 vselvs.f32 s1, s1, s1
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0[0-9a-f]+ <[^>]+> fe2f fa0f vselge.f32 s30, s30, s30
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@ -20,3 +36,19 @@ Disassembly of section .text:
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0[0-9a-f]+ <[^>]+> fe50 0ba0 vselvs.f64 d16, d16, d16
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0[0-9a-f]+ <[^>]+> fe2f fb0f vselge.f64 d15, d15, d15
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0[0-9a-f]+ <[^>]+> fe7f fbaf vselgt.f64 d31, d31, d31
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0[0-9a-f]+ <[^>]+> fe80 0a00 vmaxnm.f32 s0, s0, s0
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0[0-9a-f]+ <[^>]+> fec0 0aa0 vmaxnm.f32 s1, s1, s1
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0[0-9a-f]+ <[^>]+> fe8f fa0f vmaxnm.f32 s30, s30, s30
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0[0-9a-f]+ <[^>]+> fecf faaf vmaxnm.f32 s31, s31, s31
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0[0-9a-f]+ <[^>]+> fe80 0b00 vmaxnm.f64 d0, d0, d0
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0[0-9a-f]+ <[^>]+> fec0 0ba0 vmaxnm.f64 d16, d16, d16
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0[0-9a-f]+ <[^>]+> fe8f fb0f vmaxnm.f64 d15, d15, d15
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0[0-9a-f]+ <[^>]+> fecf fbaf vmaxnm.f64 d31, d31, d31
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0[0-9a-f]+ <[^>]+> fe80 0a40 vminnm.f32 s0, s0, s0
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0[0-9a-f]+ <[^>]+> fec0 0ae0 vminnm.f32 s1, s1, s1
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0[0-9a-f]+ <[^>]+> fe8f fa4f vminnm.f32 s30, s30, s30
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0[0-9a-f]+ <[^>]+> fecf faef vminnm.f32 s31, s31, s31
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0[0-9a-f]+ <[^>]+> fe80 0b40 vminnm.f64 d0, d0, d0
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0[0-9a-f]+ <[^>]+> fec0 0be0 vminnm.f64 d16, d16, d16
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0[0-9a-f]+ <[^>]+> fe8f fb4f vminnm.f64 d15, d15, d15
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0[0-9a-f]+ <[^>]+> fecf fbef vminnm.f64 d31, d31, d31
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@ -12,6 +12,22 @@
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vselvs.f64 d16, d16, d16
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vselge.f64 d15, d15, d15
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vselgt.f64 d31, d31, d31
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vmaxnm.f32 s0, s0, s0
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vmaxnm.f32 s1, s1, s1
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vmaxnm.f32 s30, s30, s30
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vmaxnm.f32 s31, s31, s31
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vmaxnm.f64 d0, d0, d0
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vmaxnm.f64 d16, d16, d16
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vmaxnm.f64 d15, d15, d15
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vmaxnm.f64 d31, d31, d31
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vminnm.f32 s0, s0, s0
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vminnm.f32 s1, s1, s1
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vminnm.f32 s30, s30, s30
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vminnm.f32 s31, s31, s31
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vminnm.f64 d0, d0, d0
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vminnm.f64 d16, d16, d16
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vminnm.f64 d15, d15, d15
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vminnm.f64 d31, d31, d31
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.thumb
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vseleq.f32 s0, s0, s0
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@ -22,3 +38,19 @@
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vselvs.f64 d16, d16, d16
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vselge.f64 d15, d15, d15
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vselgt.f64 d31, d31, d31
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vmaxnm.f32 s0, s0, s0
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vmaxnm.f32 s1, s1, s1
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vmaxnm.f32 s30, s30, s30
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vmaxnm.f32 s31, s31, s31
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vmaxnm.f64 d0, d0, d0
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vmaxnm.f64 d16, d16, d16
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vmaxnm.f64 d15, d15, d15
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vmaxnm.f64 d31, d31, d31
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vminnm.f32 s0, s0, s0
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vminnm.f32 s1, s1, s1
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vminnm.f32 s30, s30, s30
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vminnm.f32 s31, s31, s31
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vminnm.f64 d0, d0, d0
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vminnm.f64 d16, d16, d16
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vminnm.f64 d15, d15, d15
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vminnm.f64 d31, d31, d31
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38
gas/testsuite/gas/arm/armv8-a+simd.d
Normal file
38
gas/testsuite/gas/arm/armv8-a+simd.d
Normal file
@ -0,0 +1,38 @@
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#name: Valid v8-a+simdv3
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#objdump: -dr --prefix-addresses --show-raw-insn
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.*: +file format .*arm.*
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Disassembly of section .text:
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0[0-9a-f]+ <[^>]+> f3000f10 vmaxnm.f32 d0, d0, d0
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0[0-9a-f]+ <[^>]+> f3400fb0 vmaxnm.f32 d16, d16, d16
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0[0-9a-f]+ <[^>]+> f30fff1f vmaxnm.f32 d15, d15, d15
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0[0-9a-f]+ <[^>]+> f34fffbf vmaxnm.f32 d31, d31, d31
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0[0-9a-f]+ <[^>]+> f3000f50 vmaxnm.f32 q0, q0, q0
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0[0-9a-f]+ <[^>]+> f3400ff0 vmaxnm.f32 q8, q8, q8
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0[0-9a-f]+ <[^>]+> f30eef5e vmaxnm.f32 q7, q7, q7
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0[0-9a-f]+ <[^>]+> f34eeffe vmaxnm.f32 q15, q15, q15
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0[0-9a-f]+ <[^>]+> f3200f10 vminnm.f32 d0, d0, d0
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0[0-9a-f]+ <[^>]+> f3600fb0 vminnm.f32 d16, d16, d16
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0[0-9a-f]+ <[^>]+> f32fff1f vminnm.f32 d15, d15, d15
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0[0-9a-f]+ <[^>]+> f36fffbf vminnm.f32 d31, d31, d31
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0[0-9a-f]+ <[^>]+> f3200f50 vminnm.f32 q0, q0, q0
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0[0-9a-f]+ <[^>]+> f3600ff0 vminnm.f32 q8, q8, q8
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0[0-9a-f]+ <[^>]+> f32eef5e vminnm.f32 q7, q7, q7
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0[0-9a-f]+ <[^>]+> f36eeffe vminnm.f32 q15, q15, q15
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0[0-9a-f]+ <[^>]+> ff00 0f10 vmaxnm.f32 d0, d0, d0
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0[0-9a-f]+ <[^>]+> ff40 0fb0 vmaxnm.f32 d16, d16, d16
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0[0-9a-f]+ <[^>]+> ff0f ff1f vmaxnm.f32 d15, d15, d15
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0[0-9a-f]+ <[^>]+> ff4f ffbf vmaxnm.f32 d31, d31, d31
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0[0-9a-f]+ <[^>]+> ff00 0f50 vmaxnm.f32 q0, q0, q0
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0[0-9a-f]+ <[^>]+> ff40 0ff0 vmaxnm.f32 q8, q8, q8
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0[0-9a-f]+ <[^>]+> ff0e ef5e vmaxnm.f32 q7, q7, q7
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0[0-9a-f]+ <[^>]+> ff4e effe vmaxnm.f32 q15, q15, q15
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0[0-9a-f]+ <[^>]+> ff20 0f10 vminnm.f32 d0, d0, d0
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0[0-9a-f]+ <[^>]+> ff60 0fb0 vminnm.f32 d16, d16, d16
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0[0-9a-f]+ <[^>]+> ff2f ff1f vminnm.f32 d15, d15, d15
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0[0-9a-f]+ <[^>]+> ff6f ffbf vminnm.f32 d31, d31, d31
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0[0-9a-f]+ <[^>]+> ff20 0f50 vminnm.f32 q0, q0, q0
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0[0-9a-f]+ <[^>]+> ff60 0ff0 vminnm.f32 q8, q8, q8
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0[0-9a-f]+ <[^>]+> ff2e ef5e vminnm.f32 q7, q7, q7
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0[0-9a-f]+ <[^>]+> ff6e effe vminnm.f32 q15, q15, q15
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39
gas/testsuite/gas/arm/armv8-a+simd.s
Normal file
39
gas/testsuite/gas/arm/armv8-a+simd.s
Normal file
@ -0,0 +1,39 @@
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.syntax unified
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.arch armv8-a
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.arch_extension simd
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.arm
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vmaxnm.f32 d0, d0, d0
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vmaxnm.f32 d16, d16, d16
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vmaxnm.f32 d15, d15, d15
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vmaxnm.f32 d31, d31, d31
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vmaxnm.f32 q0, q0, q0
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vmaxnm.f32 q8, q8, q8
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vmaxnm.f32 q7, q7, q7
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vmaxnm.f32 q15, q15, q15
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vminnm.f32 d0, d0, d0
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vminnm.f32 d16, d16, d16
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vminnm.f32 d15, d15, d15
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vminnm.f32 d31, d31, d31
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vminnm.f32 q0, q0, q0
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vminnm.f32 q8, q8, q8
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vminnm.f32 q7, q7, q7
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vminnm.f32 q15, q15, q15
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.thumb
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vmaxnm.f32 d0, d0, d0
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vmaxnm.f32 d16, d16, d16
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vmaxnm.f32 d15, d15, d15
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vmaxnm.f32 d31, d31, d31
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vmaxnm.f32 q0, q0, q0
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vmaxnm.f32 q8, q8, q8
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vmaxnm.f32 q7, q7, q7
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vmaxnm.f32 q15, q15, q15
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vminnm.f32 d0, d0, d0
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vminnm.f32 d16, d16, d16
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vminnm.f32 d15, d15, d15
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vminnm.f32 d31, d31, d31
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vminnm.f32 q0, q0, q0
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vminnm.f32 q8, q8, q8
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vminnm.f32 q7, q7, q7
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vminnm.f32 q15, q15, q15
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@ -1,3 +1,8 @@
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2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
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* arm-dis.c (coprocessor_opcodes): Add VMAXNM/VMINNM.
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(neon_opcodes): Likewise.
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2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
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* arm-dis.c (coprocessor_opcodes): Add VSEL.
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@ -490,6 +490,10 @@ static const struct opcode32 coprocessor_opcodes[] =
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/* FP v5. */
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{FPU_VFP_EXT_ARMV8, 0xfe000a00, 0xff800f00, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
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{FPU_VFP_EXT_ARMV8, 0xfe000b00, 0xff800f00, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
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{FPU_VFP_EXT_ARMV8, 0xfe800a00, 0xffb00f40, "vmaxnm%u.f32\t%y1, %y2, %y0"},
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{FPU_VFP_EXT_ARMV8, 0xfe800b00, 0xffb00f40, "vmaxnm%u.f64\t%z1, %z2, %z0"},
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{FPU_VFP_EXT_ARMV8, 0xfe800a40, 0xffb00f40, "vminnm%u.f32\t%y1, %y2, %y0"},
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{FPU_VFP_EXT_ARMV8, 0xfe800b40, 0xffb00f40, "vminnm%u.f64\t%z1, %z2, %z0"},
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/* Generic coprocessor instructions. */
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{ 0, SENTINEL_GENERIC_START, 0, "" },
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@ -607,6 +611,8 @@ static const struct opcode32 neon_opcodes[] =
|
||||
{FPU_NEON_EXT_V1, 0xf3b30600, 0xffb30e10, "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
|
||||
|
||||
/* Three registers of the same length. */
|
||||
{FPU_NEON_EXT_ARMV8, 0xf3000f10, 0xffa00f10, "vmaxnm%u.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
||||
{FPU_NEON_EXT_ARMV8, 0xf3200f10, 0xffa00f10, "vminnm%u.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
||||
{FPU_NEON_EXT_V1, 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
||||
{FPU_NEON_EXT_V1, 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
||||
{FPU_NEON_EXT_V1, 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
||||
|
||||
Loading…
Reference in New Issue
Block a user