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[BINUTILS, AARCH64, 7/8] Add system registers for Memory Tagging Extension
This patch is part of the patch series to add support for ARMv8.5-A Memory Tagging Extensions which is an optional extension to ARMv8.5-A and is enabled using the +memtag command line option. This patch adds all the system registers that are part of this extension and are accessible via the MRS/MSR instructions: - TCO - TFSRE0_SL1 - TFSR_EL1 - TFSR_EL2 - TFSR_EL3 - TFSR_EL12 - RGSR_EL1 - GCR_EL1 TCO is also accessible with the MSR(immediate) instruction. *** opcodes/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * aarch64-opc.c (aarch64_sys_regs): New entries for TCO, TFSRE0_SL1, TFSR_EL1, TFSR_EL2, TFSR_EL3, TFSR_EL12, RGSR_EL1 and GCR_EL1. (aarch64_sys_reg_supported_p): New check for above. (aarch64_pstatefields): New entry for TCO. (aarch64_pstatefield_supported_p): New check for above. *** gas/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * testsuite/gas/aarch64/sysreg-4.s: Test TCO, TFSRE0_SL1, TFSR_EL1, TFSR_EL2, TFSR_EL3, TFSR_EL12, RGSR_EL1 and GCR_EL1 MSR and MRS. * testsuite/gas/aarch64/sysreg-4.d: Likewise. * testsuite/gas/aarch64/illegal-sysreg-4.l: Likewise.
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Sudakshina Das
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@ -1,3 +1,11 @@
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2018-11-12 Sudakshina Das <sudi.das@arm.com>
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* testsuite/gas/aarch64/sysreg-4.s: Test TCO, TFSRE0_SL1,
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TFSR_EL1, TFSR_EL2, TFSR_EL3, TFSR_EL12, RGSR_EL1 and
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GCR_EL1 MSR and MRS.
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* testsuite/gas/aarch64/sysreg-4.d: Likewise.
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* testsuite/gas/aarch64/illegal-sysreg-4.l: Likewise.
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2018-11-12 Sudakshina Das <sudi.das@arm.com>
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* config/tc-aarch64.c (parse_operands): Add switch case for
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@ -14,3 +14,24 @@
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[^:]*:[0-9]+: Error: selected processor does not support system register name 'scxtnum_el3'
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[^:]*:[0-9]+: Error: selected processor does not support system register name 'scxtnum_el12'
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[^:]*:[0-9]+: Error: selected processor does not support system register name 'id_pfr2_el1'
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[^:]*:[0-9]+: Error: selected processor does not support system register name 'tco'
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[^:]*:[0-9]+: Error: selected processor does not support system register name 'tco'
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[^:]*:[0-9]+: Error: selected processor does not support system register name 'tfsre0_el1'
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[^:]*:[0-9]+: Error: selected processor does not support system register name 'tfsr_el1'
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[^:]*:[0-9]+: Error: selected processor does not support system register name 'tfsr_el2'
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[^:]*:[0-9]+: Error: selected processor does not support system register name 'tfsr_el3'
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[^:]*:[0-9]+: Error: selected processor does not support system register name 'tfsr_el12'
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[^:]*:[0-9]+: Error: selected processor does not support system register name 'rgsr_el1'
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[^:]*:[0-9]+: Error: selected processor does not support system register name 'gcr_el1'
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[^:]*:[0-9]+: Error: selected processor does not support PSTATE field name 'tco'
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[^:]*:[0-9]+: Error: selected processor does not support system register name 'tco'
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[^:]*:[0-9]+: Error: selected processor does not support PSTATE field name 'tco'
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[^:]*:[0-9]+: Error: selected processor does not support system register name 'tco'
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[^:]*:[0-9]+: Error: selected processor does not support system register name 'tfsre0_el1'
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[^:]*:[0-9]+: Error: selected processor does not support system register name 'tfsr_el1'
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[^:]*:[0-9]+: Error: selected processor does not support system register name 'tfsr_el2'
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[^:]*:[0-9]+: Error: selected processor does not support system register name 'tfsr_el3'
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[^:]*:[0-9]+: Error: selected processor does not support system register name 'tfsr_el12'
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[^:]*:[0-9]+: Error: selected processor does not support system register name 'rgsr_el1'
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[^:]*:[0-9]+: Error: selected processor does not support system register name 'gcr_el1'
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[^:]*:[0-9]+: Error: selected processor does not support PSTATE field name 'tco'
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@ -1,5 +1,5 @@
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#source: sysreg-4.s
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#as: -march=armv8.5-a+rng
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#as: -march=armv8.5-a+rng+memtag
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#objdump: -dr
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.*: file format .*
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@ -19,3 +19,22 @@ Disassembly of section \.text:
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.*: d53ed0e7 mrs x7, scxtnum_el3
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.*: d53dd0e7 mrs x7, scxtnum_el12
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.*: d5380388 mrs x8, id_pfr2_el1
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.*: d53b42e1 mrs x1, tco
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.*: d53b42e2 mrs x2, tco
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.*: d5386621 mrs x1, tfsre0_el1
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.*: d5386501 mrs x1, tfsr_el1
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.*: d53c6502 mrs x2, tfsr_el2
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.*: d53e6603 mrs x3, tfsr_el3
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.*: d53d660c mrs x12, tfsr_el12
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.*: d53810a1 mrs x1, rgsr_el1
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.*: d53810c3 mrs x3, gcr_el1
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.*: d51b42e1 msr tco, x1
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.*: d51b42e2 msr tco, x2
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.*: d5186621 msr tfsre0_el1, x1
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.*: d5186501 msr tfsr_el1, x1
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.*: d51c6502 msr tfsr_el2, x2
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.*: d51e6603 msr tfsr_el3, x3
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.*: d51d660c msr tfsr_el12, x12
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.*: d51810a1 msr rgsr_el1, x1
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.*: d51810c3 msr gcr_el1, x3
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.*: d503489f msr tco, #0x8
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@ -12,3 +12,29 @@ func:
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mrs x7, scxtnum_el3
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mrs x7, scxtnum_el12
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mrs x8, id_pfr2_el1
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# ARMv8.5-a+memtag
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# MRS (register)
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mrs x1, tco
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mrs x2, TCO
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mrs x1, tfsre0_el1
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mrs x1, TFSR_EL1
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mrs x2, TFSR_EL2
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mrs x3, TFSR_EL3
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mrs x12, TFSR_EL12
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mrs x1, rgsr_el1
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mrs x3, gcr_el1
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# MSR (register)
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msr tco, x1
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msr TCO, x2
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msr tfsre0_el1, x1
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msr TFSR_EL1, x1
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msr TFSR_EL2, x2
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msr TFSR_EL3, x3
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msr TFSR_EL12, x12
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msr rgsr_el1, x1
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msr gcr_el1, x3
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# MSR (immediate)
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msr TCO, #8
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@ -1,3 +1,12 @@
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2018-11-12 Sudakshina Das <sudi.das@arm.com>
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* aarch64-opc.c (aarch64_sys_regs): New entries for TCO,
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TFSRE0_SL1, TFSR_EL1, TFSR_EL2, TFSR_EL3, TFSR_EL12,
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RGSR_EL1 and GCR_EL1.
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(aarch64_sys_reg_supported_p): New check for above.
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(aarch64_pstatefields): New entry for TCO.
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(aarch64_pstatefield_supported_p): New check for above.
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2018-11-12 Sudakshina Das <sudi.das@arm.com>
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* aarch64-asm.c (aarch64_ins_addr_simple_2): New.
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@ -3929,6 +3929,14 @@ const aarch64_sys_reg aarch64_sys_regs [] =
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{ "contextidr_el12", CPENC (3, 5, C13, C0, 1), F_ARCHEXT },
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{ "rndr", CPENC(3,3,C2,C4,0), F_ARCHEXT | F_REG_READ }, /* RO */
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{ "rndrrs", CPENC(3,3,C2,C4,1), F_ARCHEXT | F_REG_READ }, /* RO */
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{ "tco", CPENC(3,3,C4,C2,7), F_ARCHEXT },
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{ "tfsre0_el1", CPENC(3,0,C6,C6,1), F_ARCHEXT },
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{ "tfsr_el1", CPENC(3,0,C6,C5,0), F_ARCHEXT },
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{ "tfsr_el2", CPENC(3,4,C6,C5,0), F_ARCHEXT },
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{ "tfsr_el3", CPENC(3,6,C6,C6,0), F_ARCHEXT },
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{ "tfsr_el12", CPENC(3,5,C6,C6,0), F_ARCHEXT },
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{ "rgsr_el1", CPENC(3,0,C1,C0,5), F_ARCHEXT },
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{ "gcr_el1", CPENC(3,0,C1,C0,6), F_ARCHEXT },
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{ "tpidr_el0", CPENC(3,3,C13,C0,2), 0 },
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{ "tpidrro_el0", CPENC(3,3,C13,C0,3), 0 }, /* RW */
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{ "tpidr_el1", CPENC(3,0,C13,C0,4), 0 },
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@ -4392,6 +4400,18 @@ aarch64_sys_reg_supported_p (const aarch64_feature_set features,
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&& AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_5)))
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return FALSE;
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/* System Registers in ARMv8.5-A with AARCH64_FEATURE_MEMTAG. */
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if ((reg->value == CPENC (3, 3, C4, C2, 7)
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|| reg->value == CPENC (3, 0, C6, C6, 1)
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|| reg->value == CPENC (3, 0, C6, C5, 0)
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|| reg->value == CPENC (3, 4, C6, C5, 0)
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|| reg->value == CPENC (3, 6, C6, C6, 0)
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|| reg->value == CPENC (3, 5, C6, C6, 0)
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|| reg->value == CPENC (3, 0, C1, C0, 5)
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|| reg->value == CPENC (3, 0, C1, C0, 6))
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&& !(AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_MEMTAG)))
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return FALSE;
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return TRUE;
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}
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@ -4411,6 +4431,7 @@ const aarch64_sys_reg aarch64_pstatefields [] =
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{ "uao", 0x03, F_ARCHEXT },
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{ "ssbs", 0x19, F_ARCHEXT },
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{ "dit", 0x1a, F_ARCHEXT },
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{ "tco", 0x1c, F_ARCHEXT },
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{ 0, CPENC(0,0,0,0,0), 0 },
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};
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@ -4441,6 +4462,11 @@ aarch64_pstatefield_supported_p (const aarch64_feature_set features,
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&& !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_4))
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return FALSE;
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/* TCO. Values are from aarch64_pstatefields. */
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if (reg->value == 0x1c
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&& !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_MEMTAG))
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return FALSE;
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return TRUE;
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}
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