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x86/APX: correct .insn opcode space determination when REX2 is needed
In this case spaces 0f38 and 0f3a may not be put in place. To achieve the intended effect, operand parsing (but not operand processing) needs pulling ahead, so we know whether eGRP-s are in use.
This commit is contained in:
Jan Beulich
parent
eb3f3841da
commit
6804f42c67
@ -12922,46 +12922,9 @@ s_insn (int dummy ATTRIBUTE_UNUSED)
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}
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}
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/* Trim off encoding space. */
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if (j > 1 && !i.insn_opcode_space && (val >> ((j - 1) * 8)) == 0x0f)
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{
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uint8_t byte = val >> ((--j - 1) * 8);
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i.insn_opcode_space = SPACE_0F;
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switch (byte & -(j > 1))
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{
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case 0x38:
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i.insn_opcode_space = SPACE_0F38;
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--j;
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break;
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case 0x3a:
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i.insn_opcode_space = SPACE_0F3A;
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--j;
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break;
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}
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i.tm.opcode_space = i.insn_opcode_space;
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val &= ((uint64_t)1 << (j * 8)) - 1;
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}
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if (!i.tm.opcode_space && (vex || evex))
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/* Arrange for build_vex_prefix() to properly emit 0xC4/0xC5.
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Also avoid hitting abort() there or in build_evex_prefix(). */
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i.tm.opcode_space = i.insn_opcode_space == SPACE_0F ? SPACE_0F
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: SPACE_0F38;
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if (j > 2)
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{
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as_bad (_("opcode residual (%#"PRIx64") too wide"), (uint64_t) val);
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goto bad;
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}
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i.opcode_length = j;
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/* Handle operands, if any. */
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/* Parse operands, if any, before evaluating encoding space. */
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if (*line == ',')
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{
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i386_operand_type combined;
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expressionS *disp_exp = NULL;
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bool changed;
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i.memshift = -1;
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ptr = parse_operands (line + 1, &i386_mnemonics[MN__insn]);
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@ -12986,6 +12949,48 @@ s_insn (int dummy ATTRIBUTE_UNUSED)
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/* No need to distinguish encoding_evex and encoding_evex512. */
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if (i.encoding == encoding_evex512)
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i.encoding = encoding_evex;
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}
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/* Trim off encoding space. */
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if (j > 1 && !i.insn_opcode_space && (val >> ((j - 1) * 8)) == 0x0f)
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{
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uint8_t byte = val >> ((--j - 1) * 8);
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i.insn_opcode_space = SPACE_0F;
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switch (byte & -(j > 1 && !i.rex2_encoding
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&& (i.encoding != encoding_egpr || evex)))
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{
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case 0x38:
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i.insn_opcode_space = SPACE_0F38;
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--j;
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break;
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case 0x3a:
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i.insn_opcode_space = SPACE_0F3A;
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--j;
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break;
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}
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i.tm.opcode_space = i.insn_opcode_space;
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val &= ((uint64_t)1 << (j * 8)) - 1;
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}
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if (!i.tm.opcode_space && (vex || evex))
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/* Arrange for build_vex_prefix() to properly emit 0xC4/0xC5.
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Also avoid hitting abort() there or in build_evex_prefix(). */
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i.tm.opcode_space = i.insn_opcode_space == SPACE_0F ? SPACE_0F
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: SPACE_0F38;
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if (j > 2)
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{
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as_bad (_("opcode residual (%#"PRIx64") too wide"), (uint64_t) val);
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goto done;
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}
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i.opcode_length = j;
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/* Handle operands, if any. */
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if (i.operands)
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{
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i386_operand_type combined;
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expressionS *disp_exp = NULL;
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bool changed;
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if (i.encoding == encoding_egpr)
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{
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38
gas/testsuite/gas/i386/insn-rex2.l
Normal file
38
gas/testsuite/gas/i386/insn-rex2.l
Normal file
@ -0,0 +1,38 @@
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[ ]*[0-9]+[ ]+\.text
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[ ]*[0-9]+[ ]+insn_rex2:
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[ ]*[0-9]+ .... D58001C0[ ]+\.insn \{rex2\} 0x0f01/0, %eax
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[ ]*[0-9]+ .... D58038C0[ ]+\.insn \{rex2\} 0x0f38/0, %eax
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[ ]*[0-9]+ .... D5803801[ ]+\.insn \{rex2\} 0x0f3801/0, %eax
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[ ]*[0-9]+ +C0
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[ ]*[0-9]+ .... D5803901[ ]+\.insn \{rex2\} 0x0f3901/0, %eax
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[ ]*[0-9]+ +C0
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[ ]*[0-9]+ .... D5803A01[ ]+\.insn \{rex2\} 0x0f3a01/0, \$0xCC, %eax
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[ ]*[0-9]+ +C0CC
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[ ]*[0-9]+[ ]+
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[ ]*[0-9]+ .... D58801C0[ ]+\.insn \{rex2\} 0x0f01/0, %rax
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[ ]*[0-9]+ .... D58838C0[ ]+\.insn \{rex2\} 0x0f38/0, %rax
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[ ]*[0-9]+ .... D5883801[ ]+\.insn \{rex2\} 0x0f3801/0, %rax
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[ ]*[0-9]+ +C0
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[ ]*[0-9]+ .... D5883901[ ]+\.insn \{rex2\} 0x0f3901/0, %rax
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[ ]*[0-9]+ +C0
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[ ]*[0-9]+ .... D5883A01[ ]+\.insn \{rex2\} 0x0f3a01/0, \$0xCC, %rax
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[ ]*[0-9]+ +C0CC
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[ ]*[0-9]+[ ]+
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[ ]*[0-9]+ .... D58901C0[ ]+\.insn \{rex2\} 0x0f01/0, %r8
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[ ]*[0-9]+ .... D58938C0[ ]+\.insn \{rex2\} 0x0f38/0, %r8
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[ ]*[0-9]+ .... D5893801[ ]+\.insn \{rex2\} 0x0f3801/0, %r8
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[ ]*[0-9]+ +C0
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[ ]*[0-9]+ .... D5893901[ ]+\.insn \{rex2\} 0x0f3901/0, %r8
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[ ]*[0-9]+ +C0
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[ ]*[0-9]+ .... D5893A01[ ]+\.insn \{rex2\} 0x0f3a01/0, \$0xCC, %r8
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[ ]*[0-9]+ +C0CC
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[ ]*[0-9]+[ ]+
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[ ]*[0-9]+ .... D59801C0[ ]+\.insn 0x0f01/0, %r16
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[ ]*[0-9]+ .... D59838C0[ ]+\.insn 0x0f38/0, %r16
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[ ]*[0-9]+ .... D5983801[ ]+\.insn 0x0f3801/0, %r16
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[ ]*[0-9]+ +C0
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[ ]*[0-9]+ .... D5983901[ ]+\.insn 0x0f3901/0, %r16
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[ ]*[0-9]+ +C0
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[ ]*[0-9]+ .... D5983A01[ ]+\.insn 0x0f3a01/0, \$0xCC, %r16
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[ ]*[0-9]+[ ]+C0CC
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#pass
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25
gas/testsuite/gas/i386/insn-rex2.s
Normal file
25
gas/testsuite/gas/i386/insn-rex2.s
Normal file
@ -0,0 +1,25 @@
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.text
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insn_rex2:
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.insn {rex2} 0x0f01/0, %eax
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.insn {rex2} 0x0f38/0, %eax
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.insn {rex2} 0x0f3801/0, %eax
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.insn {rex2} 0x0f3901/0, %eax
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.insn {rex2} 0x0f3a01/0, $0xCC, %eax
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.insn {rex2} 0x0f01/0, %rax
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.insn {rex2} 0x0f38/0, %rax
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.insn {rex2} 0x0f3801/0, %rax
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.insn {rex2} 0x0f3901/0, %rax
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.insn {rex2} 0x0f3a01/0, $0xCC, %rax
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.insn {rex2} 0x0f01/0, %r8
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.insn {rex2} 0x0f38/0, %r8
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.insn {rex2} 0x0f3801/0, %r8
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.insn {rex2} 0x0f3901/0, %r8
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.insn {rex2} 0x0f3a01/0, $0xCC, %r8
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.insn 0x0f01/0, %r16
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.insn 0x0f38/0, %r16
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.insn 0x0f3801/0, %r16
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.insn 0x0f3901/0, %r16
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.insn 0x0f3a01/0, $0xCC, %r16
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@ -126,6 +126,7 @@ run_dump_test "x86-64-sysenter-mixed"
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run_dump_test "x86-64-sysenter-amd"
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run_list_test "x86-64-sysenter-amd" "-mamd64"
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run_dump_test "insn-64"
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run_list_test "insn-rex2" "-aln --divide"
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run_dump_test "noreg64"
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run_list_test "noreg64"
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run_dump_test "noreg64-data16"
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