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* config/bfin-parse.y (asm_1): Implement HLT instruction. Fix comments for DBGA, DBGAH and DBGAL. * config/tc-bfin.c (bfin_gen_pseudodbg_assert): Change according to the new encoding of DBGA, DBGAH, and DBGAL. include/ * opcode/bfin.h (PseudoDbg_Assert): Add bits_grp and mask_grp. (PseudoDbg_Assert_grp_bits, PseudoDbg_Assert_grp_mask): Define. (PseudoDbg_Assert_dbgop_bits, PseudoDbg_Assert_dbgop_mask, PseudoDbg_Assert_dontcare_bits, PseudoDbg_Assert_dontcare_mask): Adjust accordingly. (init_PseudoDbg_Assert): Add PseudoDbg_Assert_grp_bits and PseudoDbg_Assert_grp_mask. opcodes/ * bfin-dis.c (decode_pseudodbg_assert_0): Change according to the new encoding of DBGA, DBGAH, and DBGAL. (_print_insn_bfin): Likewise.
This commit is contained in:
Jie Zhang
parent
7dd8f318c1
commit
66a6900a09
@ -1,3 +1,10 @@
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2009-09-04 Jie Zhang <jie.zhang@analog.com>
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* config/bfin-parse.y (asm_1): Implement HLT instruction.
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Fix comments for DBGA, DBGAH and DBGAL.
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* config/tc-bfin.c (bfin_gen_pseudodbg_assert): Change according
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to the new encoding of DBGA, DBGAH, and DBGAL.
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2009-09-04 Jie Zhang <jie.zhang@analog.com>
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* doc/all.texi: Replace BFIN with Blackfin.
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@ -3588,21 +3588,27 @@ asm_1:
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$$ = bfin_gen_pseudodbg (3, 5, 0);
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}
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| HLT
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{
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notethat ("psedoDEBUG: HLT\n");
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$$ = bfin_gen_pseudodbg (3, 4, 0);
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}
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| DBGA LPAREN HALF_REG COMMA expr RPAREN
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{
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notethat ("pseudodbg_assert: DBGA (dregs_lo , uimm16 )\n");
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notethat ("pseudodbg_assert: DBGA (regs_lo/hi , uimm16 )\n");
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$$ = bfin_gen_pseudodbg_assert (IS_H ($3), &$3, uimm16 ($5));
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}
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| DBGAH LPAREN REG COMMA expr RPAREN
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{
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notethat ("pseudodbg_assert: DBGAH (dregs , uimm16 )\n");
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notethat ("pseudodbg_assert: DBGAH (regs , uimm16 )\n");
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$$ = bfin_gen_pseudodbg_assert (3, &$3, uimm16 ($5));
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}
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| DBGAL LPAREN REG COMMA expr RPAREN
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{
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notethat ("psedodbg_assert: DBGAL (dregs , uimm16 )\n");
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notethat ("psedodbg_assert: DBGAL (regs , uimm16 )\n");
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$$ = bfin_gen_pseudodbg_assert (2, &$3, uimm16 ($5));
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}
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@ -1791,10 +1791,13 @@ bfin_gen_pseudodbg (int fn, int reg, int grp)
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INSTR_T
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bfin_gen_pseudodbg_assert (int dbgop, REG_T regtest, int expected)
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{
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int grp;
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INIT (PseudoDbg_Assert);
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ASSIGN (dbgop);
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ASSIGN_R (regtest);
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grp = GROUP (regtest);
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ASSIGN (grp);
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ASSIGN (expected);
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return GEN_OPCODE32 ();
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@ -1,3 +1,13 @@
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2009-09-04 Jie Zhang <jie.zhang@analog.com>
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* opcode/bfin.h (PseudoDbg_Assert): Add bits_grp and mask_grp.
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(PseudoDbg_Assert_grp_bits, PseudoDbg_Assert_grp_mask): Define.
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(PseudoDbg_Assert_dbgop_bits, PseudoDbg_Assert_dbgop_mask,
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PseudoDbg_Assert_dontcare_bits, PseudoDbg_Assert_dontcare_mask):
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Adjust accordingly.
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(init_PseudoDbg_Assert): Add PseudoDbg_Assert_grp_bits and
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PseudoDbg_Assert_grp_mask.
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2009-08-06 Michael Eager <eager@eagercon.com>
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* dis-asm.h: Decl print_insn_microblaze().
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@ -939,7 +939,7 @@ typedef struct
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/* PseudoDbg_assert
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+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
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| 1 | 1 | 1 | 1 | 0 | - | - | - | - | - |.dbgop.....|.regtest...|
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| 1 | 1 | 1 | 1 | 0 | - | - | - | dbgop |.grp.......|.regtest...|
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|.expected......................................................|
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+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
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*/
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@ -951,6 +951,8 @@ typedef struct
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int mask_expected;
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int bits_regtest;
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int mask_regtest;
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int bits_grp;
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int mask_grp;
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int bits_dbgop;
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int mask_dbgop;
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int bits_dontcare;
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@ -964,10 +966,12 @@ typedef struct
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#define PseudoDbg_Assert_expected_mask 0xffff
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#define PseudoDbg_Assert_regtest_bits 16
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#define PseudoDbg_Assert_regtest_mask 0x7
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#define PseudoDbg_Assert_dbgop_bits 19
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#define PseudoDbg_Assert_dbgop_mask 0x7
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#define PseudoDbg_Assert_dontcare_bits 22
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#define PseudoDbg_Assert_dontcare_mask 0x1f
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#define PseudoDbg_Assert_grp_bits 19
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#define PseudoDbg_Assert_grp_mask 0x7
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#define PseudoDbg_Assert_dbgop_bits 22
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#define PseudoDbg_Assert_dbgop_mask 0x3
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#define PseudoDbg_Assert_dontcare_bits 24
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#define PseudoDbg_Assert_dontcare_mask 0x7
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#define PseudoDbg_Assert_code_bits 27
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#define PseudoDbg_Assert_code_mask 0x1f
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@ -976,6 +980,7 @@ typedef struct
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PseudoDbg_Assert_opcode, \
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PseudoDbg_Assert_expected_bits, PseudoDbg_Assert_expected_mask, \
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PseudoDbg_Assert_regtest_bits, PseudoDbg_Assert_regtest_mask, \
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PseudoDbg_Assert_grp_bits, PseudoDbg_Assert_grp_mask, \
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PseudoDbg_Assert_dbgop_bits, PseudoDbg_Assert_dbgop_mask, \
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PseudoDbg_Assert_dontcare_bits, PseudoDbg_Assert_dontcare_mask, \
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PseudoDbg_Assert_code_bits, PseudoDbg_Assert_code_mask \
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@ -1,3 +1,9 @@
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2009-09-04 Jie Zhang <jie.zhang@analog.com>
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* bfin-dis.c (decode_pseudodbg_assert_0): Change according
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to the new encoding of DBGA, DBGAH, and DBGAL.
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(_print_insn_bfin): Likewise.
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2009-09-03 Jie Zhang <jie.zhang@analog.com>
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* bfin-dis.c (_print_insn_bfin): Don't declare.
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@ -4574,17 +4574,18 @@ decode_pseudodbg_assert_0 (TIword iw0, TIword iw1, disassemble_info *outf)
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{
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/* pseudodbg_assert
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+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
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| 1 | 1 | 1 | 1 | 0 | - | - | - | - | - |.dbgop.....|.regtest...|
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| 1 | 1 | 1 | 1 | 0 | - | - | - | dbgop |.grp.......|.regtest...|
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|.expected......................................................|
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+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
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int expected = ((iw1 >> PseudoDbg_Assert_expected_bits) & PseudoDbg_Assert_expected_mask);
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int dbgop = ((iw0 >> (PseudoDbg_Assert_dbgop_bits - 16)) & PseudoDbg_Assert_dbgop_mask);
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int grp = ((iw0 >> (PseudoDbg_Assert_grp_bits - 16)) & PseudoDbg_Assert_grp_mask);
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int regtest = ((iw0 >> (PseudoDbg_Assert_regtest_bits - 16)) & PseudoDbg_Assert_regtest_mask);
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if (dbgop == 0)
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{
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OUTS (outf, "DBGA (");
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OUTS (outf, dregs_lo (regtest));
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OUTS (outf, regs_lo (regtest, grp));
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OUTS (outf, ", ");
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OUTS (outf, uimm16 (expected));
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OUTS (outf, ")");
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@ -4592,7 +4593,7 @@ decode_pseudodbg_assert_0 (TIword iw0, TIword iw1, disassemble_info *outf)
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else if (dbgop == 1)
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{
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OUTS (outf, "DBGA (");
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OUTS (outf, dregs_hi (regtest));
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OUTS (outf, regs_hi (regtest, grp));
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OUTS (outf, ", ");
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OUTS (outf, uimm16 (expected));
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OUTS (outf, ")");
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@ -4600,7 +4601,7 @@ decode_pseudodbg_assert_0 (TIword iw0, TIword iw1, disassemble_info *outf)
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else if (dbgop == 2)
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{
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OUTS (outf, "DBGAL (");
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OUTS (outf, dregs (regtest));
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OUTS (outf, allregs (regtest, grp));
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OUTS (outf, ", ");
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OUTS (outf, uimm16 (expected));
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OUTS (outf, ")");
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@ -4608,7 +4609,7 @@ decode_pseudodbg_assert_0 (TIword iw0, TIword iw1, disassemble_info *outf)
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else if (dbgop == 3)
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{
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OUTS (outf, "DBGAH (");
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OUTS (outf, dregs (regtest));
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OUTS (outf, allregs (regtest, grp));
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OUTS (outf, ", ");
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OUTS (outf, uimm16 (expected));
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OUTS (outf, ")");
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@ -4712,7 +4713,7 @@ _print_insn_bfin (bfd_vma pc, disassemble_info *outf)
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else if ((iw0 & 0xFF00) == 0xF900)
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rv = decode_pseudoOChar_0 (iw0, iw1, pc, outf);
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#endif
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else if ((iw0 & 0xFFC0) == 0xf000 && (iw1 & 0x0000) == 0x0000)
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else if ((iw0 & 0xFF00) == 0xf000 && (iw1 & 0x0000) == 0x0000)
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rv = decode_pseudodbg_assert_0 (iw0, iw1, outf);
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return rv;
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