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x86: fix AVX-512 16-bit addressing

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Despite EVEX encodings not being available in real and VM86 modes,
16-bit addressing still needs to be handled properly for 16-bit
protected mode as well as 16-bit addressing in 32-bit mode. Neither
should displacements be dropped silently by the assembler, nor should
the disassembler fail to correctly scale 8-bit displacements.
This commit is contained in:
Jan Beulich 2017-11-23 11:04:18 +01:00 committed by Jan Beulich
parent 43083a502b
commit 65f3ed048f
7 changed files with 35 additions and 5 deletions
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7
gas/ChangeLog
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@ -1,3 +1,10 @@
2017-11-23 Jan Beulich <jbeulich@suse.com>
* tc-i386.c (check_VecOperands): Don't clear .disp16.
* testsuite/gas/i386/avx512f.s: Add 16-bit addressing tests.
* testsuite/gas/i386/avx512f.d,
testsuite/gas/i386/avx512f-intel.d: Adjust expectations.
2017-11-23 Jan Beulich <jbeulich@suse.com>
PR gas/22441

6
gas/config/tc-i386.c
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@ -4798,12 +4798,8 @@ check_VecOperands (const insn_template *t)
i.types[op].bitfield.vec_disp8 = 1;
else
{
/* Vector insn can only have Vec_Disp8/Disp32 in
32/64bit modes, and Vec_Disp8/Disp16 in 16bit
mode. */
/* Vector insn doesn't allow plain Disp8. */
i.types[op].bitfield.disp8 = 0;
if (flag_code != CODE_16BIT)
i.types[op].bitfield.disp16 = 0;
}
}
else if (flag_code != CODE_16BIT)

6
gas/testsuite/gas/i386/avx512f-intel.d
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@ -6649,6 +6649,9 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 62 f2 d6 58 27 aa 00 04 00 00 vptestnmq k5,zmm5,QWORD PTR \[edx\+0x400\]\{1to8\}
[ ]*[a-f0-9]+: 62 f2 d6 58 27 6a 80 vptestnmq k5,zmm5,QWORD PTR \[edx-0x400\]\{1to8\}
[ ]*[a-f0-9]+: 62 f2 d6 58 27 aa f8 fb ff ff vptestnmq k5,zmm5,QWORD PTR \[edx-0x408\]\{1to8\}
[ ]*[a-f0-9]+: 67 62 f1 7c 48 58 07 vaddps zmm0,zmm0,ZMMWORD PTR \[bx\]
[ ]*[a-f0-9]+: 67 62 f1 7c 48 58 47 01 vaddps zmm0,zmm0,ZMMWORD PTR \[bx\+0x40\]
[ ]*[a-f0-9]+: 67 62 f1 7c 48 58 87 34 12 vaddps zmm0,zmm0,ZMMWORD PTR \[bx\+0x1234\]
[ ]*[a-f0-9]+: 62 f1 d5 48 58 f4 vaddpd zmm6,zmm5,zmm4
[ ]*[a-f0-9]+: 62 f1 d5 4f 58 f4 vaddpd zmm6\{k7\},zmm5,zmm4
[ ]*[a-f0-9]+: 62 f1 d5 cf 58 f4 vaddpd zmm6\{k7\}\{z\},zmm5,zmm4
@ -13289,4 +13292,7 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 62 f2 d6 58 27 aa 00 04 00 00 vptestnmq k5,zmm5,QWORD PTR \[edx\+0x400\]\{1to8\}
[ ]*[a-f0-9]+: 62 f2 d6 58 27 6a 80 vptestnmq k5,zmm5,QWORD PTR \[edx-0x400\]\{1to8\}
[ ]*[a-f0-9]+: 62 f2 d6 58 27 aa f8 fb ff ff vptestnmq k5,zmm5,QWORD PTR \[edx-0x408\]\{1to8\}
[ ]*[a-f0-9]+: 67 62 f1 7c 48 58 07 vaddps zmm0,zmm0,ZMMWORD PTR \[bx\]
[ ]*[a-f0-9]+: 67 62 f1 7c 48 58 47 01 vaddps zmm0,zmm0,ZMMWORD PTR \[bx\+0x40\]
[ ]*[a-f0-9]+: 67 62 f1 7c 48 58 87 34 12 vaddps zmm0,zmm0,ZMMWORD PTR \[bx\+0x1234\]
#pass

6
gas/testsuite/gas/i386/avx512f.d
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@ -6648,6 +6648,9 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 62 f2 d6 58 27 aa 00 04 00 00 vptestnmq 0x400\(%edx\)\{1to8\},%zmm5,%k5
[ ]*[a-f0-9]+: 62 f2 d6 58 27 6a 80 vptestnmq -0x400\(%edx\)\{1to8\},%zmm5,%k5
[ ]*[a-f0-9]+: 62 f2 d6 58 27 aa f8 fb ff ff vptestnmq -0x408\(%edx\)\{1to8\},%zmm5,%k5
[ ]*[a-f0-9]+: 67 62 f1 7c 48 58 07 vaddps \(%bx\),%zmm0,%zmm0
[ ]*[a-f0-9]+: 67 62 f1 7c 48 58 47 01 vaddps 0x40\(%bx\),%zmm0,%zmm0
[ ]*[a-f0-9]+: 67 62 f1 7c 48 58 87 34 12 vaddps 0x1234\(%bx\),%zmm0,%zmm0
[ ]*[a-f0-9]+: 62 f1 d5 48 58 f4 vaddpd %zmm4,%zmm5,%zmm6
[ ]*[a-f0-9]+: 62 f1 d5 4f 58 f4 vaddpd %zmm4,%zmm5,%zmm6\{%k7\}
[ ]*[a-f0-9]+: 62 f1 d5 cf 58 f4 vaddpd %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
@ -13288,4 +13291,7 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 62 f2 d6 58 27 aa 00 04 00 00 vptestnmq 0x400\(%edx\)\{1to8\},%zmm5,%k5
[ ]*[a-f0-9]+: 62 f2 d6 58 27 6a 80 vptestnmq -0x400\(%edx\)\{1to8\},%zmm5,%k5
[ ]*[a-f0-9]+: 62 f2 d6 58 27 aa f8 fb ff ff vptestnmq -0x408\(%edx\)\{1to8\},%zmm5,%k5
[ ]*[a-f0-9]+: 67 62 f1 7c 48 58 07 vaddps \(%bx\),%zmm0,%zmm0
[ ]*[a-f0-9]+: 67 62 f1 7c 48 58 47 01 vaddps 0x40\(%bx\),%zmm0,%zmm0
[ ]*[a-f0-9]+: 67 62 f1 7c 48 58 87 34 12 vaddps 0x1234\(%bx\),%zmm0,%zmm0
#pass

8
gas/testsuite/gas/i386/avx512f.s
View File

@ -7262,6 +7262,10 @@ _start:
vptestnmq -1024(%edx){1to8}, %zmm5, %k5 # AVX512F Disp8
vptestnmq -1032(%edx){1to8}, %zmm5, %k5 # AVX512F
vaddps (%bx), %zmm0, %zmm0
vaddps 0x40(%bx), %zmm0, %zmm0
vaddps 0x1234(%bx), %zmm0, %zmm0
.intel_syntax noprefix
vaddpd zmm6, zmm5, zmm4 # AVX512F
vaddpd zmm6{k7}, zmm5, zmm4 # AVX512F
@ -14520,3 +14524,7 @@ _start:
vptestnmq k5, zmm5, [edx+1024]{1to8} # AVX512F
vptestnmq k5, zmm5, [edx-1024]{1to8} # AVX512F Disp8
vptestnmq k5, zmm5, [edx-1032]{1to8} # AVX512F
vaddps zmm0, zmm0, [bx]
vaddps zmm0, zmm0, [bx+0x40]
vaddps zmm0, zmm0, [bx+0x1234]

5
opcodes/ChangeLog
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@ -1,3 +1,8 @@
2017-11-23 Jan Beulich <jbeulich@suse.com>
* i386-dis.c (OP_E_memory): Also shift the 8-bit immediate in
the 16-bit addressing case.
2017-11-23 Jan Beulich <jbeulich@suse.com>
* i386-dis.c (dis386_twobyte): Correct ud1. Add ud0.

2
opcodes/i386-dis.c
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@ -15481,6 +15481,8 @@ OP_E_memory (int bytemode, int sizeflag)
disp = *codep++;
if ((disp & 0x80) != 0)
disp -= 0x100;
if (vex.evex && shift > 0)
disp <<= shift;
break;
case 2:
disp = get16 ();