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* mips-tdep.c (mips_insn32_frame_cache): Pass frame cache in
call to heuristic_proc_desc. Remove code that became redundant
as a consequence.
(read_next_frame_reg): Remove special case for SP_REGNUM.
(set_reg_offset): Fix small typo.
(reset_saved_regs): New procedure.
(mips32_heuristic_proc_desc): No longer compute a fake
procedure descriptor. Compute the full frame cache instead.
Some minor comment reformatting.
This commit is contained in:
Joel Brobecker
parent
d7ed2d610c
commit
65596487c8
@ -1,3 +1,15 @@
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2004-09-14 Joel Brobecker <brobecker@gnat.com>
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* mips-tdep.c (mips_insn32_frame_cache): Pass frame cache in
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call to heuristic_proc_desc. Remove code that became redundant
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as a consequence.
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(read_next_frame_reg): Remove special case for SP_REGNUM.
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(set_reg_offset): Fix small typo.
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(reset_saved_regs): New procedure.
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(mips32_heuristic_proc_desc): No longer compute a fake
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procedure descriptor. Compute the full frame cache instead.
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Some minor comment reformatting.
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2004-09-14 Andrew Cagney <cagney@gnu.org>
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* MAINTAINERS: Add Michael Chastain as the backup gdb.threads
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212
gdb/mips-tdep.c
212
gdb/mips-tdep.c
@ -2060,6 +2060,7 @@ mips_insn32_frame_cache (struct frame_info *next_frame, void **this_cache)
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if ((*this_cache) != NULL)
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return (*this_cache);
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cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache);
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(*this_cache) = cache;
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cache->saved_regs = trad_frame_alloc_saved_regs (next_frame);
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@ -2073,11 +2074,7 @@ mips_insn32_frame_cache (struct frame_info *next_frame, void **this_cache)
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if (start_addr == 0)
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start_addr = heuristic_proc_start (pc);
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#ifdef NOT_YET
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proc_desc = heuristic_proc_desc (start_addr, pc, next_frame, *this_cache);
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#else
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proc_desc = heuristic_proc_desc (start_addr, pc, next_frame, NULL);
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#endif
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}
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if (proc_desc == NULL)
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@ -2086,117 +2083,6 @@ mips_insn32_frame_cache (struct frame_info *next_frame, void **this_cache)
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heuristic_proc_desc and set the saved_regs right away. */
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return cache;
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/* Extract the frame's base. */
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cache->base = (frame_unwind_register_signed (next_frame, NUM_REGS + PROC_FRAME_REG (proc_desc))
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+ PROC_FRAME_OFFSET (proc_desc) - PROC_FRAME_ADJUST (proc_desc));
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kernel_trap = PROC_REG_MASK (proc_desc) & 1;
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gen_mask = kernel_trap ? 0xFFFFFFFF : PROC_REG_MASK (proc_desc);
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float_mask = kernel_trap ? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc);
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/* In any frame other than the innermost or a frame interrupted by a
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signal, we assume that all registers have been saved. This
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assumes that all register saves in a function happen before the
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first function call. */
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if (in_prologue (frame_pc_unwind (next_frame), PROC_LOW_ADDR (proc_desc))
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/* Not sure exactly what kernel_trap means, but if it means the
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kernel saves the registers without a prologue doing it, we
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better not examine the prologue to see whether registers
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have been saved yet. */
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&& !kernel_trap)
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{
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/* We need to figure out whether the registers that the
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proc_desc claims are saved have been saved yet. */
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CORE_ADDR addr;
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/* Bitmasks; set if we have found a save for the register. */
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unsigned long gen_save_found = 0;
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unsigned long float_save_found = 0;
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addr = PROC_LOW_ADDR (proc_desc);
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/* Scan through this function's instructions preceding the
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current PC, and look for those that save registers. */
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while (addr < frame_pc_unwind (next_frame))
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{
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mips32_decode_reg_save (mips32_fetch_instruction (addr),
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&gen_save_found, &float_save_found);
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addr += MIPS_INSTLEN;
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}
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gen_mask = gen_save_found;
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float_mask = float_save_found;
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}
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/* Fill in the offsets for the registers which gen_mask says were
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saved. */
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{
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CORE_ADDR reg_position = (cache->base
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+ PROC_REG_OFFSET (proc_desc));
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int ireg;
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for (ireg = MIPS_NUMREGS - 1; gen_mask; --ireg, gen_mask <<= 1)
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if (gen_mask & 0x80000000)
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{
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cache->saved_regs[NUM_REGS + ireg].addr = reg_position;
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reg_position -= mips_abi_regsize (gdbarch);
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}
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}
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/* Fill in the offsets for the registers which float_mask says were
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saved. */
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{
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CORE_ADDR reg_position = (cache->base + PROC_FREG_OFFSET (proc_desc));
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int ireg;
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/* Fill in the offsets for the float registers which float_mask
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says were saved. */
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for (ireg = MIPS_NUMREGS - 1; float_mask; --ireg, float_mask <<= 1)
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if (float_mask & 0x80000000)
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{
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const int regno =
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NUM_REGS + mips_regnum (current_gdbarch)->fp0 + ireg;
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if (mips_abi_regsize (gdbarch) == 4
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&& TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
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{
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/* On a big endian 32 bit ABI, floating point registers
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are paired to form doubles such that the most
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significant part is in $f[N+1] and the least
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significant in $f[N] vis: $f[N+1] ||| $f[N]. The
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registers are also spilled as a pair and stored as a
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double.
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When little-endian the least significant part is
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stored first leading to the memory order $f[N] and
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then $f[N+1].
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Unfortunately, when big-endian the most significant
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part of the double is stored first, and the least
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significant is stored second. This leads to the
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registers being ordered in memory as firt $f[N+1] and
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then $f[N].
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For the big-endian case make certain that the
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addresses point at the correct (swapped) locations
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$f[N] and $f[N+1] pair (keep in mind that
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reg_position is decremented each time through the
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loop). */
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if ((ireg & 1))
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cache->saved_regs[regno].addr =
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reg_position - mips_abi_regsize (gdbarch);
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else
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cache->saved_regs[regno].addr =
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reg_position + mips_abi_regsize (gdbarch);
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}
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else
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cache->saved_regs[regno].addr = reg_position;
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reg_position -= mips_abi_regsize (gdbarch);
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}
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cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->pc]
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= cache->saved_regs[NUM_REGS + RA_REGNUM];
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}
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/* SP_REGNUM, contains the value and not the address. */
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trad_frame_set_value (cache->saved_regs, NUM_REGS + MIPS_SP_REGNUM, cache->base);
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@ -2373,12 +2259,6 @@ read_next_frame_reg (struct frame_info *fi, int regno)
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regcache_cooked_read_signed (current_regcache, regno, &val);
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return val;
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}
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else if ((regno % NUM_REGS) == MIPS_SP_REGNUM)
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/* MIPS_SP_REGNUM is special, its value is stored in saved_regs.
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In fact, it is so special that it can even only be fetched
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using a raw register number! Once this code as been converted
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to frame-unwind the problem goes away. */
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return frame_unwind_register_signed (fi, regno % NUM_REGS);
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else
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return frame_unwind_register_signed (fi, regno);
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@ -2456,7 +2336,7 @@ set_reg_offset (struct mips_frame_cache *this_cache, int regnum,
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CORE_ADDR offset)
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{
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if (this_cache != NULL
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&& this_cache->saved_regs[regnum].addr == 0)
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&& this_cache->saved_regs[regnum].addr == -1)
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{
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this_cache->saved_regs[regnum + 0 * NUM_REGS].addr = offset;
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this_cache->saved_regs[regnum + 1 * NUM_REGS].addr = offset;
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@ -2755,6 +2635,26 @@ mips16_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc,
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}
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}
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/* Mark all the registers as unset in the saved_regs array
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of THIS_CACHE. Do nothing if THIS_CACHE is null. */
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void
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reset_saved_regs (struct mips_frame_cache *this_cache)
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{
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if (this_cache == NULL || this_cache->saved_regs == NULL)
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return;
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{
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const int num_regs = NUM_REGS;
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int i;
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for (i = 0; i < num_regs; i++)
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{
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this_cache->saved_regs[i].addr = -1;
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}
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}
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}
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static void
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mips32_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc,
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CORE_ADDR sp, struct frame_info *next_frame,
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@ -2762,9 +2662,12 @@ mips32_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc,
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{
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CORE_ADDR cur_pc;
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CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for frame-pointer */
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long frame_offset;
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int frame_reg = MIPS_SP_REGNUM;
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restart:
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PROC_FRAME_OFFSET (&temp_proc_desc) = 0;
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PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */
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frame_offset = 0;
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for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSTLEN)
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{
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unsigned long inst, high_word, low_word;
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@ -2783,7 +2686,7 @@ mips32_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc,
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|| high_word == 0x67bd) /* daddiu $sp,$sp,-i */
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{
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if (low_word & 0x8000) /* negative stack adjustment? */
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PROC_FRAME_OFFSET (&temp_proc_desc) += 0x10000 - low_word;
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frame_offset += 0x10000 - low_word;
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else
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/* Exit loop if a positive stack adjustment is found, which
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usually means that the stack cleanup code in the function
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@ -2792,34 +2695,37 @@ mips32_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc,
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}
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else if ((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
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{
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PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
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set_reg_offset (this_cache, reg, sp + low_word);
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}
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else if ((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
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{
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/* Irix 6.2 N32 ABI uses sd instructions for saving $gp and
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$ra. */
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PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
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set_reg_offset (this_cache, reg, sp + low_word);
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}
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else if (high_word == 0x27be) /* addiu $30,$sp,size */
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{
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/* Old gcc frame, r30 is virtual frame pointer. */
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if ((long) low_word != PROC_FRAME_OFFSET (&temp_proc_desc))
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if ((long) low_word != frame_offset)
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frame_addr = sp + low_word;
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else if (PROC_FRAME_REG (&temp_proc_desc) == MIPS_SP_REGNUM)
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else if (frame_reg == MIPS_SP_REGNUM)
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{
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unsigned alloca_adjust;
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PROC_FRAME_REG (&temp_proc_desc) = 30;
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frame_reg = 30;
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frame_addr = read_next_frame_reg (next_frame, NUM_REGS + 30);
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alloca_adjust = (unsigned) (frame_addr - (sp + low_word));
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if (alloca_adjust > 0)
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{
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/* FP > SP + frame_size. This may be because
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* of an alloca or somethings similar.
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* Fix sp to "pre-alloca" value, and try again.
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*/
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/* FP > SP + frame_size. This may be because of
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an alloca or somethings similar. Fix sp to
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"pre-alloca" value, and try again. */
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sp += alloca_adjust;
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/* Need to reset the status of all registers. Otherwise,
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we will hit a guard that prevents the new address
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for each register to be recomputed during the second
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pass. */
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reset_saved_regs (this_cache);
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goto restart;
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}
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}
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@ -2830,29 +2736,45 @@ mips32_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc,
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else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d)
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{
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/* New gcc frame, virtual frame pointer is at r30 + frame_size. */
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if (PROC_FRAME_REG (&temp_proc_desc) == MIPS_SP_REGNUM)
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if (frame_reg == MIPS_SP_REGNUM)
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{
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unsigned alloca_adjust;
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PROC_FRAME_REG (&temp_proc_desc) = 30;
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frame_reg = 30;
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frame_addr = read_next_frame_reg (next_frame, NUM_REGS + 30);
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alloca_adjust = (unsigned) (frame_addr - sp);
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if (alloca_adjust > 0)
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{
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/* FP > SP + frame_size. This may be because
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* of an alloca or somethings similar.
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* Fix sp to "pre-alloca" value, and try again.
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*/
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sp += alloca_adjust;
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goto restart;
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}
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{
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/* FP > SP + frame_size. This may be because of
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an alloca or somethings similar. Fix sp to
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"pre-alloca" value, and try again. */
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sp = frame_addr;
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/* Need to reset the status of all registers. Otherwise,
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we will hit a guard that prevents the new address
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for each register to be recomputed during the second
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pass. */
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reset_saved_regs (this_cache);
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goto restart;
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}
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}
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}
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else if ((high_word & 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
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{
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PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
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set_reg_offset (this_cache, reg, frame_addr + low_word);
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}
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}
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if (this_cache != NULL)
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{
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this_cache->base =
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(frame_unwind_register_signed (next_frame, NUM_REGS + frame_reg)
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+ frame_offset);
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/* FIXME: brobecker/2004-09-15: We should be able to get rid of
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this assignment below, eventually. But it's still needed
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for now. */
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this_cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->pc]
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= this_cache->saved_regs[NUM_REGS + RA_REGNUM];
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}
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}
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static mips_extra_func_info_t
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