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x86: FMA4 scalar insns ignore VEX.L
Just like other VEX-encoded scalar insns do. Besides a testcase for this behavior also introduce one to verify that XOP scalar insns don't honor -mavxscalar=256, as they don't ignore XOP.L.
This commit is contained in:
Jan Beulich
parent
e6123d0c61
commit
6384fd9e1d
@ -1,3 +1,9 @@
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2020-07-08 Jan Beulich <jbeulich@suse.com>
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* testsuite/gas/i386/fma4-lig.d, testsuite/gas/i386/xop-lig.d:
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New.
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* testsuite/gas/i386/i386.exp: Run new tests.
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2020-07-07 Claudiu Zissulescu <claziss@synopsys.com>
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* config/tc-arc.c (find_opcode_match): Add error messages.
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97
gas/testsuite/gas/i386/fma4-lig.d
Normal file
97
gas/testsuite/gas/i386/fma4-lig.d
Normal file
@ -0,0 +1,97 @@
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#as: -mavxscalar=256
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#objdump: -dw
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#name: i386 FMA4 w/ -mavxscalar=256
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#source: fma4.s
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.*: file format .*
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Disassembly of section .text:
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0+ <_start>:
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[ ]*[a-f0-9]+: c4 e3 ed 69 fc 60 vfmaddpd %ymm4,%ymm6,%ymm2,%ymm7
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[ ]*[a-f0-9]+: c4 e3 ed 69 39 60 vfmaddpd \(%ecx\),%ymm6,%ymm2,%ymm7
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[ ]*[a-f0-9]+: c4 e3 ed 68 fc 60 vfmaddps %ymm4,%ymm6,%ymm2,%ymm7
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[ ]*[a-f0-9]+: c4 e3 ed 68 39 60 vfmaddps \(%ecx\),%ymm6,%ymm2,%ymm7
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[ ]*[a-f0-9]+: c4 e3 59 68 6c da 01 30 vfmaddps %xmm3,0x1\(%edx,%ebx,8\),%xmm4,%xmm5
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[ ]*[a-f0-9]+: c4 e3 49 68 8c 81 80 00 00 00 70 vfmaddps %xmm7,0x80\(%ecx,%eax,4\),%xmm6,%xmm1
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[ ]*[a-f0-9]+: c4 e3 ed 5d fc 60 vfmaddsubpd %ymm4,%ymm6,%ymm2,%ymm7
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[ ]*[a-f0-9]+: c4 e3 ed 5d 39 60 vfmaddsubpd \(%ecx\),%ymm6,%ymm2,%ymm7
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[ ]*[a-f0-9]+: c4 e3 ed 5c fc 60 vfmaddsubps %ymm4,%ymm6,%ymm2,%ymm7
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[ ]*[a-f0-9]+: c4 e3 ed 5c 39 60 vfmaddsubps \(%ecx\),%ymm6,%ymm2,%ymm7
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[ ]*[a-f0-9]+: c4 e3 ed 5f fc 60 vfmsubaddpd %ymm4,%ymm6,%ymm2,%ymm7
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[ ]*[a-f0-9]+: c4 e3 ed 5f 39 60 vfmsubaddpd \(%ecx\),%ymm6,%ymm2,%ymm7
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[ ]*[a-f0-9]+: c4 e3 ed 5e fc 60 vfmsubaddps %ymm4,%ymm6,%ymm2,%ymm7
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[ ]*[a-f0-9]+: c4 e3 ed 5e 39 60 vfmsubaddps \(%ecx\),%ymm6,%ymm2,%ymm7
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[ ]*[a-f0-9]+: c4 e3 ed 6d fc 60 vfmsubpd %ymm4,%ymm6,%ymm2,%ymm7
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[ ]*[a-f0-9]+: c4 e3 ed 6d 39 60 vfmsubpd \(%ecx\),%ymm6,%ymm2,%ymm7
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[ ]*[a-f0-9]+: c4 e3 ed 6c fc 60 vfmsubps %ymm4,%ymm6,%ymm2,%ymm7
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[ ]*[a-f0-9]+: c4 e3 ed 6c 39 60 vfmsubps \(%ecx\),%ymm6,%ymm2,%ymm7
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[ ]*[a-f0-9]+: c4 e3 e9 69 fc 60 vfmaddpd %xmm4,%xmm6,%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 e9 69 39 60 vfmaddpd \(%ecx\),%xmm6,%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 69 69 39 40 vfmaddpd %xmm4,\(%ecx\),%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 e9 68 fc 60 vfmaddps %xmm4,%xmm6,%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 e9 68 39 60 vfmaddps \(%ecx\),%xmm6,%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 69 68 39 40 vfmaddps %xmm4,\(%ecx\),%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 e9 5d fc 60 vfmaddsubpd %xmm4,%xmm6,%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 e9 5d 39 60 vfmaddsubpd \(%ecx\),%xmm6,%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 69 5d 39 40 vfmaddsubpd %xmm4,\(%ecx\),%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 e9 5c fc 60 vfmaddsubps %xmm4,%xmm6,%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 e9 5c 39 60 vfmaddsubps \(%ecx\),%xmm6,%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 69 5c 39 40 vfmaddsubps %xmm4,\(%ecx\),%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 e9 5f fc 60 vfmsubaddpd %xmm4,%xmm6,%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 e9 5f 39 60 vfmsubaddpd \(%ecx\),%xmm6,%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 69 5f 39 40 vfmsubaddpd %xmm4,\(%ecx\),%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 e9 5e fc 60 vfmsubaddps %xmm4,%xmm6,%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 e9 5e 39 60 vfmsubaddps \(%ecx\),%xmm6,%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 69 5e 39 40 vfmsubaddps %xmm4,\(%ecx\),%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 e9 6d fc 60 vfmsubpd %xmm4,%xmm6,%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 e9 6d 39 60 vfmsubpd \(%ecx\),%xmm6,%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 69 6d 39 40 vfmsubpd %xmm4,\(%ecx\),%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 e9 6c fc 60 vfmsubps %xmm4,%xmm6,%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 e9 6c 39 60 vfmsubps \(%ecx\),%xmm6,%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 69 6c 39 40 vfmsubps %xmm4,\(%ecx\),%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 ed 6b fc 60 vfmaddsd %xmm4,%xmm6,%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 ed 6b 39 60 vfmaddsd \(%ecx\),%xmm6,%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 6d 6b 39 40 vfmaddsd %xmm4,\(%ecx\),%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 ed 6f fc 60 vfmsubsd %xmm4,%xmm6,%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 ed 6f 39 60 vfmsubsd \(%ecx\),%xmm6,%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 6d 6f 39 40 vfmsubsd %xmm4,\(%ecx\),%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 ed 6a fc 60 vfmaddss %xmm4,%xmm6,%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 ed 6a 39 60 vfmaddss \(%ecx\),%xmm6,%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 6d 6a 39 40 vfmaddss %xmm4,\(%ecx\),%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 ed 6e fc 60 vfmsubss %xmm4,%xmm6,%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 ed 6e 39 60 vfmsubss \(%ecx\),%xmm6,%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 6d 6e 39 40 vfmsubss %xmm4,\(%ecx\),%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 ed 79 fc 60 vfnmaddpd %ymm4,%ymm6,%ymm2,%ymm7
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[ ]*[a-f0-9]+: c4 e3 ed 79 39 60 vfnmaddpd \(%ecx\),%ymm6,%ymm2,%ymm7
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[ ]*[a-f0-9]+: c4 e3 ed 78 fc 60 vfnmaddps %ymm4,%ymm6,%ymm2,%ymm7
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[ ]*[a-f0-9]+: c4 e3 ed 78 39 60 vfnmaddps \(%ecx\),%ymm6,%ymm2,%ymm7
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[ ]*[a-f0-9]+: c4 e3 ed 7d fc 60 vfnmsubpd %ymm4,%ymm6,%ymm2,%ymm7
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[ ]*[a-f0-9]+: c4 e3 ed 7d 39 60 vfnmsubpd \(%ecx\),%ymm6,%ymm2,%ymm7
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[ ]*[a-f0-9]+: c4 e3 ed 7c fc 60 vfnmsubps %ymm4,%ymm6,%ymm2,%ymm7
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[ ]*[a-f0-9]+: c4 e3 ed 7c 39 60 vfnmsubps \(%ecx\),%ymm6,%ymm2,%ymm7
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[ ]*[a-f0-9]+: c4 e3 e9 79 fc 60 vfnmaddpd %xmm4,%xmm6,%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 e9 79 39 60 vfnmaddpd \(%ecx\),%xmm6,%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 69 79 39 40 vfnmaddpd %xmm4,\(%ecx\),%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 e9 78 fc 60 vfnmaddps %xmm4,%xmm6,%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 e9 78 39 60 vfnmaddps \(%ecx\),%xmm6,%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 69 78 39 40 vfnmaddps %xmm4,\(%ecx\),%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 e9 7d fc 60 vfnmsubpd %xmm4,%xmm6,%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 e9 7d 39 60 vfnmsubpd \(%ecx\),%xmm6,%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 69 7d 39 40 vfnmsubpd %xmm4,\(%ecx\),%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 e9 7c fc 60 vfnmsubps %xmm4,%xmm6,%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 e9 7c 39 60 vfnmsubps \(%ecx\),%xmm6,%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 69 7c 39 40 vfnmsubps %xmm4,\(%ecx\),%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 ed 7b fc 60 vfnmaddsd %xmm4,%xmm6,%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 ed 7b 39 60 vfnmaddsd \(%ecx\),%xmm6,%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 6d 7b 39 40 vfnmaddsd %xmm4,\(%ecx\),%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 ed 7f fc 60 vfnmsubsd %xmm4,%xmm6,%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 ed 7f 39 60 vfnmsubsd \(%ecx\),%xmm6,%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 6d 7f 39 40 vfnmsubsd %xmm4,\(%ecx\),%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 ed 7a fc 60 vfnmaddss %xmm4,%xmm6,%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 ed 7a 39 60 vfnmaddss \(%ecx\),%xmm6,%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 6d 7a 39 40 vfnmaddss %xmm4,\(%ecx\),%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 ed 7e fc 60 vfnmsubss %xmm4,%xmm6,%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 ed 7e 39 60 vfnmsubss \(%ecx\),%xmm6,%xmm2,%xmm7
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[ ]*[a-f0-9]+: c4 e3 6d 7e 39 40 vfnmsubss %xmm4,\(%ecx\),%xmm2,%xmm7
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#pass
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@ -302,9 +302,11 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
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run_dump_test "rtm"
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run_dump_test "rtm-intel"
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run_dump_test "fma4"
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run_dump_test "fma4-lig"
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run_dump_test "lwp"
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run_dump_test "lwp-16bit"
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run_dump_test "xop"
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run_dump_test "xop-lig"
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run_dump_test "xop32reg"
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run_dump_test "bmi"
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run_dump_test "bmi-intel"
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5
gas/testsuite/gas/i386/xop-lig.d
Normal file
5
gas/testsuite/gas/i386/xop-lig.d
Normal file
@ -0,0 +1,5 @@
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#as: -mavxscalar=256
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#objdump: -dw
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#name: i386 XOP w/ -mavxscalar=256
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#source: xop.s
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#dump: xop.d
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@ -1,3 +1,15 @@
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2020-07-08 Jan Beulich <jbeulich@suse.com>
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* i386-dis.c (XMVexScalarI4): Define.
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(VEX_LEN_0F3A6A_P_2, VEX_LEN_0F3A6B_P_2, VEX_LEN_0F3A6E_P_2,
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VEX_LEN_0F3A6F_P_2, VEX_LEN_0F3A7A_P_2, VEX_LEN_0F3A7B_P_2,
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VEX_LEN_0F3A7E_P_2, VEX_LEN_0F3A7F_P_2): Delete.
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(vex_len_table): Move scalar FMA4 entries ...
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(prefix_table): ... here.
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(OP_REG_VexI4): Handle scalar_mode.
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* i386-opc.tbl: Use VexLIG for scalar FMA4 insns.
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* i386-tbl.h: Re-generate.
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2020-07-08 Jan Beulich <jbeulich@suse.com>
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* i386-dis.c (OP_Vex_2src_1, OP_Vex_2src_2, Vex_2src_1,
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@ -421,6 +421,7 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
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#define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
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#define XMVexScalar { OP_XMM_Vex, scalar_mode }
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#define XMVexI4 { OP_REG_VexI4, x_mode }
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#define XMVexScalarI4 { OP_REG_VexI4, scalar_mode }
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#define VexI4 { OP_VexI4, 0 }
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#define PCLMUL { PCLMUL_Fixup, 0 }
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#define VCMP { VCMP_Fixup, 0 }
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@ -1788,14 +1789,6 @@ enum
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VEX_LEN_0F3A61_P_2,
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VEX_LEN_0F3A62_P_2,
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VEX_LEN_0F3A63_P_2,
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VEX_LEN_0F3A6A_P_2,
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VEX_LEN_0F3A6B_P_2,
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VEX_LEN_0F3A6E_P_2,
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VEX_LEN_0F3A6F_P_2,
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VEX_LEN_0F3A7A_P_2,
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VEX_LEN_0F3A7B_P_2,
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VEX_LEN_0F3A7E_P_2,
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VEX_LEN_0F3A7F_P_2,
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VEX_LEN_0F3ADF_P_2,
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VEX_LEN_0F3AF0_P_3,
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VEX_LEN_0FXOP_08_CC,
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@ -6512,14 +6505,14 @@ static const struct dis386 prefix_table[][4] = {
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{
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{ Bad_Opcode },
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{ Bad_Opcode },
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{ VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
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{ "vfmaddss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, 0 },
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},
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/* PREFIX_VEX_0F3A6B */
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{
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{ Bad_Opcode },
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{ Bad_Opcode },
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{ VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
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{ "vfmaddsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, 0 },
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},
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/* PREFIX_VEX_0F3A6C */
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@ -6540,14 +6533,14 @@ static const struct dis386 prefix_table[][4] = {
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{
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{ Bad_Opcode },
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{ Bad_Opcode },
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{ VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
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{ "vfmsubss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, 0 },
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},
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/* PREFIX_VEX_0F3A6F */
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{
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{ Bad_Opcode },
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{ Bad_Opcode },
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{ VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
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{ "vfmsubsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, 0 },
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},
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/* PREFIX_VEX_0F3A78 */
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@ -6568,14 +6561,14 @@ static const struct dis386 prefix_table[][4] = {
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{
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{ Bad_Opcode },
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{ Bad_Opcode },
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{ VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
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{ "vfnmaddss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, 0 },
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},
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/* PREFIX_VEX_0F3A7B */
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{
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{ Bad_Opcode },
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{ Bad_Opcode },
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{ VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
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{ "vfnmaddsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, 0 },
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},
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/* PREFIX_VEX_0F3A7C */
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@ -6597,14 +6590,14 @@ static const struct dis386 prefix_table[][4] = {
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{
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{ Bad_Opcode },
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{ Bad_Opcode },
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{ VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
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{ "vfnmsubss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, 0 },
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},
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/* PREFIX_VEX_0F3A7F */
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{
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{ Bad_Opcode },
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{ Bad_Opcode },
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{ VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
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{ "vfnmsubsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, 0 },
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},
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/* PREFIX_VEX_0F3ACE */
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@ -9620,46 +9613,6 @@ static const struct dis386 vex_len_table[][2] = {
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{ "vpcmpistri", { XM, EXx, Ib }, 0 },
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},
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/* VEX_LEN_0F3A6A_P_2 */
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{
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{ "vfmaddss", { XMScalar, VexScalar, EXxmm_md, XMVexI4 }, 0 },
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},
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/* VEX_LEN_0F3A6B_P_2 */
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{
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{ "vfmaddsd", { XMScalar, VexScalar, EXxmm_mq, XMVexI4 }, 0 },
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},
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/* VEX_LEN_0F3A6E_P_2 */
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{
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{ "vfmsubss", { XMScalar, VexScalar, EXxmm_md, XMVexI4 }, 0 },
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},
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/* VEX_LEN_0F3A6F_P_2 */
|
||||
{
|
||||
{ "vfmsubsd", { XMScalar, VexScalar, EXxmm_mq, XMVexI4 }, 0 },
|
||||
},
|
||||
|
||||
/* VEX_LEN_0F3A7A_P_2 */
|
||||
{
|
||||
{ "vfnmaddss", { XMScalar, VexScalar, EXxmm_md, XMVexI4 }, 0 },
|
||||
},
|
||||
|
||||
/* VEX_LEN_0F3A7B_P_2 */
|
||||
{
|
||||
{ "vfnmaddsd", { XMScalar, VexScalar, EXxmm_mq, XMVexI4 }, 0 },
|
||||
},
|
||||
|
||||
/* VEX_LEN_0F3A7E_P_2 */
|
||||
{
|
||||
{ "vfnmsubss", { XMScalar, VexScalar, EXxmm_md, XMVexI4 }, 0 },
|
||||
},
|
||||
|
||||
/* VEX_LEN_0F3A7F_P_2 */
|
||||
{
|
||||
{ "vfnmsubsd", { XMScalar, VexScalar, EXxmm_mq, XMVexI4 }, 0 },
|
||||
},
|
||||
|
||||
/* VEX_LEN_0F3ADF_P_2 */
|
||||
{
|
||||
{ "vaeskeygenassist", { XM, EXx, Ib }, 0 },
|
||||
@ -15865,29 +15818,21 @@ static void
|
||||
OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
|
||||
{
|
||||
int reg;
|
||||
const char **names;
|
||||
const char **names = names_xmm;
|
||||
|
||||
FETCH_DATA (the_info, codep + 1);
|
||||
reg = *codep++;
|
||||
|
||||
if (bytemode != x_mode)
|
||||
if (bytemode != x_mode && bytemode != scalar_mode)
|
||||
abort ();
|
||||
|
||||
reg >>= 4;
|
||||
if (address_mode != mode_64bit)
|
||||
reg &= 7;
|
||||
|
||||
switch (vex.length)
|
||||
{
|
||||
case 128:
|
||||
names = names_xmm;
|
||||
break;
|
||||
case 256:
|
||||
names = names_ymm;
|
||||
break;
|
||||
default:
|
||||
abort ();
|
||||
}
|
||||
if (bytemode == x_mode && vex.length == 256)
|
||||
names = names_ymm;
|
||||
|
||||
oappend (names[reg]);
|
||||
|
||||
if (vex.w)
|
||||
|
||||
@ -2335,10 +2335,10 @@ vfmaddpd, 4, 0x6669, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=2|Ve
|
||||
vfmaddpd, 4, 0x6669, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
|
||||
vfmaddps, 4, 0x6668, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=2|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
|
||||
vfmaddps, 4, 0x6668, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
|
||||
vfmaddsd, 4, 0x666b, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV|VexW1|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM }
|
||||
vfmaddsd, 4, 0x666b, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV|VexW0|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
|
||||
vfmaddss, 4, 0x666a, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV|VexW1|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM }
|
||||
vfmaddss, 4, 0x666a, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV|VexW0|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
|
||||
vfmaddsd, 4, 0x666b, None, 1, CpuFMA4, Modrm|VexLIG|VexOpcode=2|VexVVVV|VexW1|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM }
|
||||
vfmaddsd, 4, 0x666b, None, 1, CpuFMA4, Modrm|VexLIG|VexOpcode=2|VexVVVV|VexW0|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
|
||||
vfmaddss, 4, 0x666a, None, 1, CpuFMA4, Modrm|VexLIG|VexOpcode=2|VexVVVV|VexW1|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM }
|
||||
vfmaddss, 4, 0x666a, None, 1, CpuFMA4, Modrm|VexLIG|VexOpcode=2|VexVVVV|VexW0|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
|
||||
vfmaddsubpd, 4, 0x665d, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=2|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
|
||||
vfmaddsubpd, 4, 0x665d, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
|
||||
vfmaddsubps, 4, 0x665c, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=2|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
|
||||
@ -2351,26 +2351,26 @@ vfmsubpd, 4, 0x666d, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=2|Ve
|
||||
vfmsubpd, 4, 0x666d, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
|
||||
vfmsubps, 4, 0x666c, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=2|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
|
||||
vfmsubps, 4, 0x666c, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
|
||||
vfmsubsd, 4, 0x666f, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV|VexW1|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM }
|
||||
vfmsubsd, 4, 0x666f, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV|VexW0|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
|
||||
vfmsubss, 4, 0x666e, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV|VexW1|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM }
|
||||
vfmsubss, 4, 0x666e, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV|VexW0|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
|
||||
vfmsubsd, 4, 0x666f, None, 1, CpuFMA4, Modrm|VexLIG|VexOpcode=2|VexVVVV|VexW1|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM }
|
||||
vfmsubsd, 4, 0x666f, None, 1, CpuFMA4, Modrm|VexLIG|VexOpcode=2|VexVVVV|VexW0|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
|
||||
vfmsubss, 4, 0x666e, None, 1, CpuFMA4, Modrm|VexLIG|VexOpcode=2|VexVVVV|VexW1|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM }
|
||||
vfmsubss, 4, 0x666e, None, 1, CpuFMA4, Modrm|VexLIG|VexOpcode=2|VexVVVV|VexW0|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
|
||||
vfnmaddpd, 4, 0x6679, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=2|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
|
||||
vfnmaddpd, 4, 0x6679, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
|
||||
vfnmaddps, 4, 0x6678, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=2|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
|
||||
vfnmaddps, 4, 0x6678, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
|
||||
vfnmaddsd, 4, 0x667b, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV|VexW1|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM }
|
||||
vfnmaddsd, 4, 0x667b, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV|VexW0|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
|
||||
vfnmaddss, 4, 0x667a, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV|VexW1|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM }
|
||||
vfnmaddss, 4, 0x667a, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV|VexW0|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
|
||||
vfnmaddsd, 4, 0x667b, None, 1, CpuFMA4, Modrm|VexLIG|VexOpcode=2|VexVVVV|VexW1|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM }
|
||||
vfnmaddsd, 4, 0x667b, None, 1, CpuFMA4, Modrm|VexLIG|VexOpcode=2|VexVVVV|VexW0|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
|
||||
vfnmaddss, 4, 0x667a, None, 1, CpuFMA4, Modrm|VexLIG|VexOpcode=2|VexVVVV|VexW1|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM }
|
||||
vfnmaddss, 4, 0x667a, None, 1, CpuFMA4, Modrm|VexLIG|VexOpcode=2|VexVVVV|VexW0|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
|
||||
vfnmsubpd, 4, 0x667d, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=2|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
|
||||
vfnmsubpd, 4, 0x667d, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
|
||||
vfnmsubps, 4, 0x667c, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=2|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
|
||||
vfnmsubps, 4, 0x667c, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
|
||||
vfnmsubsd, 4, 0x667f, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV|VexW1|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM }
|
||||
vfnmsubsd, 4, 0x667f, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV|VexW0|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
|
||||
vfnmsubss, 4, 0x667e, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV|VexW1|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM }
|
||||
vfnmsubss, 4, 0x667e, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV|VexW0|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
|
||||
vfnmsubsd, 4, 0x667f, None, 1, CpuFMA4, Modrm|VexLIG|VexOpcode=2|VexVVVV|VexW1|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM }
|
||||
vfnmsubsd, 4, 0x667f, None, 1, CpuFMA4, Modrm|VexLIG|VexOpcode=2|VexVVVV|VexW0|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
|
||||
vfnmsubss, 4, 0x667e, None, 1, CpuFMA4, Modrm|VexLIG|VexOpcode=2|VexVVVV|VexW1|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM }
|
||||
vfnmsubss, 4, 0x667e, None, 1, CpuFMA4, Modrm|VexLIG|VexOpcode=2|VexVVVV|VexW0|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
|
||||
|
||||
// XOP instructions
|
||||
|
||||
|
||||
@ -45978,7 +45978,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 2, 2, 2, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 1, 2, 2, 2, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 1,
|
||||
0, 1, 0, 0, 1, 0 } },
|
||||
@ -45996,7 +45996,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 2, 2, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 1, 1, 2, 2, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 1, 0, 0, 0, 0 } },
|
||||
@ -46014,7 +46014,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 2, 2, 2, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 1, 2, 2, 2, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, 1, 0, 0,
|
||||
0, 1, 0, 0, 1, 0 } },
|
||||
@ -46032,7 +46032,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 2, 2, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 1, 1, 2, 2, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 1, 0, 0, 0, 0 } },
|
||||
@ -46266,7 +46266,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 2, 2, 2, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 1, 2, 2, 2, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 1,
|
||||
0, 1, 0, 0, 1, 0 } },
|
||||
@ -46284,7 +46284,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 2, 2, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 1, 1, 2, 2, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 1, 0, 0, 0, 0 } },
|
||||
@ -46302,7 +46302,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 2, 2, 2, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 1, 2, 2, 2, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, 1, 0, 0,
|
||||
0, 1, 0, 0, 1, 0 } },
|
||||
@ -46320,7 +46320,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 2, 2, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 1, 1, 2, 2, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 1, 0, 0, 0, 0 } },
|
||||
@ -46410,7 +46410,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 2, 2, 2, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 1, 2, 2, 2, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 1,
|
||||
0, 1, 0, 0, 1, 0 } },
|
||||
@ -46428,7 +46428,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 2, 2, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 1, 1, 2, 2, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 1, 0, 0, 0, 0 } },
|
||||
@ -46446,7 +46446,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 2, 2, 2, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 1, 2, 2, 2, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, 1, 0, 0,
|
||||
0, 1, 0, 0, 1, 0 } },
|
||||
@ -46464,7 +46464,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 2, 2, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 1, 1, 2, 2, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 1, 0, 0, 0, 0 } },
|
||||
@ -46554,7 +46554,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 2, 2, 2, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 1, 2, 2, 2, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 1,
|
||||
0, 1, 0, 0, 1, 0 } },
|
||||
@ -46572,7 +46572,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 2, 2, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 1, 1, 2, 2, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 1, 0, 0, 0, 0 } },
|
||||
@ -46590,7 +46590,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 2, 2, 2, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 1, 2, 2, 2, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, 1, 0, 0,
|
||||
0, 1, 0, 0, 1, 0 } },
|
||||
@ -46608,7 +46608,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 2, 2, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 1, 1, 2, 2, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 1, 0, 0, 0, 0 } },
|
||||
|
||||
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Reference in New Issue
Block a user