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Add support for AArch64 system register names IP0, IP1, FP and LR.
* config/tc-aarch64.c (reg_entry_reg_names): Add IP0, IP1, FP, and LR as register aliases of register 16, 17, 29 and 30 respectively. * testsuite/gas/aarch64/diagnostic.l: Remove diagnostic prohibiting register 'lr' which is now an alias. * testsuite/gas/aarch64/diagnostic.s: Remove instruction utilizing register 'lr' which is now an alias.
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@ -1,3 +1,13 @@
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2017-06-07 Michael Collison <michael.collison@arm.com>
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* config/tc-aarch64.c (reg_entry_reg_names): Add IP0,
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IP1, FP, and LR as register aliases of register 16, 17, 29
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and 30 respectively.
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* testsuite/gas/aarch64/diagnostic.l: Remove diagnostic
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prohibiting register 'lr' which is now an alias.
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* testsuite/gas/aarch64/diagnostic.s: Remove instruction
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utilizing register 'lr' which is now an alias.
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2017-06-06 Jiong Wang <jiong.wang@arm.com>
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* config/tc-arm.c (reject_bad_reg): Allow REG_SP on ARMv8-A.
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@ -6797,6 +6797,11 @@ static const reg_entry reg_names[] = {
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REGDEF (wzr, 31, Z_32), REGDEF (WZR, 31, Z_32),
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REGDEF (xzr, 31, Z_64), REGDEF (XZR, 31, Z_64),
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REGDEF (ip0, 16, R_64), REGDEF (IP0, 16, R_64),
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REGDEF (ip1, 17, R_64), REGDEF (IP1, 17, R_64),
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REGDEF (fp, 29, R_64), REGDEF (FP, 29, R_64),
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REGDEF (lr, 30, R_64), REGDEF (LR, 30, R_64),
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/* Floating-point single precision registers. */
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REGSET (s, FP_S), REGSET (S, FP_S),
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@ -98,7 +98,6 @@
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[^:]*:100: Error: operand 3 must be one of the standard conditions, excluding AL and NV. -- `cinc w0,w1,nv'
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[^:]*:101: Error: operand 2 must be one of the standard conditions, excluding AL and NV. -- `cset w0,al'
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[^:]*:102: Error: operand 2 must be one of the standard conditions, excluding AL and NV. -- `cset w0,nv'
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[^:]*:105: Error: operand 1 must be an integer register -- `ret lr'
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[^:]*:106: Error: operand 1 must be an integer register -- `ret kk'
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[^:]*:107: Error: immediate operand required at operand 1 -- `clrex x0'
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[^:]*:108: Error: immediate operand required at operand 1 -- `clrex w0'
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@ -102,7 +102,7 @@
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cset w0, nv
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# test diagnostic info on optional operand
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ret lr
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ret kk
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clrex x0
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clrex w0
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