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aarch64: Add LSE128 instruction operand support

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Given the particular encoding of the LSE128 instructions, create the
necessary shared input+output operand register description and
handling in the code to allow for the encoding of the LSE128 128-bit
atomic operations.

gas/ChangeLog:

	* config/tc-aarch64.c (parse_operands):

include/ChangeLog:

	* opcode/aarch64.h (enum aarch64_opnd):

opcodes/ChangeLog:

	* aarch64-opc.c (fields):
	(aarch64_print_operand):
	* aarch64-opc.h (enum aarch64_field_kind):
	* aarch64-tbl.h (AARCH64_OPERANDS):
This commit is contained in:
Victor Do Nascimento 2023-10-30 11:47:23 +00:00
parent ecd4c78ddd
commit 6219f9dae7
5 changed files with 15 additions and 0 deletions
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5
gas/config/tc-aarch64.c
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@ -7863,6 +7863,11 @@ parse_operands (char *str, const aarch64_opcode *opcode)
po_char_or_fail ('!');
break;
case AARCH64_OPND_LSE128_Rt:
case AARCH64_OPND_LSE128_Rt2:
po_int_fp_reg_or_fail (REG_TYPE_R_64);
break;
default:
as_fatal (_("unhandled operand code %d"), operands[i]);
}

2
include/opcode/aarch64.h
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@ -521,6 +521,8 @@ enum aarch64_opnd
AARCH64_OPND_BARRIER_PSB, /* Barrier operand for PSB. */
AARCH64_OPND_BARRIER_GCSB, /* Barrier operand for GCSB. */
AARCH64_OPND_BTI_TARGET, /* BTI {<target>}. */
AARCH64_OPND_LSE128_Rt, /* LSE128 <Xt1>. */
AARCH64_OPND_LSE128_Rt2, /* LSE128 <Xt2>. */
AARCH64_OPND_SVE_ADDR_RI_S4x16, /* SVE [<Xn|SP>, #<simm4>*16]. */
AARCH64_OPND_SVE_ADDR_RI_S4x32, /* SVE [<Xn|SP>, #<simm4>*32]. */
AARCH64_OPND_SVE_ADDR_RI_S4xVL, /* SVE [<Xn|SP>, #<simm4>, MUL VL]. */

4
opcodes/aarch64-opc.c
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@ -226,6 +226,8 @@ const aarch64_field fields[] =
{ 10, 8 }, /* CSSC_imm8. */
{ 11, 1 }, /* H: in advsimd scalar x indexed element instructions. */
{ 21, 1 }, /* L: in advsimd scalar x indexed element instructions. */
{ 0, 5 }, /* LSE128_Rt: Shared input+output operand register. */
{ 16, 5 }, /* LSE128_Rt2: Shared input+output operand register 2. */
{ 20, 1 }, /* M: in advsimd scalar x indexed element instructions. */
{ 22, 1 }, /* N: in logical (immediate) instructions. */
{ 30, 1 }, /* Q: in most AdvSIMD instructions. */
@ -3770,6 +3772,8 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
case AARCH64_OPND_Rt_SYS:
case AARCH64_OPND_PAIRREG:
case AARCH64_OPND_SVE_Rm:
case AARCH64_OPND_LSE128_Rt:
case AARCH64_OPND_LSE128_Rt2:
/* The optional-ness of <Xt> in e.g. IC <ic_op>{, <Xt>} is determined by
the <ic_op>, therefore we use opnd->present to override the
generic optional-ness information. */

2
opcodes/aarch64-opc.h
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@ -36,6 +36,8 @@ enum aarch64_field_kind
FLD_CSSC_imm8,
FLD_H,
FLD_L,
FLD_LSE128_Rt,
FLD_LSE128_Rt2,
FLD_M,
FLD_N,
FLD_Q,

2
opcodes/aarch64-tbl.h
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@ -6308,6 +6308,8 @@ const struct aarch64_opcode aarch64_opcode_table[] =
"the GCSB option name DSYNC") \
Y(SYSTEM, hint, "BTI_TARGET", 0, F (), \
"BTI targets j/c/jc") \
Y(INT_REG, regno, "LSE128_Rt", 0, F(FLD_LSE128_Rt), "an integer register") \
Y(INT_REG, regno, "LSE128_Rt2", 0, F(FLD_LSE128_Rt2), "an integer register") \
Y(ADDRESS, sve_addr_ri_s4, "SVE_ADDR_RI_S4x16", \
4 << OPD_F_OD_LSB, F(FLD_Rn), \
"an address with a 4-bit signed offset, multiplied by 16") \