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sim: mcore: invert sim_cpu storage
This commit is contained in:
Mike Frysinger
parent
6a08ae198b
commit
620dd532fe
@ -98,8 +98,8 @@ mcore_store_unsigned_integer (unsigned char *addr, int len, unsigned long val)
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static int memcycles = 1;
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#define gr cpu->active_gregs
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#define cr cpu->regs.cregs
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#define gr MCORE_SIM_CPU (cpu)->active_gregs
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#define cr MCORE_SIM_CPU (cpu)->regs.cregs
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#define sr cr[0]
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#define vbr cr[1]
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#define esr cr[2]
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@ -125,10 +125,12 @@ static int memcycles = 1;
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#define SR_AF() ((sr >> 1) & 1)
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static void set_active_regs (SIM_CPU *cpu)
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{
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struct mcore_sim_cpu *mcore_cpu = MCORE_SIM_CPU (cpu);
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if (SR_AF())
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cpu->active_gregs = cpu->regs.alt_gregs;
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mcore_cpu->active_gregs = mcore_cpu->regs.alt_gregs;
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else
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cpu->active_gregs = cpu->regs.gregs;
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mcore_cpu->active_gregs = mcore_cpu->regs.gregs;
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}
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#define TRAPCODE 1 /* r1 holds which function we want */
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@ -144,13 +146,15 @@ static void set_active_regs (SIM_CPU *cpu)
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static void
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set_initial_gprs (SIM_CPU *cpu)
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{
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struct mcore_sim_cpu *mcore_cpu = MCORE_SIM_CPU (cpu);
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/* Set up machine just out of reset. */
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CPU_PC_SET (cpu, 0);
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sr = 0;
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/* Clean out the GPRs and alternate GPRs. */
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memset (&cpu->regs.gregs, 0, sizeof(cpu->regs.gregs));
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memset (&cpu->regs.alt_gregs, 0, sizeof(cpu->regs.alt_gregs));
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memset (&mcore_cpu->regs.gregs, 0, sizeof(mcore_cpu->regs.gregs));
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memset (&mcore_cpu->regs.alt_gregs, 0, sizeof(mcore_cpu->regs.alt_gregs));
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/* Make our register set point to the right place. */
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set_active_regs (cpu);
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@ -203,10 +207,12 @@ process_stub (SIM_DESC sd, SIM_CPU *cpu, int what)
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static void
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util (SIM_DESC sd, SIM_CPU *cpu, unsigned what)
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{
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struct mcore_sim_cpu *mcore_cpu = MCORE_SIM_CPU (cpu);
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switch (what)
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{
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case 0: /* exit */
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sim_engine_halt (sd, cpu, NULL, cpu->regs.pc, sim_exited, gr[PARM1]);
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sim_engine_halt (sd, cpu, NULL, mcore_cpu->regs.pc, sim_exited, gr[PARM1]);
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break;
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case 1: /* printf */
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@ -220,7 +226,7 @@ util (SIM_DESC sd, SIM_CPU *cpu, unsigned what)
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break;
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case 3: /* utime */
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gr[RET1] = cpu->insts;
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gr[RET1] = mcore_cpu->insts;
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break;
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case 0xFF:
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@ -287,6 +293,7 @@ static int tracing = 0;
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static void
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step_once (SIM_DESC sd, SIM_CPU *cpu)
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{
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struct mcore_sim_cpu *mcore_cpu = MCORE_SIM_CPU (cpu);
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int needfetch;
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word ibuf;
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word pc;
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@ -349,7 +356,7 @@ step_once (SIM_DESC sd, SIM_CPU *cpu)
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if ((WLincyc == 1) && (pc == WLendpc))
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{
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cycs = (cpu->cycles + (insts + bonus_cycles +
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cycs = (mcore_cpu->cycles + (insts + bonus_cycles +
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(memops * memcycles)) - WLbcyc);
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if (WLcnts[WLW] == 1)
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@ -384,7 +391,7 @@ step_once (SIM_DESC sd, SIM_CPU *cpu)
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if (pc == WL[w])
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{
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WLcnts[w]++;
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WLbcyc = cpu->cycles + insts
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WLbcyc = mcore_cpu->cycles + insts
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+ bonus_cycles + (memops * memcycles);
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WLendpc = gr[15];
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WLincyc = 1;
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@ -1215,10 +1222,10 @@ step_once (SIM_DESC sd, SIM_CPU *cpu)
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/* Hide away the things we've cached while executing. */
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CPU_PC_SET (cpu, pc);
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cpu->insts += insts; /* instructions done ... */
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cpu->cycles += insts; /* and each takes a cycle */
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cpu->cycles += bonus_cycles; /* and extra cycles for branches */
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cpu->cycles += memops * memcycles; /* and memop cycle delays */
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mcore_cpu->insts += insts; /* instructions done ... */
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mcore_cpu->cycles += insts; /* and each takes a cycle */
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mcore_cpu->cycles += bonus_cycles; /* and extra cycles for branches */
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mcore_cpu->cycles += memops * memcycles; /* and memop cycle delays */
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}
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void
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@ -1244,6 +1251,8 @@ sim_engine_run (SIM_DESC sd,
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static int
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mcore_reg_store (SIM_CPU *cpu, int rn, const void *memory, int length)
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{
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struct mcore_sim_cpu *mcore_cpu = MCORE_SIM_CPU (cpu);
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if (rn < NUM_MCORE_REGS && rn >= 0)
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{
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if (length == 4)
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@ -1252,7 +1261,7 @@ mcore_reg_store (SIM_CPU *cpu, int rn, const void *memory, int length)
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/* misalignment safe */
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ival = mcore_extract_unsigned_integer (memory, 4);
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cpu->asints[rn] = ival;
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mcore_cpu->asints[rn] = ival;
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}
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return 4;
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@ -1264,11 +1273,13 @@ mcore_reg_store (SIM_CPU *cpu, int rn, const void *memory, int length)
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static int
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mcore_reg_fetch (SIM_CPU *cpu, int rn, void *memory, int length)
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{
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struct mcore_sim_cpu *mcore_cpu = MCORE_SIM_CPU (cpu);
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if (rn < NUM_MCORE_REGS && rn >= 0)
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{
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if (length == 4)
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{
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long ival = cpu->asints[rn];
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long ival = mcore_cpu->asints[rn];
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/* misalignment-safe */
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mcore_store_unsigned_integer (memory, 4, ival);
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@ -1284,18 +1295,19 @@ void
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sim_info (SIM_DESC sd, int verbose)
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{
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SIM_CPU *cpu = STATE_CPU (sd, 0);
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struct mcore_sim_cpu *mcore_cpu = MCORE_SIM_CPU (cpu);
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#ifdef WATCHFUNCTIONS
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int w, wcyc;
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#endif
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double virttime = cpu->cycles / 36.0e6;
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double virttime = mcore_cpu->cycles / 36.0e6;
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host_callback *callback = STATE_CALLBACK (sd);
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callback->printf_filtered (callback, "\n\n# instructions executed %10d\n",
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cpu->insts);
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mcore_cpu->insts);
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callback->printf_filtered (callback, "# cycles %10d\n",
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cpu->cycles);
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mcore_cpu->cycles);
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callback->printf_filtered (callback, "# pipeline stalls %10d\n",
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cpu->stalls);
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mcore_cpu->stalls);
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callback->printf_filtered (callback, "# virtual time taken %10.4f\n",
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virttime);
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@ -1326,13 +1338,13 @@ sim_info (SIM_DESC sd, int verbose)
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static sim_cia
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mcore_pc_get (sim_cpu *cpu)
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{
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return cpu->regs.pc;
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return MCORE_SIM_CPU (cpu)->regs.pc;
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}
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static void
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mcore_pc_set (sim_cpu *cpu, sim_cia pc)
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{
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cpu->regs.pc = pc;
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MCORE_SIM_CPU (cpu)->regs.pc = pc;
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}
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static void
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@ -1356,7 +1368,8 @@ sim_open (SIM_OPEN_KIND kind, host_callback *cb,
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cb->syscall_map = cb_mcore_syscall_map;
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/* The cpu data is kept in a separately allocated chunk of memory. */
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if (sim_cpu_alloc_all (sd, 1) != SIM_RC_OK)
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if (sim_cpu_alloc_all_extra (sd, 1, sizeof (struct mcore_sim_cpu))
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!= SIM_RC_OK)
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{
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free_state (sd);
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return 0;
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@ -19,6 +19,8 @@ along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#ifndef SIM_MAIN_H
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#define SIM_MAIN_H
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#define SIM_HAVE_COMMON_SIM_CPU
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#include "sim-basics.h"
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typedef long int word;
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@ -48,8 +50,7 @@ struct mcore_regset
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#define LAST_VALID_CREG 32 /* only 0..12 implemented */
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#define NUM_MCORE_REGS (16 + 16 + LAST_VALID_CREG + 1)
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struct _sim_cpu {
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struct mcore_sim_cpu {
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union
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{
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struct mcore_regset regs;
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@ -64,9 +65,9 @@ struct _sim_cpu {
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int stalls;
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int cycles;
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int insts;
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sim_cpu_base base;
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};
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#define MCORE_SIM_CPU(cpu) ((struct mcore_sim_cpu *) CPU_ARCH_DATA (cpu))
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#endif
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