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e200 LSP support

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It has bothered me for a long time that we have disabled LSP (and SPE)
tests.  Also the LSP test comment indicating there is something wrong
with get_powerpc_dialect.  I don't think there is.  Decoding of a VLE
instruction depends on whether the processor is in VLE mode (some
processors support both VLE and standard PPC) which we flag per
section with SHF_PPC_VLE for decoding when disassembling.

Background: Some versions of powerpc e200 have "Lightweight Signal
Processing" support, examples being e200z215 and e200z425.  As far as
I can tell, LSP and SPE are mutually exclusive.  This seems to be
borne out by insn encoding, for example LSP "zvaddih" and SPE "evaddw"
have the same encoding.  So none of the processor descriptions in
ppc_opts ought to have both PPC_OPCODE_LSP and PPC_OPCODE_SPE/2, if we
want disassembly to work.  I also could not find anything to suggest
that the LSP insns are enabled only in VLE mode, which means the LSP
insns should not be in vle_opcodes.

Fix all this by moving the LSP insns to their own table, and add a new
e200z2 cpu entry with LSP support, removing LSP from -me200z4 and from
-mvle.  (Yes, I know, as I said above some of the e200z4 processors
have LSP.  Others have SPE.  It's hard to choose good options.  Think
of z2 as meaning earlier, z4 as later.)  Also add -mlsp to allow
adding the LSP insn set.

include/
	* opcode/ppc.h (lsp_opcodes, lsp_num_opcodes): Declare.
	(LSP_OP_TO_SEG): Define.
binutils/
	* doc/binutils.texi: Update ppc docs.
gas/
	* config/tc-ppc.c (ppc_setup_opcodes): Add lsp opcodes to ppc_hash.
	* doc/c-ppc.texi: Document e200 and lsp.
	* testsuite/gas/ppc/lsp-checks.d: Assemble with -me200z2.
	* testsuite/gas/ppc/lsp.d: Likewise, disassembly too.
	* testsuite/gas/ppc/ppc.exp: Don't xfail lsp test.
opcodes/
	* ppc-dis.c (ppc_opts): Add e200z2 and lsp.  Don't set
	PPC_OPCODE_LSP for e200z4 or vle.
	(ppc_parse_cpu): Mutually exclude LSP and SPE.
	(LSP_OPCD_SEGS): Define.
	(lsp_opcd_indices): New array.
	(disassemble_init_powerpc): Init lsp_opcd_indices.
	(lookup_lsp): New function.
	(print_insn_powerpc): Call it.
	* ppc-opc.c: Include libiberty.h for ARRAY_SIZE and use throughout.
	(vle_opcodes): Move LSP opcodes to..
	(lsp_opcodes): ..here, and sort.
	(lsp_num_opcodes): New.
This commit is contained in:
Alan Modra 2022-10-13 08:46:28 +10:30
parent d12f8998d2
commit 61a457e5da
9 changed files with 459 additions and 353 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
binutils/doc/binutils.texi
View File

@ -2632,7 +2632,7 @@ rather than @code{li}. All of the @option{-m} arguments for
@option{601}, @option{603}, @option{604}, @option{620}, @option{7400},
@option{7410}, @option{7450}, @option{7455}, @option{750cl},
@option{821}, @option{850}, @option{860}, @option{a2}, @option{booke},
@option{booke32}, @option{cell}, @option{com}, @option{e200z4},
@option{booke32}, @option{cell}, @option{com}, @option{e200z2}, @option{e200z4},
@option{e300}, @option{e500}, @option{e500mc}, @option{e500mc64},
@option{e500x2}, @option{e5500}, @option{e6500}, @option{efs},
@option{power4}, @option{power5}, @option{power6}, @option{power7},
@ -2643,9 +2643,10 @@ rather than @code{li}. All of the @option{-m} arguments for
@option{pwrx}, @option{titan}, @option{vle}, and @option{future}.
@option{32} and @option{64} modify the default or a prior CPU
selection, disabling and enabling 64-bit insns respectively. In
addition, @option{altivec}, @option{any}, @option{htm}, @option{vsx},
and @option{spe} add capabilities to a previous @emph{or later} CPU
selection. @option{any} will disassemble any opcode known to
addition, @option{altivec}, @option{any}, @option{lsp}, @option{htm},
@option{vsx}, @option{spe} and @option{spe2} add capabilities to a
previous @emph{or later} CPU selection.
@option{any} will disassemble any opcode known to
binutils, but in cases where an opcode has two different meanings or
different arguments, you may not see the disassembly you expect.
If you disassemble without giving a CPU selection, a default will be

24
gas/config/tc-ppc.c
View File

@ -1810,6 +1810,30 @@ ppc_setup_opcodes (void)
}
}
/* LSP instructions */
if ((ppc_cpu & PPC_OPCODE_LSP) != 0)
{
unsigned int prev_seg = 0;
unsigned int seg;
op_end = lsp_opcodes + lsp_num_opcodes;
for (op = lsp_opcodes; op < op_end; op++)
{
if (ENABLE_CHECKING)
{
seg = LSP_OP_TO_SEG (op->opcode);
if (seg < prev_seg)
{
as_bad (_("opcode is not sorted for %s"), op->name);
bad_insn = true;
}
prev_seg = seg;
bad_insn |= insn_validate (op);
}
str_hash_insert (ppc_hash, op->name, op, 0);
}
}
/* SPE2 instructions */
if ((ppc_cpu & PPC_OPCODE_SPE2) == PPC_OPCODE_SPE2)
{

16
gas/doc/c-ppc.texi
View File

@ -81,6 +81,12 @@ Generate code for PowerPC 821/850/860.
@item -mppc64, -m620
Generate code for PowerPC 620/625/630.
@item -me200z2, -me200z4
Generate code for e200 variants, e200z2 with LSP, e200z4 with SPE.
@item -me300
Generate code for PowerPC e300 family.
@item -me500, -me500x2
Generate code for Motorola e500 core complex.
@ -96,11 +102,14 @@ Generate code for Freescale e5500 core complex.
@item -me6500
Generate code for Freescale e6500 core complex.
@item -mlsp
Enable LSP instructions. (Disables SPE and SPE2.)
@item -mspe
Generate code for Motorola SPE instructions.
Generate code for Motorola SPE instructions. (Disables LSP.)
@item -mspe2
Generate code for Freescale SPE2 instructions.
Generate code for Freescale SPE2 instructions. (Disables LSP.)
@item -mtitan
Generate code for AppliedMicro Titan core complex.
@ -114,9 +123,6 @@ Generate code for 32-bit BookE.
@item -ma2
Generate code for A2 architecture.
@item -me300
Generate code for PowerPC e300 family.
@item -maltivec
Generate code for processors with AltiVec instructions.

2
gas/testsuite/gas/ppc/lsp-checks.d
View File

@ -1,3 +1,3 @@
#name: Test LSP operands checks
#as: -a32 -mbig -mvle
#as: -a32 -mbig -me200z2
#error_output: lsp-checks.l

4
gas/testsuite/gas/ppc/lsp.d
View File

@ -1,5 +1,5 @@
#as: -a32 -mbig -mvle
#objdump: -d -Mvle
#as: -a32 -mbig -me200z2
#objdump: -d -Me200z2
#name: Validate LSP instructions
.*: +file format elf.*-powerpc.*

4
gas/testsuite/gas/ppc/ppc.exp
View File

@ -87,11 +87,7 @@ run_dump_test "vle-simple-4"
run_dump_test "vle-simple-5"
run_dump_test "vle-simple-6"
run_dump_test "vle-mult-ld-st-insns"
#fail expected until get_powerpc_dialect() patch not applied
setup_xfail "*-*-*"
run_dump_test "lsp"
run_dump_test "lsp-checks"
run_dump_test "efs"
run_dump_test "efs2"

5
include/opcode/ppc.h
View File

@ -78,6 +78,8 @@ extern const struct powerpc_opcode prefix_opcodes[];
extern const unsigned int prefix_num_opcodes;
extern const struct powerpc_opcode vle_opcodes[];
extern const unsigned int vle_num_opcodes;
extern const struct powerpc_opcode lsp_opcodes[];
extern const unsigned int lsp_num_opcodes;
extern const struct powerpc_opcode spe2_opcodes[];
extern const unsigned int spe2_num_opcodes;
@ -255,6 +257,9 @@ extern const unsigned int spe2_num_opcodes;
/* A macro to convert a VLE opcode to a VLE opcode segment. */
#define VLE_OP_TO_SEG(i) ((i) >> 1)
/* Map LSP insn to lookup segment for disassembly. */
#define LSP_OP_TO_SEG(i) (((i) & 0x7ff) >> 6)
/* A macro to extract the extended opcode from a SPE2 instruction. */
#define SPE2_XOP(i) ((i) & 0x7ff)

84
opcodes/ppc-dis.c
View File

@ -131,11 +131,17 @@ struct ppc_mopt ppc_opts[] = {
0 },
{ "com", PPC_OPCODE_COMMON,
0 },
{ "e200z4", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE| PPC_OPCODE_SPE
{ "e200z2", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_LSP
| PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
| PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
| PPC_OPCODE_E500 | PPC_OPCODE_VLE | PPC_OPCODE_E200Z4
| PPC_OPCODE_EFS2 | PPC_OPCODE_LSP),
| PPC_OPCODE_EFS2),
0 },
{ "e200z4", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
| PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
| PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
| PPC_OPCODE_E500 | PPC_OPCODE_VLE | PPC_OPCODE_E200Z4
| PPC_OPCODE_EFS2),
0 },
{ "e300", PPC_OPCODE_PPC | PPC_OPCODE_E300,
0 },
@ -173,6 +179,8 @@ struct ppc_mopt ppc_opts[] = {
0 },
{ "efs2", PPC_OPCODE_PPC | PPC_OPCODE_EFS | PPC_OPCODE_EFS2,
0 },
{ "lsp", PPC_OPCODE_PPC,
PPC_OPCODE_LSP },
{ "power4", PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4,
0 },
{ "power5", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
@ -270,10 +278,10 @@ struct ppc_mopt ppc_opts[] = {
{ "titan", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_PMR
| PPC_OPCODE_RFMCI | PPC_OPCODE_TITAN),
0 },
{ "vle", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE| PPC_OPCODE_SPE
{ "vle", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
| PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
| PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
| PPC_OPCODE_LSP | PPC_OPCODE_EFS2 | PPC_OPCODE_SPE2),
| PPC_OPCODE_EFS2 | PPC_OPCODE_SPE2),
PPC_OPCODE_VLE },
{ "vsx", PPC_OPCODE_PPC,
PPC_OPCODE_VSX },
@ -321,7 +329,15 @@ ppc_parse_cpu (ppc_cpu_t ppc_cpu, ppc_cpu_t *sticky, const char *arg)
if (i >= ARRAY_SIZE (ppc_opts))
return 0;
/* SPE and LSP are mutually exclusive, don't allow them both in
sticky options. However do allow them both in ppc_cpu, so that
for example, -mvle -mlsp enables both SPE and LSP for assembly. */
if ((ppc_opts[i].sticky & PPC_OPCODE_LSP) != 0)
*sticky &= ~(PPC_OPCODE_SPE | PPC_OPCODE_SPE2);
else if ((ppc_opts[i].sticky & (PPC_OPCODE_SPE | PPC_OPCODE_SPE2)) != 0)
*sticky &= ~PPC_OPCODE_LSP;
ppc_cpu |= *sticky;
return ppc_cpu;
}
@ -412,6 +428,8 @@ static unsigned short powerpc_opcd_indices[PPC_OPCD_SEGS + 1];
static unsigned short prefix_opcd_indices[PREFIX_OPCD_SEGS + 1];
#define VLE_OPCD_SEGS (1 + VLE_OP_TO_SEG (VLE_OP (-1, 0xffff)))
static unsigned short vle_opcd_indices[VLE_OPCD_SEGS + 1];
#define LSP_OPCD_SEGS (1 + LSP_OP_TO_SEG (-1))
static unsigned short lsp_opcd_indices[LSP_OPCD_SEGS + 1];
#define SPE2_OPCD_SEGS (1 + SPE2_XOP_TO_SEG (SPE2_XOP (-1)))
static unsigned short spe2_opcd_indices[SPE2_OPCD_SEGS + 1];
@ -479,6 +497,15 @@ disassemble_init_powerpc (struct disassemble_info *info)
}
}
/* LSP opcodes */
for (seg = 0, idx = 0; seg <= LSP_OPCD_SEGS; seg++)
{
lsp_opcd_indices[seg] = idx;
for (; idx < lsp_num_opcodes; idx++)
if (seg < LSP_OP_TO_SEG (lsp_opcodes[idx].opcode))
break;
}
/* SPE2 opcodes */
for (seg = 0, idx = 0; seg <= SPE2_OPCD_SEGS; seg++)
{
@ -728,6 +755,51 @@ lookup_vle (uint64_t insn, ppc_cpu_t dialect)
return NULL;
}
/* Find a match for INSN in the LSP opcode table. */
static const struct powerpc_opcode *
lookup_lsp (uint64_t insn, ppc_cpu_t dialect)
{
const struct powerpc_opcode *opcode, *opcode_end;
unsigned op, seg;
op = PPC_OP (insn);
if (op != 0x4)
return NULL;
seg = LSP_OP_TO_SEG (insn);
/* Find the first match in the opcode table for this opcode. */
opcode_end = lsp_opcodes + lsp_opcd_indices[seg + 1];
for (opcode = lsp_opcodes + lsp_opcd_indices[seg];
opcode < opcode_end;
++opcode)
{
const ppc_opindex_t *opindex;
const struct powerpc_operand *operand;
int invalid;
if ((insn & opcode->mask) != opcode->opcode
|| (opcode->deprecated & dialect) != 0)
continue;
/* Check validity of operands. */
invalid = 0;
for (opindex = opcode->operands; *opindex != 0; ++opindex)
{
operand = powerpc_operands + *opindex;
if (operand->extract)
(*operand->extract) (insn, (ppc_cpu_t) 0, &invalid);
}
if (invalid)
continue;
return opcode;
}
return NULL;
}
/* Find a match for INSN in the SPE2 opcode table. */
static const struct powerpc_opcode *
@ -746,7 +818,7 @@ lookup_spe2 (uint64_t insn, ppc_cpu_t dialect)
xop = SPE2_XOP (insn);
seg = SPE2_XOP_TO_SEG (xop);
/* Find the first match in the opcode table for this major opcode. */
/* Find the first match in the opcode table for this opcode. */
opcode_end = spe2_opcodes + spe2_opcd_indices[seg + 1];
for (opcode = spe2_opcodes + spe2_opcd_indices[seg];
opcode < opcode_end;
@ -936,6 +1008,8 @@ print_insn_powerpc (bfd_vma memaddr,
}
if (opcode == NULL && insn_length == 4)
{
if ((dialect & PPC_OPCODE_LSP) != 0)
opcode = lookup_lsp (insn, dialect);
if ((dialect & PPC_OPCODE_SPE2) != 0)
opcode = lookup_spe2 (insn, dialect);
if (opcode == NULL)

664
opcodes/ppc-opc.c
View File

@ -23,6 +23,7 @@
#include <stdio.h>
#include "opcode/ppc.h"
#include "opintl.h"
#include "libiberty.h"
/* This file holds the PowerPC opcode table. The opcode table
includes almost all of the extended instruction mnemonics. This
@ -3873,8 +3874,7 @@ const struct powerpc_operand powerpc_operands[] =
{ 0x3, 15, NULL, NULL, 0 },
};
const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
/ sizeof (powerpc_operands[0]));
const unsigned int num_powerpc_operands = ARRAY_SIZE (powerpc_operands);
/* Macros used to form opcodes. */
@ -9582,8 +9582,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"dctfixqq", XVA(63,994,1), XVA_MASK, POWER10, PPCVLE, {VD, FRBp}},
};
const unsigned int powerpc_num_opcodes =
sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
const unsigned int powerpc_num_opcodes = ARRAY_SIZE (powerpc_opcodes);
/* The opcode table for 8-byte prefix instructions.
@ -9659,8 +9658,7 @@ const struct powerpc_opcode prefix_opcodes[] = {
{"pstxvp", P8LS|OP(62), P_D_MASK, POWER10, 0, {XTP, D34, PRA0, PCREL}},
};
const unsigned int prefix_num_opcodes =
sizeof (prefix_opcodes) / sizeof (prefix_opcodes[0]);
const unsigned int prefix_num_opcodes = ARRAY_SIZE (prefix_opcodes);
/* The VLE opcode table.
@ -9702,6 +9700,224 @@ const struct powerpc_opcode vle_opcodes[] = {
{"se_cmphl", SE_RR(3,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
/* by major opcode */
{"e_cmpi", SCI8BF(6,0,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
{"e_cmpwi", SCI8BF(6,0,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
{"e_cmpli", SCI8BF(6,1,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
{"e_cmplwi", SCI8BF(6,1,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
{"e_addi", SCI8(6,16), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
{"e_subi", SCI8(6,16), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}},
{"e_addi.", SCI8(6,17), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
{"e_addic", SCI8(6,18), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
{"e_subic", SCI8(6,18), SCI8_MASK, PPCVLE, EXT, {RT, RA, SCLSCI8N}},
{"e_addic.", SCI8(6,19), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
{"e_subic.", SCI8(6,19), SCI8_MASK, PPCVLE, EXT, {RT, RA, SCLSCI8N}},
{"e_mulli", SCI8(6,20), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
{"e_subfic", SCI8(6,22), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
{"e_subfic.", SCI8(6,23), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
{"e_andi", SCI8(6,24), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
{"e_andi.", SCI8(6,25), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
{"e_nop", SCI8(6,26), 0xffffffff, PPCVLE, EXT, {0}},
{"e_ori", SCI8(6,26), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
{"e_ori.", SCI8(6,27), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
{"e_xori", SCI8(6,28), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
{"e_xori.", SCI8(6,29), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
{"e_lbzu", OPVUP(6,0), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
{"e_lhau", OPVUP(6,3), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
{"e_lhzu", OPVUP(6,1), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
{"e_lmw", OPVUP(6,8), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
{"e_lwzu", OPVUP(6,2), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
{"e_stbu", OPVUP(6,4), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
{"e_sthu", OPVUP(6,5), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
{"e_stwu", OPVUP(6,6), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
{"e_stmw", OPVUP(6,9), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
{"e_lmvgprw", OPVUPRT(6,16,0),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
{"e_ldmvgprw", OPVUPRT(6,16,0),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
{"e_stmvgprw", OPVUPRT(6,17,0),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
{"e_lmvsprw", OPVUPRT(6,16,1),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
{"e_ldmvsprw", OPVUPRT(6,16,1),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
{"e_stmvsprw", OPVUPRT(6,17,1),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
{"e_lmvsrrw", OPVUPRT(6,16,4),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
{"e_ldmvsrrw", OPVUPRT(6,16,4),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
{"e_stmvsrrw", OPVUPRT(6,17,4),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
{"e_lmvcsrrw", OPVUPRT(6,16,5),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
{"e_ldmvcsrrw", OPVUPRT(6,16,5),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
{"e_stmvcsrrw", OPVUPRT(6,17,5),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
{"e_lmvdsrrw", OPVUPRT(6,16,6),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
{"e_ldmvdsrrw", OPVUPRT(6,16,6),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
{"e_stmvdsrrw", OPVUPRT(6,17,6),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
{"e_lmvmcsrrw", OPVUPRT(6,16,7),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
{"e_stmvmcsrrw", OPVUPRT(6,17,7),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
{"e_add16i", OP(7), OP_MASK, PPCVLE, 0, {RT, RA, SI}},
{"e_la", OP(7), OP_MASK, PPCVLE, EXT, {RT, D, RA0}},
{"e_sub16i", OP(7), OP_MASK, PPCVLE, EXT, {RT, RA, NSI}},
{"se_addi", SE_IM5(8,0), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
{"se_cmpli", SE_IM5(8,1), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
{"se_subi", SE_IM5(9,0), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
{"se_subi.", SE_IM5(9,1), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
{"se_cmpi", SE_IM5(10,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
{"se_bmaski", SE_IM5(11,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
{"se_andi", SE_IM5(11,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
{"e_lbz", OP(12), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
{"e_stb", OP(13), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
{"e_lha", OP(14), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
{"se_srw", SE_RR(16,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
{"se_sraw", SE_RR(16,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
{"se_slw", SE_RR(16,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
{"se_nop", SE_RR(17,0), 0xffff, PPCVLE, EXT, {0}},
{"se_or", SE_RR(17,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
{"se_andc", SE_RR(17,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
{"se_and", SE_RR(17,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
{"se_and.", SE_RR(17,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
{"se_li", IM7(9), IM7_MASK, PPCVLE, 0, {RX, UI7}},
{"e_lwz", OP(20), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
{"e_stw", OP(21), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
{"e_lhz", OP(22), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
{"e_sth", OP(23), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
{"se_bclri", SE_IM5(24,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
{"se_bgeni", SE_IM5(24,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
{"se_bseti", SE_IM5(25,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
{"se_btsti", SE_IM5(25,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
{"se_srwi", SE_IM5(26,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
{"se_srawi", SE_IM5(26,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
{"se_slwi", SE_IM5(27,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
{"e_lis", I16L(28,28), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
{"e_and2is.", I16L(28,29), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
{"e_or2is", I16L(28,26), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
{"e_and2i.", I16L(28,25), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
{"e_or2i", I16L(28,24), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
{"e_cmphl16i", IA16(28,23), IA16_MASK, PPCVLE, 0, {RA, VLEUIMM}},
{"e_cmph16i", IA16(28,22), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
{"e_cmpl16i", I16A(28,21), I16A_MASK, PPCVLE, 0, {RA, VLEUIMM}},
{"e_mull2i", I16A(28,20), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
{"e_cmp16i", IA16(28,19), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
{"e_sub2is", I16A(28,18), I16A_MASK, PPCVLE, EXT, {RA, VLENSIMM}},
{"e_add2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
{"e_sub2i.", I16A(28,17), I16A_MASK, PPCVLE, EXT, {RA, VLENSIMM}},
{"e_add2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
{"e_li", LI20(28,0), LI20_MASK, PPCVLE, 0, {RT, IMM20}},
{"e_rlwimi", M(29,0), M_MASK, PPCVLE, 0, {RA, RS, SH, MB, ME}},
{"e_inslwi", M(29,0), M_MASK, PPCVLE, EXT, {RA, RS, ILWn, ILWb}},
{"e_insrwi", M(29,0), M_MASK, PPCVLE, EXT, {RA, RS, IRWn, IRWb}},
{"e_rotlwi", MME(29,31,1), MMBME_MASK, PPCVLE, EXT, {RA, RS, SH}},
{"e_rotrwi", MME(29,31,1), MMBME_MASK, PPCVLE, EXT, {RA, RS, RRWn}},
{"e_clrlwi", MME(29,31,1), MSHME_MASK, PPCVLE, EXT, {RA, RS, MB}},
{"e_clrrwi", M(29,1), MSHMB_MASK, PPCVLE, EXT, {RA, RS, CRWn}},
{"e_rlwinm", M(29,1), M_MASK, PPCVLE, 0, {RA, RS, SH, MBE, ME}},
{"e_extlwi", M(29,1), MMB_MASK, PPCVLE, EXT, {RA, RS, ELWn, SH}},
{"e_extrwi", MME(29,31,1), MME_MASK, PPCVLE, EXT, {RA, RS, ERWn, ERWb}},
{"e_clrlslwi", M(29,1), M_MASK, PPCVLE, EXT, {RA, RS, CSLWb, CSLWn}},
{"e_b", BD24(30,0,0), BD24_MASK, PPCVLE, 0, {B24}},
{"e_bl", BD24(30,0,1), BD24_MASK, PPCVLE, 0, {B24}},
{"e_bdnz", EBD15(30,8,BO32DNZ,0), EBD15_MASK, PPCVLE, EXT, {B15}},
{"e_bdnzl", EBD15(30,8,BO32DNZ,1), EBD15_MASK, PPCVLE, EXT, {B15}},
{"e_bdz", EBD15(30,8,BO32DZ,0), EBD15_MASK, PPCVLE, EXT, {B15}},
{"e_bdzl", EBD15(30,8,BO32DZ,1), EBD15_MASK, PPCVLE, EXT, {B15}},
{"e_bge", EBD15BI(30,8,BO32F,CBLT,0), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}},
{"e_bgel", EBD15BI(30,8,BO32F,CBLT,1), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}},
{"e_bnl", EBD15BI(30,8,BO32F,CBLT,0), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}},
{"e_bnll", EBD15BI(30,8,BO32F,CBLT,1), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}},
{"e_blt", EBD15BI(30,8,BO32T,CBLT,0), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}},
{"e_bltl", EBD15BI(30,8,BO32T,CBLT,1), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}},
{"e_bgt", EBD15BI(30,8,BO32T,CBGT,0), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}},
{"e_bgtl", EBD15BI(30,8,BO32T,CBGT,1), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}},
{"e_ble", EBD15BI(30,8,BO32F,CBGT,0), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}},
{"e_blel", EBD15BI(30,8,BO32F,CBGT,1), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}},
{"e_bng", EBD15BI(30,8,BO32F,CBGT,0), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}},
{"e_bngl", EBD15BI(30,8,BO32F,CBGT,1), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}},
{"e_bne", EBD15BI(30,8,BO32F,CBEQ,0), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}},
{"e_bnel", EBD15BI(30,8,BO32F,CBEQ,1), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}},
{"e_beq", EBD15BI(30,8,BO32T,CBEQ,0), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}},
{"e_beql", EBD15BI(30,8,BO32T,CBEQ,1), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}},
{"e_bso", EBD15BI(30,8,BO32T,CBSO,0), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}},
{"e_bsol", EBD15BI(30,8,BO32T,CBSO,1), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}},
{"e_bun", EBD15BI(30,8,BO32T,CBSO,0), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}},
{"e_bunl", EBD15BI(30,8,BO32T,CBSO,1), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}},
{"e_bns", EBD15BI(30,8,BO32F,CBSO,0), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}},
{"e_bnsl", EBD15BI(30,8,BO32F,CBSO,1), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}},
{"e_bnu", EBD15BI(30,8,BO32F,CBSO,0), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}},
{"e_bnul", EBD15BI(30,8,BO32F,CBSO,1), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}},
{"e_bc", BD15(30,8,0), BD15_MASK, PPCVLE, 0, {BO32, BI32, B15}},
{"e_bcl", BD15(30,8,1), BD15_MASK, PPCVLE, 0, {BO32, BI32, B15}},
{"e_bf", EBD15(30,8,BO32F,0), EBD15_MASK, PPCVLE, EXT, {BI32,B15}},
{"e_bfl", EBD15(30,8,BO32F,1), EBD15_MASK, PPCVLE, EXT, {BI32,B15}},
{"e_bt", EBD15(30,8,BO32T,0), EBD15_MASK, PPCVLE, EXT, {BI32,B15}},
{"e_btl", EBD15(30,8,BO32T,1), EBD15_MASK, PPCVLE, EXT, {BI32,B15}},
{"e_cmph", X(31,14), X_MASK, PPCVLE, 0, {CRD, RA, RB}},
{"e_sc", X(31,36), XRTRA_MASK, PPCVLE, 0, {ELEV}},
{"e_cmphl", X(31,46), X_MASK, PPCVLE, 0, {CRD, RA, RB}},
{"e_crandc", XL(31,129), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
{"e_crnand", XL(31,225), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
{"e_crnot", XL(31,33), XL_MASK, PPCVLE, EXT, {BT, BAB}},
{"e_crnor", XL(31,33), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
{"e_crclr", XL(31,193), XL_MASK, PPCVLE, EXT, {BTAB}},
{"e_crxor", XL(31,193), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
{"e_mcrf", XL(31,16), XL_MASK, PPCVLE, 0, {CRD, CR}},
{"e_slwi", EX(31,112), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
{"e_slwi.", EX(31,113), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
{"e_crand", XL(31,257), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
{"e_rlw", EX(31,560), EX_MASK, PPCVLE, 0, {RA, RS, RB}},
{"e_rlw.", EX(31,561), EX_MASK, PPCVLE, 0, {RA, RS, RB}},
{"e_crset", XL(31,289), XL_MASK, PPCVLE, EXT, {BTAB}},
{"e_creqv", XL(31,289), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
{"e_rlwi", EX(31,624), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
{"e_rlwi.", EX(31,625), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
{"e_crorc", XL(31,417), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
{"e_crmove", XL(31,449), XL_MASK, PPCVLE, EXT, {BT, BAB}},
{"e_cror", XL(31,449), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
{"mtmas1", XSPR(31,467,625), XSPR_MASK, PPCVLE, EXT, {RS}},
{"e_srwi", EX(31,1136), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
{"e_srwi.", EX(31,1137), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
{"se_lbz", SD4(8), SD4_MASK, PPCVLE, 0, {RZ, SE_SD, RX}},
{"se_stb", SD4(9), SD4_MASK, PPCVLE, 0, {RZ, SE_SD, RX}},
{"se_lhz", SD4(10), SD4_MASK, PPCVLE, 0, {RZ, SE_SDH, RX}},
{"se_sth", SD4(11), SD4_MASK, PPCVLE, 0, {RZ, SE_SDH, RX}},
{"se_lwz", SD4(12), SD4_MASK, PPCVLE, 0, {RZ, SE_SDW, RX}},
{"se_stw", SD4(13), SD4_MASK, PPCVLE, 0, {RZ, SE_SDW, RX}},
{"se_bge", EBD8IO(28,0,0), EBD8IO3_MASK, PPCVLE, EXT, {B8}},
{"se_bnl", EBD8IO(28,0,0), EBD8IO3_MASK, PPCVLE, EXT, {B8}},
{"se_ble", EBD8IO(28,0,1), EBD8IO3_MASK, PPCVLE, EXT, {B8}},
{"se_bng", EBD8IO(28,0,1), EBD8IO3_MASK, PPCVLE, EXT, {B8}},
{"se_bne", EBD8IO(28,0,2), EBD8IO3_MASK, PPCVLE, EXT, {B8}},
{"se_bns", EBD8IO(28,0,3), EBD8IO3_MASK, PPCVLE, EXT, {B8}},
{"se_bnu", EBD8IO(28,0,3), EBD8IO3_MASK, PPCVLE, EXT, {B8}},
{"se_bf", EBD8IO(28,0,0), EBD8IO2_MASK, PPCVLE, EXT, {BI16, B8}},
{"se_blt", EBD8IO(28,1,0), EBD8IO3_MASK, PPCVLE, EXT, {B8}},
{"se_bgt", EBD8IO(28,1,1), EBD8IO3_MASK, PPCVLE, EXT, {B8}},
{"se_beq", EBD8IO(28,1,2), EBD8IO3_MASK, PPCVLE, EXT, {B8}},
{"se_bso", EBD8IO(28,1,3), EBD8IO3_MASK, PPCVLE, EXT, {B8}},
{"se_bun", EBD8IO(28,1,3), EBD8IO3_MASK, PPCVLE, EXT, {B8}},
{"se_bt", EBD8IO(28,1,0), EBD8IO2_MASK, PPCVLE, EXT, {BI16, B8}},
{"se_bc", BD8IO(28), BD8IO_MASK, PPCVLE, 0, {BO16, BI16, B8}},
{"se_b", BD8(58,0,0), BD8_MASK, PPCVLE, 0, {B8}},
{"se_bl", BD8(58,0,1), BD8_MASK, PPCVLE, 0, {B8}},
};
const unsigned int vle_num_opcodes = ARRAY_SIZE (vle_opcodes);
const struct powerpc_opcode lsp_opcodes[] = {
{"zvaddih", VX(4, 0x200), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM}},
{"zvsubifh", VX(4, 0x201), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM}},
{"zvaddh", VX(4, 0x204), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
@ -9798,6 +10014,114 @@ const struct powerpc_opcode vle_opcodes[] = {
{"zslwss", VX(4, 0x27D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
{"zslwius", VX(4, 0x27E), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM}},
{"zslwiss", VX(4, 0x27F), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM}},
{"zlddx", VX(4, 0x300), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
{"zldd", VX(4, 0x301), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8, RA}},
{"zldwx", VX(4, 0x302), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
{"zldw", VX(4, 0x303), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8, RA}},
{"zldhx", VX(4, 0x304), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
{"zldh", VX(4, 0x305), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8, RA}},
{"zlwgsfdx", VX(4, 0x308), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
{"zlwgsfd", VX(4, 0x309), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}},
{"zlwwosdx", VX(4, 0x30A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
{"zlwwosd", VX(4, 0x30B), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}},
{"zlwhsplatwdx", VX(4, 0x30C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
{"zlwhsplatwd", VX(4, 0x30D), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}},
{"zlwhsplatdx", VX(4, 0x30E), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
{"zlwhsplatd", VX(4, 0x30F), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}},
{"zlwhgwsfdx", VX(4, 0x310), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
{"zlwhgwsfd", VX(4, 0x311), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}},
{"zlwhedx", VX(4, 0x312), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
{"zlwhed", VX(4, 0x313), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}},
{"zlwhosdx", VX(4, 0x314), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
{"zlwhosd", VX(4, 0x315), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}},
{"zlwhoudx", VX(4, 0x316), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
{"zlwhoud", VX(4, 0x317), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}},
{"zlwhx", VX(4, 0x318), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
{"zlwh", VX(4, 0x319), VX_MASK, PPCLSP, 0, {RD, EVUIMM_4, RA}},
{"zlwwx", VX(4, 0x31A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
{"zlww", VX(4, 0x31B), VX_MASK, PPCLSP, 0, {RD, EVUIMM_4, RA}},
{"zlhgwsfx", VX(4, 0x31C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
{"zlhgwsf", VX(4, 0x31D), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2, RA}},
{"zlhhsplatx", VX(4, 0x31E), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
{"zlhhsplat", VX(4, 0x31F), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2, RA}},
{"zstddx", VX(4, 0x320), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
{"zstdd", VX(4, 0x321), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_8, RA}},
{"zstdwx", VX(4, 0x322), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
{"zstdw", VX(4, 0x323), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_8, RA}},
{"zstdhx", VX(4, 0x324), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
{"zstdh", VX(4, 0x325), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_8, RA}},
{"zstwhedx", VX(4, 0x328), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
{"zstwhed", VX(4, 0x329), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_4, RA}},
{"zstwhodx", VX(4, 0x32A), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
{"zstwhod", VX(4, 0x32B), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_4, RA}},
{"zlhhex", VX(4, 0x330), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
{"zlhhe", VX(4, 0x331), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2, RA}},
{"zlhhosx", VX(4, 0x332), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
{"zlhhos", VX(4, 0x333), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2, RA}},
{"zlhhoux", VX(4, 0x334), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
{"zlhhou", VX(4, 0x335), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2, RA}},
{"zsthex", VX(4, 0x338), VX_MASK, PPCLSP, 0, {RS, RA, RB}},
{"zsthe", VX(4, 0x339), VX_MASK, PPCLSP, 0, {RS, EVUIMM_2, RA}},
{"zsthox", VX(4, 0x33A), VX_MASK, PPCLSP, 0, {RS, RA, RB}},
{"zstho", VX(4, 0x33B), VX_MASK, PPCLSP, 0, {RS, EVUIMM_2, RA}},
{"zstwhx", VX(4, 0x33C), VX_MASK, PPCLSP, 0, {RS, RA, RB}},
{"zstwh", VX(4, 0x33D), VX_MASK, PPCLSP, 0, {RS, EVUIMM_4, RA}},
{"zstwwx", VX(4, 0x33E), VX_MASK, PPCLSP, 0, {RS, RA, RB}},
{"zstww", VX(4, 0x33F), VX_MASK, PPCLSP, 0, {RS, EVUIMM_4, RA}},
{"zlddmx", VX(4, 0x340), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
{"zlddu", VX(4, 0x341), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8_EX0, RA}},
{"zldwmx", VX(4, 0x342), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
{"zldwu", VX(4, 0x343), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8_EX0, RA}},
{"zldhmx", VX(4, 0x344), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
{"zldhu", VX(4, 0x345), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8_EX0, RA}},
{"zlwgsfdmx", VX(4, 0x348), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
{"zlwgsfdu", VX(4, 0x349), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}},
{"zlwwosdmx", VX(4, 0x34A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
{"zlwwosdu", VX(4, 0x34B), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}},
{"zlwhsplatwdmx", VX(4, 0x34C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
{"zlwhsplatwdu", VX(4, 0x34D), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}},
{"zlwhsplatdmx", VX(4, 0x34E), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
{"zlwhsplatdu", VX(4, 0x34F), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}},
{"zlwhgwsfdmx", VX(4, 0x350), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
{"zlwhgwsfdu", VX(4, 0x351), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}},
{"zlwhedmx", VX(4, 0x352), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
{"zlwhedu", VX(4, 0x353), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}},
{"zlwhosdmx", VX(4, 0x354), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
{"zlwhosdu", VX(4, 0x355), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}},
{"zlwhoudmx", VX(4, 0x356), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
{"zlwhoudu", VX(4, 0x357), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}},
{"zlwhmx", VX(4, 0x358), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
{"zlwhu", VX(4, 0x359), VX_MASK, PPCLSP, 0, {RD, EVUIMM_4_EX0, RA}},
{"zlwwmx", VX(4, 0x35A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
{"zlwwu", VX(4, 0x35B), VX_MASK, PPCLSP, 0, {RD, EVUIMM_4_EX0, RA}},
{"zlhgwsfmx", VX(4, 0x35C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
{"zlhgwsfu", VX(4, 0x35D), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2_EX0, RA}},
{"zlhhsplatmx", VX(4, 0x35E), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
{"zlhhsplatu", VX(4, 0x35F), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2_EX0, RA}},
{"zstddmx", VX(4, 0x360), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
{"zstddu", VX(4, 0x361), VX_MASK, PPCLSP, 0, {RS, EVUIMM_8_EX0, RA}},
{"zstdwmx", VX(4, 0x362), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
{"zstdwu", VX(4, 0x363), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_8_EX0, RA}},
{"zstdhmx", VX(4, 0x364), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
{"zstdhu", VX(4, 0x365), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_8_EX0, RA}},
{"zstwhedmx", VX(4, 0x368), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
{"zstwhedu", VX(4, 0x369), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_4_EX0, RA}},
{"zstwhodmx", VX(4, 0x36A), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
{"zstwhodu", VX(4, 0x36B), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_4_EX0, RA}},
{"zlhhemx", VX(4, 0x370), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
{"zlhheu", VX(4, 0x371), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2_EX0, RA}},
{"zlhhosmx", VX(4, 0x372), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
{"zlhhosu", VX(4, 0x373), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2_EX0, RA}},
{"zlhhoumx", VX(4, 0x374), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
{"zlhhouu", VX(4, 0x375), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2_EX0, RA}},
{"zsthemx", VX(4, 0x378), VX_MASK, PPCLSP, 0, {RS, RA, RB}},
{"zstheu", VX(4, 0x379), VX_MASK, PPCLSP, 0, {RS, EVUIMM_2_EX0, RA}},
{"zsthomx", VX(4, 0x37A), VX_MASK, PPCLSP, 0, {RS, RA, RB}},
{"zsthou", VX(4, 0x37B), VX_MASK, PPCLSP, 0, {RS, EVUIMM_2_EX0, RA}},
{"zstwhmx", VX(4, 0x37C), VX_MASK, PPCLSP, 0, {RS, RA, RB}},
{"zstwhu", VX(4, 0x37D), VX_MASK, PPCLSP, 0, {RS, EVUIMM_4_EX0, RA}},
{"zstwwmx", VX(4, 0x37E), VX_MASK, PPCLSP, 0, {RS, RA, RB}},
{"zstwwu", VX(4, 0x37F), VX_MASK, PPCLSP, 0, {RS, EVUIMM_4_EX0, RA}},
{"zaddwgui", VX(4, 0x460), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
{"zsubfwgui", VX(4, 0x461), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
{"zaddd", VX(4, 0x462), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
@ -10272,332 +10596,9 @@ const struct powerpc_opcode vle_opcodes[] = {
{"zmwsfraas", VX(4, 0x6FB), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
{"zmwsfans", VX(4, 0x6FC), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
{"zmwsfrans", VX(4, 0x6FD), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
{"zlddx", VX(4, 0x300), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
{"zldd", VX(4, 0x301), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8, RA}},
{"zldwx", VX(4, 0x302), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
{"zldw", VX(4, 0x303), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8, RA}},
{"zldhx", VX(4, 0x304), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
{"zldh", VX(4, 0x305), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8, RA}},
{"zlwgsfdx", VX(4, 0x308), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
{"zlwgsfd", VX(4, 0x309), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}},
{"zlwwosdx", VX(4, 0x30A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
{"zlwwosd", VX(4, 0x30B), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}},
{"zlwhsplatwdx", VX(4, 0x30C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
{"zlwhsplatwd", VX(4, 0x30D), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}},
{"zlwhsplatdx", VX(4, 0x30E), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
{"zlwhsplatd", VX(4, 0x30F), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}},
{"zlwhgwsfdx", VX(4, 0x310), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
{"zlwhgwsfd", VX(4, 0x311), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}},
{"zlwhedx", VX(4, 0x312), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
{"zlwhed", VX(4, 0x313), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}},
{"zlwhosdx", VX(4, 0x314), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
{"zlwhosd", VX(4, 0x315), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}},
{"zlwhoudx", VX(4, 0x316), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
{"zlwhoud", VX(4, 0x317), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}},
{"zlwhx", VX(4, 0x318), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
{"zlwh", VX(4, 0x319), VX_MASK, PPCLSP, 0, {RD, EVUIMM_4, RA}},
{"zlwwx", VX(4, 0x31A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
{"zlww", VX(4, 0x31B), VX_MASK, PPCLSP, 0, {RD, EVUIMM_4, RA}},
{"zlhgwsfx", VX(4, 0x31C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
{"zlhgwsf", VX(4, 0x31D), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2, RA}},
{"zlhhsplatx", VX(4, 0x31E), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
{"zlhhsplat", VX(4, 0x31F), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2, RA}},
{"zstddx", VX(4, 0x320), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
{"zstdd", VX(4, 0x321), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_8, RA}},
{"zstdwx", VX(4, 0x322), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
{"zstdw", VX(4, 0x323), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_8, RA}},
{"zstdhx", VX(4, 0x324), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
{"zstdh", VX(4, 0x325), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_8, RA}},
{"zstwhedx", VX(4, 0x328), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
{"zstwhed", VX(4, 0x329), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_4, RA}},
{"zstwhodx", VX(4, 0x32A), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
{"zstwhod", VX(4, 0x32B), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_4, RA}},
{"zlhhex", VX(4, 0x330), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
{"zlhhe", VX(4, 0x331), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2, RA}},
{"zlhhosx", VX(4, 0x332), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
{"zlhhos", VX(4, 0x333), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2, RA}},
{"zlhhoux", VX(4, 0x334), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
{"zlhhou", VX(4, 0x335), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2, RA}},
{"zsthex", VX(4, 0x338), VX_MASK, PPCLSP, 0, {RS, RA, RB}},
{"zsthe", VX(4, 0x339), VX_MASK, PPCLSP, 0, {RS, EVUIMM_2, RA}},
{"zsthox", VX(4, 0x33A), VX_MASK, PPCLSP, 0, {RS, RA, RB}},
{"zstho", VX(4, 0x33B), VX_MASK, PPCLSP, 0, {RS, EVUIMM_2, RA}},
{"zstwhx", VX(4, 0x33C), VX_MASK, PPCLSP, 0, {RS, RA, RB}},
{"zstwh", VX(4, 0x33D), VX_MASK, PPCLSP, 0, {RS, EVUIMM_4, RA}},
{"zstwwx", VX(4, 0x33E), VX_MASK, PPCLSP, 0, {RS, RA, RB}},
{"zstww", VX(4, 0x33F), VX_MASK, PPCLSP, 0, {RS, EVUIMM_4, RA}},
{"zlddmx", VX(4, 0x340), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
{"zlddu", VX(4, 0x341), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8_EX0, RA}},
{"zldwmx", VX(4, 0x342), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
{"zldwu", VX(4, 0x343), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8_EX0, RA}},
{"zldhmx", VX(4, 0x344), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
{"zldhu", VX(4, 0x345), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8_EX0, RA}},
{"zlwgsfdmx", VX(4, 0x348), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
{"zlwgsfdu", VX(4, 0x349), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}},
{"zlwwosdmx", VX(4, 0x34A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
{"zlwwosdu", VX(4, 0x34B), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}},
{"zlwhsplatwdmx", VX(4, 0x34C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
{"zlwhsplatwdu", VX(4, 0x34D), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}},
{"zlwhsplatdmx", VX(4, 0x34E), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
{"zlwhsplatdu", VX(4, 0x34F), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}},
{"zlwhgwsfdmx", VX(4, 0x350), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
{"zlwhgwsfdu", VX(4, 0x351), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}},
{"zlwhedmx", VX(4, 0x352), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
{"zlwhedu", VX(4, 0x353), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}},
{"zlwhosdmx", VX(4, 0x354), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
{"zlwhosdu", VX(4, 0x355), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}},
{"zlwhoudmx", VX(4, 0x356), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
{"zlwhoudu", VX(4, 0x357), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}},
{"zlwhmx", VX(4, 0x358), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
{"zlwhu", VX(4, 0x359), VX_MASK, PPCLSP, 0, {RD, EVUIMM_4_EX0, RA}},
{"zlwwmx", VX(4, 0x35A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
{"zlwwu", VX(4, 0x35B), VX_MASK, PPCLSP, 0, {RD, EVUIMM_4_EX0, RA}},
{"zlhgwsfmx", VX(4, 0x35C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
{"zlhgwsfu", VX(4, 0x35D), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2_EX0, RA}},
{"zlhhsplatmx", VX(4, 0x35E), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
{"zlhhsplatu", VX(4, 0x35F), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2_EX0, RA}},
{"zstddmx", VX(4, 0x360), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
{"zstddu", VX(4, 0x361), VX_MASK, PPCLSP, 0, {RS, EVUIMM_8_EX0, RA}},
{"zstdwmx", VX(4, 0x362), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
{"zstdwu", VX(4, 0x363), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_8_EX0, RA}},
{"zstdhmx", VX(4, 0x364), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
{"zstdhu", VX(4, 0x365), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_8_EX0, RA}},
{"zstwhedmx", VX(4, 0x368), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
{"zstwhedu", VX(4, 0x369), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_4_EX0, RA}},
{"zstwhodmx", VX(4, 0x36A), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
{"zstwhodu", VX(4, 0x36B), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_4_EX0, RA}},
{"zlhhemx", VX(4, 0x370), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
{"zlhheu", VX(4, 0x371), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2_EX0, RA}},
{"zlhhosmx", VX(4, 0x372), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
{"zlhhosu", VX(4, 0x373), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2_EX0, RA}},
{"zlhhoumx", VX(4, 0x374), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
{"zlhhouu", VX(4, 0x375), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2_EX0, RA}},
{"zsthemx", VX(4, 0x378), VX_MASK, PPCLSP, 0, {RS, RA, RB}},
{"zstheu", VX(4, 0x379), VX_MASK, PPCLSP, 0, {RS, EVUIMM_2_EX0, RA}},
{"zsthomx", VX(4, 0x37A), VX_MASK, PPCLSP, 0, {RS, RA, RB}},
{"zsthou", VX(4, 0x37B), VX_MASK, PPCLSP, 0, {RS, EVUIMM_2_EX0, RA}},
{"zstwhmx", VX(4, 0x37C), VX_MASK, PPCLSP, 0, {RS, RA, RB}},
{"zstwhu", VX(4, 0x37D), VX_MASK, PPCLSP, 0, {RS, EVUIMM_4_EX0, RA}},
{"zstwwmx", VX(4, 0x37E), VX_MASK, PPCLSP, 0, {RS, RA, RB}},
{"zstwwu", VX(4, 0x37F), VX_MASK, PPCLSP, 0, {RS, EVUIMM_4_EX0, RA}},
{"e_cmpi", SCI8BF(6,0,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
{"e_cmpwi", SCI8BF(6,0,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
{"e_cmpli", SCI8BF(6,1,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
{"e_cmplwi", SCI8BF(6,1,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
{"e_addi", SCI8(6,16), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
{"e_subi", SCI8(6,16), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}},
{"e_addi.", SCI8(6,17), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
{"e_addic", SCI8(6,18), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
{"e_subic", SCI8(6,18), SCI8_MASK, PPCVLE, EXT, {RT, RA, SCLSCI8N}},
{"e_addic.", SCI8(6,19), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
{"e_subic.", SCI8(6,19), SCI8_MASK, PPCVLE, EXT, {RT, RA, SCLSCI8N}},
{"e_mulli", SCI8(6,20), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
{"e_subfic", SCI8(6,22), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
{"e_subfic.", SCI8(6,23), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
{"e_andi", SCI8(6,24), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
{"e_andi.", SCI8(6,25), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
{"e_nop", SCI8(6,26), 0xffffffff, PPCVLE, EXT, {0}},
{"e_ori", SCI8(6,26), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
{"e_ori.", SCI8(6,27), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
{"e_xori", SCI8(6,28), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
{"e_xori.", SCI8(6,29), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
{"e_lbzu", OPVUP(6,0), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
{"e_lhau", OPVUP(6,3), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
{"e_lhzu", OPVUP(6,1), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
{"e_lmw", OPVUP(6,8), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
{"e_lwzu", OPVUP(6,2), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
{"e_stbu", OPVUP(6,4), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
{"e_sthu", OPVUP(6,5), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
{"e_stwu", OPVUP(6,6), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
{"e_stmw", OPVUP(6,9), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
{"e_lmvgprw", OPVUPRT(6,16,0),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
{"e_ldmvgprw", OPVUPRT(6,16,0),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
{"e_stmvgprw", OPVUPRT(6,17,0),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
{"e_lmvsprw", OPVUPRT(6,16,1),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
{"e_ldmvsprw", OPVUPRT(6,16,1),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
{"e_stmvsprw", OPVUPRT(6,17,1),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
{"e_lmvsrrw", OPVUPRT(6,16,4),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
{"e_ldmvsrrw", OPVUPRT(6,16,4),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
{"e_stmvsrrw", OPVUPRT(6,17,4),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
{"e_lmvcsrrw", OPVUPRT(6,16,5),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
{"e_ldmvcsrrw", OPVUPRT(6,16,5),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
{"e_stmvcsrrw", OPVUPRT(6,17,5),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
{"e_lmvdsrrw", OPVUPRT(6,16,6),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
{"e_ldmvdsrrw", OPVUPRT(6,16,6),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
{"e_stmvdsrrw", OPVUPRT(6,17,6),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
{"e_lmvmcsrrw", OPVUPRT(6,16,7),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
{"e_stmvmcsrrw", OPVUPRT(6,17,7),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
{"e_add16i", OP(7), OP_MASK, PPCVLE, 0, {RT, RA, SI}},
{"e_la", OP(7), OP_MASK, PPCVLE, EXT, {RT, D, RA0}},
{"e_sub16i", OP(7), OP_MASK, PPCVLE, EXT, {RT, RA, NSI}},
{"se_addi", SE_IM5(8,0), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
{"se_cmpli", SE_IM5(8,1), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
{"se_subi", SE_IM5(9,0), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
{"se_subi.", SE_IM5(9,1), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
{"se_cmpi", SE_IM5(10,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
{"se_bmaski", SE_IM5(11,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
{"se_andi", SE_IM5(11,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
{"e_lbz", OP(12), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
{"e_stb", OP(13), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
{"e_lha", OP(14), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
{"se_srw", SE_RR(16,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
{"se_sraw", SE_RR(16,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
{"se_slw", SE_RR(16,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
{"se_nop", SE_RR(17,0), 0xffff, PPCVLE, EXT, {0}},
{"se_or", SE_RR(17,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
{"se_andc", SE_RR(17,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
{"se_and", SE_RR(17,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
{"se_and.", SE_RR(17,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
{"se_li", IM7(9), IM7_MASK, PPCVLE, 0, {RX, UI7}},
{"e_lwz", OP(20), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
{"e_stw", OP(21), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
{"e_lhz", OP(22), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
{"e_sth", OP(23), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
{"se_bclri", SE_IM5(24,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
{"se_bgeni", SE_IM5(24,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
{"se_bseti", SE_IM5(25,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
{"se_btsti", SE_IM5(25,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
{"se_srwi", SE_IM5(26,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
{"se_srawi", SE_IM5(26,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
{"se_slwi", SE_IM5(27,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
{"e_lis", I16L(28,28), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
{"e_and2is.", I16L(28,29), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
{"e_or2is", I16L(28,26), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
{"e_and2i.", I16L(28,25), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
{"e_or2i", I16L(28,24), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
{"e_cmphl16i", IA16(28,23), IA16_MASK, PPCVLE, 0, {RA, VLEUIMM}},
{"e_cmph16i", IA16(28,22), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
{"e_cmpl16i", I16A(28,21), I16A_MASK, PPCVLE, 0, {RA, VLEUIMM}},
{"e_mull2i", I16A(28,20), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
{"e_cmp16i", IA16(28,19), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
{"e_sub2is", I16A(28,18), I16A_MASK, PPCVLE, EXT, {RA, VLENSIMM}},
{"e_add2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
{"e_sub2i.", I16A(28,17), I16A_MASK, PPCVLE, EXT, {RA, VLENSIMM}},
{"e_add2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
{"e_li", LI20(28,0), LI20_MASK, PPCVLE, 0, {RT, IMM20}},
{"e_rlwimi", M(29,0), M_MASK, PPCVLE, 0, {RA, RS, SH, MB, ME}},
{"e_inslwi", M(29,0), M_MASK, PPCVLE, EXT, {RA, RS, ILWn, ILWb}},
{"e_insrwi", M(29,0), M_MASK, PPCVLE, EXT, {RA, RS, IRWn, IRWb}},
{"e_rotlwi", MME(29,31,1), MMBME_MASK, PPCVLE, EXT, {RA, RS, SH}},
{"e_rotrwi", MME(29,31,1), MMBME_MASK, PPCVLE, EXT, {RA, RS, RRWn}},
{"e_clrlwi", MME(29,31,1), MSHME_MASK, PPCVLE, EXT, {RA, RS, MB}},
{"e_clrrwi", M(29,1), MSHMB_MASK, PPCVLE, EXT, {RA, RS, CRWn}},
{"e_rlwinm", M(29,1), M_MASK, PPCVLE, 0, {RA, RS, SH, MBE, ME}},
{"e_extlwi", M(29,1), MMB_MASK, PPCVLE, EXT, {RA, RS, ELWn, SH}},
{"e_extrwi", MME(29,31,1), MME_MASK, PPCVLE, EXT, {RA, RS, ERWn, ERWb}},
{"e_clrlslwi", M(29,1), M_MASK, PPCVLE, EXT, {RA, RS, CSLWb, CSLWn}},
{"e_b", BD24(30,0,0), BD24_MASK, PPCVLE, 0, {B24}},
{"e_bl", BD24(30,0,1), BD24_MASK, PPCVLE, 0, {B24}},
{"e_bdnz", EBD15(30,8,BO32DNZ,0), EBD15_MASK, PPCVLE, EXT, {B15}},
{"e_bdnzl", EBD15(30,8,BO32DNZ,1), EBD15_MASK, PPCVLE, EXT, {B15}},
{"e_bdz", EBD15(30,8,BO32DZ,0), EBD15_MASK, PPCVLE, EXT, {B15}},
{"e_bdzl", EBD15(30,8,BO32DZ,1), EBD15_MASK, PPCVLE, EXT, {B15}},
{"e_bge", EBD15BI(30,8,BO32F,CBLT,0), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}},
{"e_bgel", EBD15BI(30,8,BO32F,CBLT,1), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}},
{"e_bnl", EBD15BI(30,8,BO32F,CBLT,0), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}},
{"e_bnll", EBD15BI(30,8,BO32F,CBLT,1), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}},
{"e_blt", EBD15BI(30,8,BO32T,CBLT,0), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}},
{"e_bltl", EBD15BI(30,8,BO32T,CBLT,1), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}},
{"e_bgt", EBD15BI(30,8,BO32T,CBGT,0), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}},
{"e_bgtl", EBD15BI(30,8,BO32T,CBGT,1), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}},
{"e_ble", EBD15BI(30,8,BO32F,CBGT,0), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}},
{"e_blel", EBD15BI(30,8,BO32F,CBGT,1), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}},
{"e_bng", EBD15BI(30,8,BO32F,CBGT,0), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}},
{"e_bngl", EBD15BI(30,8,BO32F,CBGT,1), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}},
{"e_bne", EBD15BI(30,8,BO32F,CBEQ,0), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}},
{"e_bnel", EBD15BI(30,8,BO32F,CBEQ,1), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}},
{"e_beq", EBD15BI(30,8,BO32T,CBEQ,0), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}},
{"e_beql", EBD15BI(30,8,BO32T,CBEQ,1), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}},
{"e_bso", EBD15BI(30,8,BO32T,CBSO,0), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}},
{"e_bsol", EBD15BI(30,8,BO32T,CBSO,1), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}},
{"e_bun", EBD15BI(30,8,BO32T,CBSO,0), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}},
{"e_bunl", EBD15BI(30,8,BO32T,CBSO,1), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}},
{"e_bns", EBD15BI(30,8,BO32F,CBSO,0), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}},
{"e_bnsl", EBD15BI(30,8,BO32F,CBSO,1), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}},
{"e_bnu", EBD15BI(30,8,BO32F,CBSO,0), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}},
{"e_bnul", EBD15BI(30,8,BO32F,CBSO,1), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}},
{"e_bc", BD15(30,8,0), BD15_MASK, PPCVLE, 0, {BO32, BI32, B15}},
{"e_bcl", BD15(30,8,1), BD15_MASK, PPCVLE, 0, {BO32, BI32, B15}},
{"e_bf", EBD15(30,8,BO32F,0), EBD15_MASK, PPCVLE, EXT, {BI32,B15}},
{"e_bfl", EBD15(30,8,BO32F,1), EBD15_MASK, PPCVLE, EXT, {BI32,B15}},
{"e_bt", EBD15(30,8,BO32T,0), EBD15_MASK, PPCVLE, EXT, {BI32,B15}},
{"e_btl", EBD15(30,8,BO32T,1), EBD15_MASK, PPCVLE, EXT, {BI32,B15}},
{"e_cmph", X(31,14), X_MASK, PPCVLE, 0, {CRD, RA, RB}},
{"e_sc", X(31,36), XRTRA_MASK, PPCVLE, 0, {ELEV}},
{"e_cmphl", X(31,46), X_MASK, PPCVLE, 0, {CRD, RA, RB}},
{"e_crandc", XL(31,129), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
{"e_crnand", XL(31,225), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
{"e_crnot", XL(31,33), XL_MASK, PPCVLE, EXT, {BT, BAB}},
{"e_crnor", XL(31,33), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
{"e_crclr", XL(31,193), XL_MASK, PPCVLE, EXT, {BTAB}},
{"e_crxor", XL(31,193), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
{"e_mcrf", XL(31,16), XL_MASK, PPCVLE, 0, {CRD, CR}},
{"e_slwi", EX(31,112), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
{"e_slwi.", EX(31,113), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
{"e_crand", XL(31,257), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
{"e_rlw", EX(31,560), EX_MASK, PPCVLE, 0, {RA, RS, RB}},
{"e_rlw.", EX(31,561), EX_MASK, PPCVLE, 0, {RA, RS, RB}},
{"e_crset", XL(31,289), XL_MASK, PPCVLE, EXT, {BTAB}},
{"e_creqv", XL(31,289), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
{"e_rlwi", EX(31,624), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
{"e_rlwi.", EX(31,625), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
{"e_crorc", XL(31,417), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
{"e_crmove", XL(31,449), XL_MASK, PPCVLE, EXT, {BT, BAB}},
{"e_cror", XL(31,449), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
{"mtmas1", XSPR(31,467,625), XSPR_MASK, PPCVLE, EXT, {RS}},
{"e_srwi", EX(31,1136), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
{"e_srwi.", EX(31,1137), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
{"se_lbz", SD4(8), SD4_MASK, PPCVLE, 0, {RZ, SE_SD, RX}},
{"se_stb", SD4(9), SD4_MASK, PPCVLE, 0, {RZ, SE_SD, RX}},
{"se_lhz", SD4(10), SD4_MASK, PPCVLE, 0, {RZ, SE_SDH, RX}},
{"se_sth", SD4(11), SD4_MASK, PPCVLE, 0, {RZ, SE_SDH, RX}},
{"se_lwz", SD4(12), SD4_MASK, PPCVLE, 0, {RZ, SE_SDW, RX}},
{"se_stw", SD4(13), SD4_MASK, PPCVLE, 0, {RZ, SE_SDW, RX}},
{"se_bge", EBD8IO(28,0,0), EBD8IO3_MASK, PPCVLE, EXT, {B8}},
{"se_bnl", EBD8IO(28,0,0), EBD8IO3_MASK, PPCVLE, EXT, {B8}},
{"se_ble", EBD8IO(28,0,1), EBD8IO3_MASK, PPCVLE, EXT, {B8}},
{"se_bng", EBD8IO(28,0,1), EBD8IO3_MASK, PPCVLE, EXT, {B8}},
{"se_bne", EBD8IO(28,0,2), EBD8IO3_MASK, PPCVLE, EXT, {B8}},
{"se_bns", EBD8IO(28,0,3), EBD8IO3_MASK, PPCVLE, EXT, {B8}},
{"se_bnu", EBD8IO(28,0,3), EBD8IO3_MASK, PPCVLE, EXT, {B8}},
{"se_bf", EBD8IO(28,0,0), EBD8IO2_MASK, PPCVLE, EXT, {BI16, B8}},
{"se_blt", EBD8IO(28,1,0), EBD8IO3_MASK, PPCVLE, EXT, {B8}},
{"se_bgt", EBD8IO(28,1,1), EBD8IO3_MASK, PPCVLE, EXT, {B8}},
{"se_beq", EBD8IO(28,1,2), EBD8IO3_MASK, PPCVLE, EXT, {B8}},
{"se_bso", EBD8IO(28,1,3), EBD8IO3_MASK, PPCVLE, EXT, {B8}},
{"se_bun", EBD8IO(28,1,3), EBD8IO3_MASK, PPCVLE, EXT, {B8}},
{"se_bt", EBD8IO(28,1,0), EBD8IO2_MASK, PPCVLE, EXT, {BI16, B8}},
{"se_bc", BD8IO(28), BD8IO_MASK, PPCVLE, 0, {BO16, BI16, B8}},
{"se_b", BD8(58,0,0), BD8_MASK, PPCVLE, 0, {B8}},
{"se_bl", BD8(58,0,1), BD8_MASK, PPCVLE, 0, {B8}},
};
const unsigned int vle_num_opcodes =
sizeof (vle_opcodes) / sizeof (vle_opcodes[0]);
const unsigned int lsp_num_opcodes = ARRAY_SIZE (lsp_opcodes);
/* SPE v2 instruction set from SPE2PIM Rev. 2 08/2011 */
const struct powerpc_opcode spe2_opcodes[] = {
@ -11391,5 +11392,4 @@ const struct powerpc_opcode spe2_opcodes[] = {
{"evavgdsr", VX (4, 1663), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
};
const unsigned int spe2_num_opcodes =
sizeof (spe2_opcodes) / sizeof (spe2_opcodes[0]);
const unsigned int spe2_num_opcodes = ARRAY_SIZE (spe2_opcodes);