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* config/tc-mips.c (mips_arg_info): Replace allow_nonconst and lax_max with lax_match. (match_int_operand): Update accordingly. Don't report an error for !lax_match-only cases. (match_insn): Replace more_alts with lax_match and use it to initialize the mips_arg_info field. Add a complete_p parameter. Handle implicit VU0 suffixes here. (match_invalid_for_isa, match_insns, match_mips16_insns): New functions. (mips_ip, mips16_ip): Use them.
This commit is contained in:
Richard Sandiford
parent
d436c1c2e8
commit
60f20e8ba8
@ -1,3 +1,16 @@
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2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
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* config/tc-mips.c (mips_arg_info): Replace allow_nonconst and
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lax_max with lax_match.
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(match_int_operand): Update accordingly. Don't report an error
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for !lax_match-only cases.
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(match_insn): Replace more_alts with lax_match and use it to
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initialize the mips_arg_info field. Add a complete_p parameter.
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Handle implicit VU0 suffixes here.
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(match_invalid_for_isa, match_insns, match_mips16_insns): New
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functions.
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(mips_ip, mips16_ip): Use them.
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2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
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* config/tc-mips.c (match_expression): Report uses of registers here.
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@ -4271,14 +4271,11 @@ struct mips_arg_info
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where it gives the lsb position. */
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unsigned int last_op_int;
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/* If true, the OP_INT match routine should treat plain symbolic operands
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as if a relocation operator like %lo(...) had been used. This is only
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ever true if the operand can be relocated. */
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bfd_boolean allow_nonconst;
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/* When true, the OP_INT match routine should allow unsigned N-bit
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arguments to be used where a signed N-bit operand is expected. */
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bfd_boolean lax_max;
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/* If true, match routines should assume that no later instruction
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alternative matches and should therefore be as accomodating as
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possible. Match routines should not report errors if something
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is only invalid for !LAX_MATCH. */
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bfd_boolean lax_match;
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/* True if a reference to the current AT register was seen. */
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bfd_boolean seen_at;
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@ -4559,8 +4556,6 @@ match_int_operand (struct mips_arg_info *arg,
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factor = 1 << operand->shift;
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min_val = mips_int_operand_min (operand);
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max_val = mips_int_operand_max (operand);
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if (arg->lax_max)
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max_val = ((1 << operand_base->size) - 1) << operand->shift;
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if (operand_base->lsb == 0
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&& operand_base->size == 16
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@ -4580,13 +4575,10 @@ match_int_operand (struct mips_arg_info *arg,
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if (offset_expr.X_op != O_constant)
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{
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/* If non-constant operands are allowed then leave them for
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the caller to process, otherwise fail the match. */
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if (!arg->allow_nonconst)
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{
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match_not_constant (arg);
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return FALSE;
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}
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/* Accept non-constant operands if no later alternative matches,
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leaving it for the caller to process. */
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if (!arg->lax_match)
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return FALSE;
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offset_reloc[0] = BFD_RELOC_LO16;
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return TRUE;
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}
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@ -4595,6 +4587,16 @@ match_int_operand (struct mips_arg_info *arg,
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ourselves. */
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sval = offset_expr.X_add_number;
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offset_expr.X_op = O_absent;
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/* For compatibility with older assemblers, we accept
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0x8000-0xffff as signed 16-bit numbers when only
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signed numbers are allowed. */
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if (sval > max_val)
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{
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max_val = ((1 << operand_base->size) - 1) << operand->shift;
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if (!arg->lax_match && sval <= max_val)
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return FALSE;
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}
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}
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else
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{
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@ -7047,7 +7049,7 @@ normalize_address_expr (expressionS *ex)
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static bfd_boolean
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match_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode,
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struct mips_operand_token *tokens, unsigned int opcode_extra,
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bfd_boolean more_alts)
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bfd_boolean lax_match, bfd_boolean complete_p)
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{
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const char *args;
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struct mips_arg_info arg;
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@ -7062,13 +7064,18 @@ match_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode,
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offset_reloc[2] = BFD_RELOC_UNUSED;
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create_insn (insn, opcode);
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insn->insn_opcode |= opcode_extra;
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/* When no opcode suffix is specified, assume ".xyzw". */
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if ((opcode->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) != 0 && opcode_extra == 0)
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insn->insn_opcode |= 0xf << mips_vu0_channel_mask.lsb;
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else
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insn->insn_opcode |= opcode_extra;
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memset (&arg, 0, sizeof (arg));
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arg.insn = insn;
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arg.token = tokens;
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arg.argnum = 1;
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arg.last_regno = ILLEGAL_REG;
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arg.dest_regno = ILLEGAL_REG;
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arg.lax_match = lax_match;
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for (args = opcode->args;; ++args)
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{
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if (arg.token->type == OT_END)
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@ -7107,6 +7114,8 @@ match_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode,
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return FALSE;
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/* Successful match. */
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if (!complete_p)
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return TRUE;
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clear_insn_error ();
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if (arg.dest_regno == arg.last_regno
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&& strncmp (insn->insn_mo->name, "jalr", 4) == 0)
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@ -7148,7 +7157,6 @@ match_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode,
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/* Handle special macro operands. Work out the properties of
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other operands. */
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arg.opnum += 1;
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arg.lax_max = FALSE;
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switch (*args)
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{
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case '+':
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@ -7219,32 +7227,6 @@ match_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode,
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return FALSE;
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continue;
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/* ??? This is the traditional behavior, but is flaky if
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there are alternative versions of the same instruction
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for different subarchitectures. The next alternative
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might not be suitable. */
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case 'j':
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/* For compatibility with older assemblers, we accept
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0x8000-0xffff as signed 16-bit numbers when only
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signed numbers are allowed. */
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arg.lax_max = !more_alts;
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case 'i':
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/* Only accept non-constant operands if this is the
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final alternative. Later alternatives might include
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a macro implementation. */
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arg.allow_nonconst = !more_alts;
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break;
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case 'u':
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/* There are no macro implementations for out-of-range values. */
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arg.allow_nonconst = TRUE;
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break;
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case 'o':
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/* There should always be a macro implementation. */
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arg.allow_nonconst = FALSE;
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break;
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case 'p':
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*offset_reloc = BFD_RELOC_16_PCREL_S2;
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break;
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@ -7479,6 +7461,141 @@ match_mips16_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode,
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}
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}
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/* Record that the current instruction is invalid for the current ISA. */
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static void
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match_invalid_for_isa (void)
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{
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set_insn_error_ss
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(0, _("Opcode not supported on this processor: %s (%s)"),
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mips_cpu_info_from_arch (mips_opts.arch)->name,
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mips_cpu_info_from_isa (mips_opts.isa)->name);
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}
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/* Try to match TOKENS against a series of opcode entries, starting at FIRST.
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Return true if a definite match or failure was found, storing any match
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in INSN. OPCODE_EXTRA is a value that should be ORed into the opcode
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(to handle things like VU0 suffixes). LAX_MATCH is true if we have already
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tried and failed to match under normal conditions and now want to try a
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more relaxed match. */
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static bfd_boolean
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match_insns (struct mips_cl_insn *insn, const struct mips_opcode *first,
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const struct mips_opcode *past, struct mips_operand_token *tokens,
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int opcode_extra, bfd_boolean lax_match)
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{
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const struct mips_opcode *opcode;
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const struct mips_opcode *invalid_delay_slot;
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bfd_boolean seen_valid_for_isa, seen_valid_for_size;
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/* Search for a match, ignoring alternatives that don't satisfy the
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current ISA or forced_length. */
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invalid_delay_slot = 0;
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seen_valid_for_isa = FALSE;
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seen_valid_for_size = FALSE;
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opcode = first;
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do
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{
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gas_assert (strcmp (opcode->name, first->name) == 0);
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if (is_opcode_valid (opcode))
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{
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seen_valid_for_isa = TRUE;
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if (is_size_valid (opcode))
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{
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bfd_boolean delay_slot_ok;
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seen_valid_for_size = TRUE;
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delay_slot_ok = is_delay_slot_valid (opcode);
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if (match_insn (insn, opcode, tokens, opcode_extra,
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lax_match, delay_slot_ok))
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{
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if (!delay_slot_ok)
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{
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if (!invalid_delay_slot)
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invalid_delay_slot = opcode;
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}
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else
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return TRUE;
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}
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}
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}
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++opcode;
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}
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while (opcode < past && strcmp (opcode->name, first->name) == 0);
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/* If the only matches we found had the wrong length for the delay slot,
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pick the first such match. We'll issue an appropriate warning later. */
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if (invalid_delay_slot)
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{
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if (match_insn (insn, invalid_delay_slot, tokens, opcode_extra,
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lax_match, TRUE))
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return TRUE;
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abort ();
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}
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/* Handle the case where we didn't try to match an instruction because
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all the alternatives were incompatible with the current ISA. */
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if (!seen_valid_for_isa)
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{
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match_invalid_for_isa ();
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return TRUE;
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}
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/* Handle the case where we didn't try to match an instruction because
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all the alternatives were of the wrong size. */
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if (!seen_valid_for_size)
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{
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if (mips_opts.insn32)
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set_insn_error (0, _("Opcode not supported in the `insn32' mode"));
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else
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set_insn_error_i
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(0, _("Unrecognized %d-bit version of microMIPS opcode"),
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8 * forced_insn_length);
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return TRUE;
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}
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return FALSE;
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}
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/* Like match_insns, but for MIPS16. */
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static bfd_boolean
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match_mips16_insns (struct mips_cl_insn *insn, const struct mips_opcode *first,
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struct mips_operand_token *tokens)
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{
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const struct mips_opcode *opcode;
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bfd_boolean seen_valid_for_isa;
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/* Search for a match, ignoring alternatives that don't satisfy the
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current ISA. There are no separate entries for extended forms so
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we deal with forced_length later. */
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seen_valid_for_isa = FALSE;
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opcode = first;
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do
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{
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gas_assert (strcmp (opcode->name, first->name) == 0);
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if (is_opcode_valid_16 (opcode))
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{
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seen_valid_for_isa = TRUE;
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if (match_mips16_insn (insn, opcode, tokens))
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return TRUE;
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}
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++opcode;
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}
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while (opcode < &mips16_opcodes[bfd_mips16_num_opcodes]
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&& strcmp (opcode->name, first->name) == 0);
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/* Handle the case where we didn't try to match an instruction because
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all the alternatives were incompatible with the current ISA. */
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if (!seen_valid_for_isa)
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{
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match_invalid_for_isa ();
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return TRUE;
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}
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return FALSE;
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}
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/* Set up global variables for the start of a new macro. */
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static void
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@ -12952,14 +13069,10 @@ mips_lookup_insn (struct hash_control *hash, const char *start,
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to offset_expr. */
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static void
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mips_ip (char *str, struct mips_cl_insn *ip)
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mips_ip (char *str, struct mips_cl_insn *insn)
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{
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bfd_boolean wrong_delay_slot_insns = FALSE;
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bfd_boolean need_delay_slot_ok = TRUE;
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struct mips_opcode *firstinsn = NULL;
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const struct mips_opcode *past;
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const struct mips_opcode *first, *past;
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struct hash_control *hash;
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struct mips_opcode *first, *insn;
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char format;
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size_t end;
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struct mips_operand_token *tokens;
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@ -12976,26 +13089,22 @@ mips_ip (char *str, struct mips_cl_insn *ip)
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past = &mips_opcodes[NUMOPCODES];
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}
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forced_insn_length = 0;
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insn = NULL;
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opcode_extra = 0;
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/* We first try to match an instruction up to a space or to the end. */
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for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++)
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continue;
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first = insn = mips_lookup_insn (hash, str, end, &opcode_extra);
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if (insn == NULL)
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first = mips_lookup_insn (hash, str, end, &opcode_extra);
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if (first == NULL)
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{
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set_insn_error (0, _("Unrecognized opcode"));
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return;
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}
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/* When no opcode suffix is specified, assume ".xyzw". */
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if ((insn->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) != 0 && opcode_extra == 0)
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opcode_extra = 0xf << mips_vu0_channel_mask.lsb;
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if (strcmp (insn->name, "li.s") == 0)
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if (strcmp (first->name, "li.s") == 0)
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format = 'f';
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else if (strcmp (insn->name, "li.d") == 0)
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else if (strcmp (first->name, "li.d") == 0)
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format = 'd';
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else
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format = 0;
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@ -13003,84 +13112,10 @@ mips_ip (char *str, struct mips_cl_insn *ip)
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if (!tokens)
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return;
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/* For microMIPS instructions placed in a fixed-length branch delay slot
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we make up to two passes over the relevant fragment of the opcode
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table. First we try instructions that meet the delay slot's length
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requirement. If none matched, then we retry with the remaining ones
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and if one matches, then we use it and then issue an appropriate
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warning later on. */
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for (;;)
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{
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bfd_boolean delay_slot_ok;
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bfd_boolean size_ok;
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bfd_boolean ok;
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bfd_boolean more_alts;
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if (!match_insns (insn, first, past, tokens, opcode_extra, FALSE)
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&& !match_insns (insn, first, past, tokens, opcode_extra, TRUE))
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set_insn_error (0, _("Illegal operands"));
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gas_assert (strcmp (insn->name, first->name) == 0);
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ok = is_opcode_valid (insn);
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size_ok = is_size_valid (insn);
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delay_slot_ok = is_delay_slot_valid (insn);
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if (!delay_slot_ok && !wrong_delay_slot_insns)
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{
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firstinsn = insn;
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wrong_delay_slot_insns = TRUE;
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}
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more_alts = (insn + 1 < past
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&& strcmp (insn[0].name, insn[1].name) == 0);
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if (!ok || !size_ok || delay_slot_ok != need_delay_slot_ok)
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{
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if (more_alts)
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{
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++insn;
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continue;
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}
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if (wrong_delay_slot_insns && need_delay_slot_ok)
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{
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gas_assert (firstinsn);
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need_delay_slot_ok = FALSE;
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past = insn + 1;
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insn = firstinsn;
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continue;
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}
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if (!ok)
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set_insn_error_ss
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(0, _("Opcode not supported on this processor: %s (%s)"),
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mips_cpu_info_from_arch (mips_opts.arch)->name,
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mips_cpu_info_from_isa (mips_opts.isa)->name);
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else if (mips_opts.insn32)
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set_insn_error
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(0, _("Opcode not supported in the `insn32' mode"));
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else
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set_insn_error_i
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(0, _("Unrecognized %d-bit version of microMIPS opcode"),
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8 * forced_insn_length);
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break;
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}
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if (match_insn (ip, insn, tokens, opcode_extra,
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more_alts || (wrong_delay_slot_insns
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&& need_delay_slot_ok)))
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break;
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/* Args don't match. */
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set_insn_error (0, _("Illegal operands"));
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if (more_alts)
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{
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++insn;
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continue;
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}
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if (wrong_delay_slot_insns && need_delay_slot_ok)
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{
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gas_assert (firstinsn);
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need_delay_slot_ok = FALSE;
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past = insn + 1;
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insn = firstinsn;
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continue;
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}
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break;
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}
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obstack_free (&mips_operand_tokens, tokens);
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}
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|
||||
@ -13089,10 +13124,10 @@ mips_ip (char *str, struct mips_cl_insn *ip)
|
||||
bytes if the user explicitly requested a small or extended instruction. */
|
||||
|
||||
static void
|
||||
mips16_ip (char *str, struct mips_cl_insn *ip)
|
||||
mips16_ip (char *str, struct mips_cl_insn *insn)
|
||||
{
|
||||
char *end, *s, c;
|
||||
struct mips_opcode *insn, *first;
|
||||
struct mips_opcode *first;
|
||||
struct mips_operand_token *tokens;
|
||||
|
||||
forced_insn_length = 0;
|
||||
@ -13133,10 +13168,10 @@ mips16_ip (char *str, struct mips_cl_insn *ip)
|
||||
forced_insn_length = 2;
|
||||
|
||||
*end = 0;
|
||||
first = insn = (struct mips_opcode *) hash_find (mips16_op_hash, str);
|
||||
first = (struct mips_opcode *) hash_find (mips16_op_hash, str);
|
||||
*end = c;
|
||||
|
||||
if (!insn)
|
||||
if (!first)
|
||||
{
|
||||
set_insn_error (0, _("Unrecognized opcode"));
|
||||
return;
|
||||
@ -13146,45 +13181,9 @@ mips16_ip (char *str, struct mips_cl_insn *ip)
|
||||
if (!tokens)
|
||||
return;
|
||||
|
||||
for (;;)
|
||||
{
|
||||
bfd_boolean ok;
|
||||
bfd_boolean more_alts;
|
||||
if (!match_mips16_insns (insn, first, tokens))
|
||||
set_insn_error (0, _("Illegal operands"));
|
||||
|
||||
gas_assert (strcmp (insn->name, first->name) == 0);
|
||||
|
||||
ok = is_opcode_valid_16 (insn);
|
||||
more_alts = (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes]
|
||||
&& strcmp (insn[0].name, insn[1].name) == 0);
|
||||
if (! ok)
|
||||
{
|
||||
if (more_alts)
|
||||
{
|
||||
++insn;
|
||||
continue;
|
||||
}
|
||||
else
|
||||
{
|
||||
set_insn_error_ss
|
||||
(0, _("Opcode not supported on this processor: %s (%s)"),
|
||||
mips_cpu_info_from_arch (mips_opts.arch)->name,
|
||||
mips_cpu_info_from_isa (mips_opts.isa)->name);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (match_mips16_insn (ip, insn, tokens))
|
||||
break;
|
||||
|
||||
/* Args don't match. */
|
||||
set_insn_error (0, _("Illegal operands"));
|
||||
if (more_alts)
|
||||
{
|
||||
++insn;
|
||||
continue;
|
||||
}
|
||||
break;
|
||||
}
|
||||
obstack_free (&mips_operand_tokens, tokens);
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user