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x86-64: Always display suffix for %LQ in 64bit

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In 64bit, assembler generates a warning for "sysret":

$ echo sysret | as --64 -o x.o -
{standard input}: Assembler messages:
{standard input}:1: Warning: no instruction mnemonic suffix given and no register operands; using default for `sysret'

Always display suffix for %LQ in 64bit to display "sysretl".

gas/

	PR binutils/26704
	* testsuite/gas/i386/noreg64-data16.d: Expect sysretl instead of
	sysret.
	* testsuite/gas/i386/noreg64.d: Likewise.
	* testsuite/gas/i386/x86-64-intel64.d: Likewise.
	* testsuite/gas/i386/x86-64-opcode.d: Likewise.

opcodes/

	PR binutils/26704
	* i386-dis.c (putop): Always display suffix for %LQ in 64bit.
This commit is contained in:
H.J. Lu 2020-10-05 05:27:58 -07:00
parent 0e9f3bf126
commit 5b316d90e4
7 changed files with 19 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
gas/ChangeLog
View File

@ -1,3 +1,12 @@
2020-10-05 H.J. Lu <hongjiu.lu@intel.com>
PR binutils/26704
* testsuite/gas/i386/noreg64-data16.d: Expect sysretl instead of
sysret.
* testsuite/gas/i386/noreg64.d: Likewise.
* testsuite/gas/i386/x86-64-intel64.d: Likewise.
* testsuite/gas/i386/x86-64-opcode.d: Likewise.
2020-10-05 H.J. Lu <hongjiu.lu@intel.com>
PR binutils/26705

2
gas/testsuite/gas/i386/noreg64-data16.d
View File

@ -150,7 +150,7 @@ Disassembly of section .text:
*[a-f0-9]+: 66 81 28 89 00 subw \$0x89,\(%rax\)
*[a-f0-9]+: 66 81 28 34 12 subw \$0x1234,\(%rax\)
*[a-f0-9]+: 66 81 28 78 56 subw \$0x5678,\(%rax\)
*[a-f0-9]+: 66 0f 07 data16 sysret *
*[a-f0-9]+: 66 0f 07 data16 sysretl *
*[a-f0-9]+: 66 f7 00 89 00 testw \$0x89,\(%rax\)
*[a-f0-9]+: 66 f7 00 34 12 testw \$0x1234,\(%rax\)
*[a-f0-9]+: 66 f7 00 78 56 testw \$0x5678,\(%rax\)

2
gas/testsuite/gas/i386/noreg64.d
View File

@ -151,7 +151,7 @@ Disassembly of section .text:
*[a-f0-9]+: 81 28 89 00 00 00 subl \$0x89,\(%rax\)
*[a-f0-9]+: 81 28 34 12 00 00 subl \$0x1234,\(%rax\)
*[a-f0-9]+: 81 28 78 56 34 12 subl \$0x12345678,\(%rax\)
*[a-f0-9]+: 0f 07 sysret *
*[a-f0-9]+: 0f 07 sysretl *
*[a-f0-9]+: f7 00 89 00 00 00 testl \$0x89,\(%rax\)
*[a-f0-9]+: f7 00 34 12 00 00 testl \$0x1234,\(%rax\)
*[a-f0-9]+: f7 00 78 56 34 12 testl \$0x12345678,\(%rax\)

2
gas/testsuite/gas/i386/x86-64-intel64.d
View File

@ -15,7 +15,7 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 48 ff 18 rex\.W lcall \*\(%rax\)
[ ]*[a-f0-9]+: 48 ff 29 rex\.W ljmp \*\(%rcx\)
[ ]*[a-f0-9]+: 0f 05 syscall
[ ]*[a-f0-9]+: 0f 07 sysret
[ ]*[a-f0-9]+: 0f 07 sysretl
[ ]*[a-f0-9]+: 48 0f 07 sysretq *
[ ]*[a-f0-9]+: 48 0f b4 01 lfs \(%rcx\),%rax
[ ]*[a-f0-9]+: 48 0f b4 01 lfs \(%rcx\),%rax

2
gas/testsuite/gas/i386/x86-64-opcode.d
View File

@ -321,7 +321,7 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 66 0f 00 c8 str %ax
[ ]*[a-f0-9]+: 0f 00 08 str \(%rax\)
[ ]*[a-f0-9]+: 0f 05 syscall
[ ]*[a-f0-9]+: 0f 07 sysret
[ ]*[a-f0-9]+: 0f 07 sysretl
[ ]*[a-f0-9]+: 48 0f 07 sysretq *
[ ]*[a-f0-9]+: 0f 01 f8 swapgs
[ ]*[a-f0-9]+: 66 68 22 22 pushw \$0x2222

5
opcodes/ChangeLog
View File

@ -1,3 +1,8 @@
2020-10-05 H.J. Lu <hongjiu.lu@intel.com>
PR binutils/26704
* i386-dis.c (putop): Always display suffix for %LQ in 64bit.
2020-10-05 H.J. Lu <hongjiu.lu@intel.com>
PR binutils/26705

2
opcodes/i386-dis.c
View File

@ -10870,7 +10870,7 @@ putop (const char *in_template, int sizeflag)
USED_REX (REX_W);
*obufp++ = 'q';
}
else if((address_mode == mode_64bit && need_modrm && cond)
else if((address_mode == mode_64bit && cond)
|| (sizeflag & SUFFIX_ALWAYS))
*obufp++ = intel_syntax? 'd' : 'l';
}