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gas/
2006-09-23 H.J. Lu <hongjiu.lu@intel.com> PR binutils/3235 * config/tc-i386.c (match_template): Check address size prefix to turn Disp64/Disp32/Disp16 operand into Disp32/Disp16/Disp32 operand. gas/testsuite/ 2006-09-23 H.J. Lu <hongjiu.lu@intel.com> PR binutils/3235 * gas/i386/addr16.d: New file. * gas/i386/addr16.s: Likewise. * gas/i386/addr32.d: Likewise. * gas/i386/addr32.s: Likewise. * gas/i386/i386.exp: Add "addr16" and "addr32". * gas/i386/x86-64-addr32.s: Add tests for "add32 mov". * gas/i386/x86-64-addr32.d: Updated. opcodes/ 2006-09-23 H.J. Lu <hongjiu.lu@intel.com> PR binutils/3235 * i386-dis.c (OP_OFF64): Get 32bit offset if there is an address size prefix.
This commit is contained in:
H.J. Lu
parent
b41e175056
commit
539e75adb5
@ -1,3 +1,10 @@
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2006-09-23 H.J. Lu <hongjiu.lu@intel.com>
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PR binutils/3235
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* config/tc-i386.c (match_template): Check address size prefix
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to turn Disp64/Disp32/Disp16 operand into Disp32/Disp16/Disp32
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operand.
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2006-09-22 Alan Modra <amodra@bigpond.net.au>
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* config/tc-ppc.c (ppc_symbol_chars): Remove '+' and '-'.
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@ -2563,6 +2563,8 @@ match_template ()
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unsigned int overlap0, overlap1, overlap2;
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unsigned int found_reverse_match;
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int suffix_check;
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unsigned int operand_types [3];
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int addr_prefix_disp;
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#define MATCH(overlap, given, template) \
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((overlap & ~JumpAbsolute) \
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@ -2581,6 +2583,10 @@ match_template ()
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overlap1 = 0;
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overlap2 = 0;
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found_reverse_match = 0;
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operand_types [0] = 0;
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operand_types [1] = 0;
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operand_types [2] = 0;
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addr_prefix_disp = -1;
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suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
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? No_bSuf
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: (i.suffix == WORD_MNEM_SUFFIX
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@ -2596,6 +2602,8 @@ match_template ()
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for (t = current_templates->start; t < current_templates->end; t++)
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{
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addr_prefix_disp = -1;
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/* Must have right number of operands. */
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if (i.operands != t->operands)
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continue;
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@ -2606,6 +2614,10 @@ match_template ()
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&& (t->opcode_modifier & IgnoreSize)))
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continue;
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operand_types [0] = t->operand_types [0];
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operand_types [1] = t->operand_types [1];
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operand_types [2] = t->operand_types [2];
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/* In general, don't allow 64-bit operands in 32-bit mode. */
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if (i.suffix == QWORD_MNEM_SUFFIX
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&& flag_code != CODE_64BIT
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@ -2613,8 +2625,8 @@ match_template ()
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? (!(t->opcode_modifier & IgnoreSize)
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&& !intel_float_operand (t->name))
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: intel_float_operand (t->name) != 2)
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&& (!(t->operand_types[0] & (RegMMX | RegXMM))
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|| !(t->operand_types[t->operands > 1] & (RegMMX | RegXMM)))
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&& (!(operand_types[0] & (RegMMX | RegXMM))
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|| !(operand_types[t->operands > 1] & (RegMMX | RegXMM)))
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&& (t->base_opcode != 0x0fc7
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|| t->extension_opcode != 1 /* cmpxchg8b */))
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continue;
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@ -2628,41 +2640,76 @@ match_template ()
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break;
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}
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overlap0 = i.types[0] & t->operand_types[0];
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/* Address size prefix will turn Disp64/Disp32/Disp16 operand
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into Disp32/Disp16/Disp32 operand. */
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if (i.prefix[ADDR_PREFIX] != 0)
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{
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unsigned int j, DispOn = 0, DispOff = 0;
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switch (flag_code)
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{
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case CODE_16BIT:
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DispOn = Disp32;
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DispOff = Disp16;
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break;
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case CODE_32BIT:
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DispOn = Disp16;
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DispOff = Disp32;
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break;
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case CODE_64BIT:
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DispOn = Disp32;
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DispOff = Disp64;
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break;
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}
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for (j = 0; j < 3; j++)
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{
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/* There should be only one Disp operand. */
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if ((operand_types[j] & DispOff))
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{
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addr_prefix_disp = j;
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operand_types[j] |= DispOn;
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operand_types[j] &= ~DispOff;
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break;
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}
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}
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}
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overlap0 = i.types[0] & operand_types[0];
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switch (t->operands)
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{
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case 1:
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if (!MATCH (overlap0, i.types[0], t->operand_types[0]))
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if (!MATCH (overlap0, i.types[0], operand_types[0]))
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continue;
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break;
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case 2:
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case 3:
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overlap1 = i.types[1] & t->operand_types[1];
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if (!MATCH (overlap0, i.types[0], t->operand_types[0])
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|| !MATCH (overlap1, i.types[1], t->operand_types[1])
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overlap1 = i.types[1] & operand_types[1];
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if (!MATCH (overlap0, i.types[0], operand_types[0])
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|| !MATCH (overlap1, i.types[1], operand_types[1])
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/* monitor in SSE3 is a very special case. The first
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register and the second register may have different
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sizes. */
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|| !((t->base_opcode == 0x0f01
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&& t->extension_opcode == 0xc8)
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|| CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
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t->operand_types[0],
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operand_types[0],
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overlap1, i.types[1],
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t->operand_types[1])))
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operand_types[1])))
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{
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/* Check if other direction is valid ... */
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if ((t->opcode_modifier & (D | FloatD)) == 0)
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continue;
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/* Try reversing direction of operands. */
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overlap0 = i.types[0] & t->operand_types[1];
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overlap1 = i.types[1] & t->operand_types[0];
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if (!MATCH (overlap0, i.types[0], t->operand_types[1])
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|| !MATCH (overlap1, i.types[1], t->operand_types[0])
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overlap0 = i.types[0] & operand_types[1];
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overlap1 = i.types[1] & operand_types[0];
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if (!MATCH (overlap0, i.types[0], operand_types[1])
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|| !MATCH (overlap1, i.types[1], operand_types[0])
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|| !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
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t->operand_types[1],
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operand_types[1],
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overlap1, i.types[1],
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t->operand_types[0]))
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operand_types[0]))
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{
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/* Does not match either direction. */
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continue;
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@ -2678,12 +2725,12 @@ match_template ()
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reverse match 3 operand instructions, and all 3
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operand instructions only need to be checked for
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register consistency between operands 2 and 3. */
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overlap2 = i.types[2] & t->operand_types[2];
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if (!MATCH (overlap2, i.types[2], t->operand_types[2])
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overlap2 = i.types[2] & operand_types[2];
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if (!MATCH (overlap2, i.types[2], operand_types[2])
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|| !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1],
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t->operand_types[1],
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operand_types[1],
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overlap2, i.types[2],
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t->operand_types[2]))
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operand_types[2]))
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continue;
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}
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@ -2711,7 +2758,7 @@ match_template ()
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{
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if (!intel_syntax
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&& ((i.types[0] & JumpAbsolute)
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!= (t->operand_types[0] & JumpAbsolute)))
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!= (operand_types[0] & JumpAbsolute)))
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{
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as_warn (_("indirect %s without `*'"), t->name);
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}
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@ -2727,6 +2774,11 @@ match_template ()
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/* Copy the template we found. */
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i.tm = *t;
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if (addr_prefix_disp != -1)
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i.tm.operand_types[addr_prefix_disp]
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= operand_types[addr_prefix_disp];
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if (found_reverse_match)
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{
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/* If we found a reverse match we must alter the opcode
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@ -2735,8 +2787,8 @@ match_template ()
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i.tm.base_opcode ^= found_reverse_match;
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i.tm.operand_types[0] = t->operand_types[1];
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i.tm.operand_types[1] = t->operand_types[0];
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i.tm.operand_types[0] = operand_types[1];
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i.tm.operand_types[1] = operand_types[0];
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}
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return 1;
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@ -1,3 +1,16 @@
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2006-09-23 H.J. Lu <hongjiu.lu@intel.com>
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PR binutils/3235
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* gas/i386/addr16.d: New file.
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* gas/i386/addr16.s: Likewise.
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* gas/i386/addr32.d: Likewise.
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* gas/i386/addr32.s: Likewise.
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* gas/i386/i386.exp: Add "addr16" and "addr32".
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* gas/i386/x86-64-addr32.s: Add tests for "add32 mov".
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* gas/i386/x86-64-addr32.d: Updated.
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2006-09-20 Kai Tietz <Kai.Tietz@onevision.com>
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* gas/all/gas.exp: Add support for x86_64-*-mingw64.
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15
gas/testsuite/gas/i386/addr16.d
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15
gas/testsuite/gas/i386/addr16.d
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@ -0,0 +1,15 @@
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#objdump: -drw
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#name: i386 16-bit addressing in 32-bit mode.
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.*: +file format .*
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Disassembly of section .text:
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0+000 <.text>:
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[ ]*0:[ ]+67 a0 98 08 [ ]+addr16[ ]+mov[ ]+0x898,%al
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[ ]*4:[ ]+67 66 a1 98 08 [ ]+addr16[ ]+mov[ ]+0x898,%ax
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[ ]*9:[ ]+67 a1 98 08 [ ]+addr16[ ]+mov[ ]+0x898,%eax
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[ ]*d:[ ]+67 a2 98 08 [ ]+addr16[ ]+mov[ ]+%al,0x898
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[ ]*11:[ ]+67 66 a3 98 08 [ ]+addr16[ ]+mov[ ]+%ax,0x898
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[ ]*16:[ ]+67 a3 98 08[ ]+addr16[ ]+mov[ ]+%eax,0x898
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#pass
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7
gas/testsuite/gas/i386/addr16.s
Normal file
7
gas/testsuite/gas/i386/addr16.s
Normal file
@ -0,0 +1,7 @@
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.text
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addr16 mov 0x0898,%al
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addr16 mov 0x0898,%ax
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addr16 mov 0x0898,%eax
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addr16 mov %al,0x0898
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addr16 mov %ax,0x0898
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addr16 mov %eax,0x0898
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15
gas/testsuite/gas/i386/addr32.d
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15
gas/testsuite/gas/i386/addr32.d
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@ -0,0 +1,15 @@
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#objdump: -drw -mi8086
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#name: i386 32-bit addressing in 16-bit mode.
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.*: +file format .*
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Disassembly of section .text:
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0+000 <.text>:
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[ ]*0:[ ]+67 a0 98 08 60 00[ ]+addr32[ ]+mov[ ]+0x600898,%al
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[ ]*6:[ ]+67 a1 98 08 60 00[ ]+addr32[ ]+mov[ ]+0x600898,%ax
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[ ]*c:[ ]+67 66 a1 98 08 60 00[ ]+addr32[ ]+mov[ ]+0x600898,%eax
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[ ]*13:[ ]+67 a2 98 08 60 00[ ]+addr32[ ]+mov[ ]+%al,0x600898
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[ ]*19:[ ]+67 a3 98 08 60 00[ ]+addr32[ ]+mov[ ]+%ax,0x600898
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[ ]*1f:[ ]+67 66 a3 98 08 60 00[ ]+addr32[ ]+mov[ ]+%eax,0x600898
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#pass
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8
gas/testsuite/gas/i386/addr32.s
Normal file
8
gas/testsuite/gas/i386/addr32.s
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@ -0,0 +1,8 @@
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.text
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.code16
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addr32 mov 0x600898,%al
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addr32 mov 0x600898,%ax
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addr32 mov 0x600898,%eax
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addr32 mov %al,0x600898
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addr32 mov %ax,0x600898
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addr32 mov %eax,0x600898
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@ -81,6 +81,8 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
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run_dump_test "nops-2"
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run_dump_test "nops-2-i386"
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run_dump_test "nops-2-merom"
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run_dump_test "addr16"
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run_dump_test "addr32"
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# These tests require support for 8 and 16 bit relocs,
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# so we only run them for ELF and COFF targets.
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@ -11,4 +11,12 @@ Disassembly of section .text:
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[ ]*8:[ ]+67 49 8d 80 00 00 00 00[ ]+addr32[ ]+lea[ ]+0x0\(%r8d?\),%rax.*
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[ ]*10:[ ]+67 48 8d 05 00 00 00 00[ ]+addr32[ ]+lea[ ]+0\(%[re]ip\),%rax.*
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[ ]*18:[ ]+67 48 8d 04 25 00 00 00 00[ ]+addr32[ ]+lea[ ]+0x0,%rax.*
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[ ]*21:[ ]+67 a0 98 08 60 00[ ]+addr32[ ]+mov[ ]+0x600898,%al
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[ ]*27:[ ]+67 66 a1 98 08 60 00[ ]+addr32[ ]+mov[ ]+0x600898,%ax
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[ ]*2e:[ ]+67 a1 98 08 60 00[ ]+addr32[ ]+mov[ ]+0x600898,%eax
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[ ]*34:[ ]+67 48 a1 98 08 60 00[ ]+addr32[ ]+mov[ ]+0x600898,%rax
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[ ]*3b:[ ]+67 a2 98 08 60 00[ ]+addr32[ ]+mov[ ]+%al,0x600898
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[ ]*41:[ ]+67 66 a3 98 08 60 00[ ]+addr32[ ]+mov[ ]+%ax,0x600898
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[ ]*48:[ ]+67 a3 98 08 60 00[ ]+addr32[ ]+mov[ ]+%eax,0x600898
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[ ]*4e:[ ]+67 48 a3 98 08 60 00[ ]+addr32[ ]+mov[ ]+%rax,0x600898
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#pass
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@ -3,3 +3,11 @@
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lea symbol(%r8d), %rax
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addr32 lea symbol(%rip), %rax
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addr32 lea symbol, %rax
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addr32 mov 0x600898,%al
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addr32 mov 0x600898,%ax
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addr32 mov 0x600898,%eax
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addr32 mov 0x600898,%rax
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addr32 mov %al,0x600898
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addr32 mov %ax,0x600898
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addr32 mov %eax,0x600898
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addr32 mov %rax,0x600898
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@ -1,3 +1,9 @@
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2006-09-23 H.J. Lu <hongjiu.lu@intel.com>
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PR binutils/3235
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* i386-dis.c (OP_OFF64): Get 32bit offset if there is an
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address size prefix.
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2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
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* score-dis.c: New file.
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@ -4693,7 +4693,8 @@ OP_OFF64 (int bytemode, int sizeflag)
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{
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bfd_vma off;
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if (address_mode != mode_64bit)
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if (address_mode != mode_64bit
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|| (prefixes & PREFIX_ADDR))
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{
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OP_OFF (bytemode, sizeflag);
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return;
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