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aarch64: Add support for predicate-as-counter registers
SME2 adds a new format for the existing SVE predicate registers: predicates as counters rather than predicates as masks. In assembly code, operands that interpret predicates as counters are written pn<N> rather than p<N>. This patch adds support for these registers and extends some existing instructions to support them. Since the new forms are just a programmer convenience, there's no need to make them more restrictive than the earlier predicate-as-mask forms.
This commit is contained in:
Richard Sandiford
parent
586c62819f
commit
503fae1299
@ -307,6 +307,7 @@ struct reloc_entry
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BASIC_REG_TYPE(V) /* v[0-31] */ \
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BASIC_REG_TYPE(Z) /* z[0-31] */ \
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BASIC_REG_TYPE(P) /* p[0-15] */ \
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BASIC_REG_TYPE(PN) /* pn[0-15] */ \
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BASIC_REG_TYPE(ZA) /* za */ \
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BASIC_REG_TYPE(ZAT) /* za[0-15] (ZA tile) */ \
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BASIC_REG_TYPE(ZATH) /* za[0-15]h (ZA tile horizontal slice) */ \
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@ -440,6 +441,16 @@ get_reg_expected_msg (unsigned int mask, unsigned int seen)
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| reg_type_masks[REG_TYPE_ZATHV])))
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return N_("expected 'za' rather than a ZA tile at operand %d");
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if ((mask & reg_type_masks[REG_TYPE_PN])
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&& (seen & reg_type_masks[REG_TYPE_P]))
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return N_("expected a predicate-as-counter rather than predicate-as-mask"
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" register at operand %d");
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if ((mask & reg_type_masks[REG_TYPE_P])
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&& (seen & reg_type_masks[REG_TYPE_PN]))
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return N_("expected a predicate-as-mask rather than predicate-as-counter"
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" register at operand %d");
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/* Integer, zero and stack registers. */
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if (mask == reg_type_masks[REG_TYPE_R_64])
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return N_("expected a 64-bit integer register at operand %d");
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@ -456,7 +467,12 @@ get_reg_expected_msg (unsigned int mask, unsigned int seen)
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return N_("expected an Advanced SIMD vector register at operand %d");
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if (mask == reg_type_masks[REG_TYPE_Z])
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return N_("expected an SVE vector register at operand %d");
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if (mask == reg_type_masks[REG_TYPE_P])
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if (mask == reg_type_masks[REG_TYPE_P]
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|| mask == (reg_type_masks[REG_TYPE_P] | reg_type_masks[REG_TYPE_PN]))
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/* Use this error for "predicate-as-mask only" and "either kind of
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predicate". We report a more specific error if P is used where
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PN is expected, and vice versa, so the issue at this point is
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"predicate-like" vs. "not predicate-like". */
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return N_("expected an SVE predicate register at operand %d");
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if (mask == reg_type_masks[REG_TYPE_VZ])
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return N_("expected a vector register at operand %d");
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@ -1127,6 +1143,7 @@ aarch64_valid_suffix_char_p (aarch64_reg_type type, char ch)
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return ch == '.';
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case REG_TYPE_P:
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case REG_TYPE_PN:
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return ch == '.' || ch == '/';
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default:
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@ -6609,6 +6626,13 @@ parse_operands (char *str, const aarch64_opcode *opcode)
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reg_type = REG_TYPE_Z;
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goto vector_reg;
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case AARCH64_OPND_SVE_PNd:
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case AARCH64_OPND_SVE_PNg4_10:
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case AARCH64_OPND_SVE_PNn:
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case AARCH64_OPND_SVE_PNt:
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reg_type = REG_TYPE_PN;
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goto vector_reg;
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case AARCH64_OPND_Va:
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case AARCH64_OPND_Vd:
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case AARCH64_OPND_Vn:
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@ -6622,7 +6646,9 @@ parse_operands (char *str, const aarch64_opcode *opcode)
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goto failure;
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info->reg.regno = reg->number;
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if ((reg_type == REG_TYPE_P || reg_type == REG_TYPE_Z)
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if ((reg_type == REG_TYPE_P
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|| reg_type == REG_TYPE_PN
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|| reg_type == REG_TYPE_Z)
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&& vectype.type == NT_invtype)
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/* Unqualified P and Z registers are allowed in certain
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contexts. Rely on F_STRICT qualifier checking to catch
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@ -8343,9 +8369,12 @@ static const reg_entry reg_names[] = {
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/* SVE vector registers. */
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REGSET (z, Z), REGSET (Z, Z),
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/* SVE predicate registers. */
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/* SVE predicate(-as-mask) registers. */
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REGSET16 (p, P), REGSET16 (P, P),
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/* SVE predicate-as-counter registers. */
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REGSET16 (pn, PN), REGSET16 (PN, PN),
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/* SME ZA. We model this as a register because it acts syntactically
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like ZA0H, supporting qualifier suffixes and indexing. */
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REGDEF (za, 0, ZA), REGDEF (ZA, 0, ZA),
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3
gas/testsuite/gas/aarch64/sve-sme2-1-invalid.d
Normal file
3
gas/testsuite/gas/aarch64/sve-sme2-1-invalid.d
Normal file
@ -0,0 +1,3 @@
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#as: -march=armv8-a
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#source: sve-sme2-1-invalid.s
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#error_output: sve-sme2-1-invalid.l
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51
gas/testsuite/gas/aarch64/sve-sme2-1-invalid.l
Normal file
51
gas/testsuite/gas/aarch64/sve-sme2-1-invalid.l
Normal file
@ -0,0 +1,51 @@
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[^ :]+: Assembler messages:
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[^ :]+:[0-9]+: Error: operand mismatch -- `pfalse pn0\.h'
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[^ :]+:[0-9]+: Info: did you mean this\?
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[^ :]+:[0-9]+: Info: pfalse pn0\.b
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[^ :]+:[0-9]+: Error: operand mismatch -- `pfalse pn0\.s'
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[^ :]+:[0-9]+: Info: did you mean this\?
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[^ :]+:[0-9]+: Info: pfalse pn0\.b
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[^ :]+:[0-9]+: Error: operand mismatch -- `pfalse pn0\.d'
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[^ :]+:[0-9]+: Info: did you mean this\?
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[^ :]+:[0-9]+: Info: pfalse pn0\.b
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[^ :]+:[0-9]+: Error: operand mismatch -- `pfalse pn0\.q'
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[^ :]+:[0-9]+: Info: did you mean this\?
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[^ :]+:[0-9]+: Info: pfalse pn0\.b
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[^ :]+:[0-9]+: Error: operand mismatch -- `pfalse pn0'
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[^ :]+:[0-9]+: Info: did you mean this\?
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[^ :]+:[0-9]+: Info: pfalse pn0\.b
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[^ :]+:[0-9]+: Error: expected a predicate-as-counter rather than predicate-as-mask register at operand 2 -- `mov pn0\.b,p0\.b'
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[^ :]+:[0-9]+: Error: expected a predicate-as-mask rather than predicate-as-counter register at operand 2 -- `mov p0\.b,pn0\.b'
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[^ :]+:[0-9]+: Error: operand mismatch -- `mov pn0\.b,pn1\.h'
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[^ :]+:[0-9]+: Info: did you mean this\?
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[^ :]+:[0-9]+: Info: mov pn0\.b, pn1\.b
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[^ :]+:[0-9]+: Error: operand mismatch -- `mov pn0\.h,pn1\.b'
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[^ :]+:[0-9]+: Info: did you mean this\?
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[^ :]+:[0-9]+: Info: mov pn0\.b, pn1\.b
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[^ :]+:[0-9]+: Error: operand mismatch -- `mov pn0\.h,pn1\.h'
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[^ :]+:[0-9]+: Info: did you mean this\?
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[^ :]+:[0-9]+: Info: mov pn0\.b, pn1\.b
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[^ :]+:[0-9]+: Error: operand mismatch -- `mov pn0\.s,pn1\.s'
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[^ :]+:[0-9]+: Info: did you mean this\?
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[^ :]+:[0-9]+: Info: mov pn0\.b, pn1\.b
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[^ :]+:[0-9]+: Error: operand mismatch -- `mov pn0\.d,pn1\.d'
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[^ :]+:[0-9]+: Info: did you mean this\?
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[^ :]+:[0-9]+: Info: mov pn0\.b, pn1\.b
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[^ :]+:[0-9]+: Error: operand mismatch -- `mov pn0\.q,pn1\.q'
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[^ :]+:[0-9]+: Info: did you mean this\?
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[^ :]+:[0-9]+: Info: mov pn0\.b, pn1\.b
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[^ :]+:[0-9]+: Error: operand mismatch -- `mov pn0,pn1'
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[^ :]+:[0-9]+: Info: did you mean this\?
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[^ :]+:[0-9]+: Info: mov pn0\.b, pn1\.b
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[^ :]+:[0-9]+: Error: operand mismatch -- `ldr pn0\.b,\[x0\]'
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[^ :]+:[0-9]+: Info: did you mean this\?
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[^ :]+:[0-9]+: Info: ldr pn0, \[x0\]
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[^ :]+:[0-9]+: Error: invalid base register at operand 2 -- `ldr pn0\.b,\[xzr\]'
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[^ :]+:[0-9]+: Error: immediate offset out of range -256 to 255 at operand 2 -- `ldr pn0,\[x0,#-257,mul vl\]'
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[^ :]+:[0-9]+: Error: immediate offset out of range -256 to 255 at operand 2 -- `ldr pn0,\[x0,#256,mul vl\]'
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[^ :]+:[0-9]+: Error: operand mismatch -- `str pn0\.b,\[x0\]'
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[^ :]+:[0-9]+: Info: did you mean this\?
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[^ :]+:[0-9]+: Info: str pn0, \[x0\]
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[^ :]+:[0-9]+: Error: invalid base register at operand 2 -- `str pn0\.b,\[xzr\]'
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[^ :]+:[0-9]+: Error: immediate offset out of range -256 to 255 at operand 2 -- `str pn0,\[x0,#-257,mul vl\]'
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[^ :]+:[0-9]+: Error: immediate offset out of range -256 to 255 at operand 2 -- `str pn0,\[x0,#256,mul vl\]'
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25
gas/testsuite/gas/aarch64/sve-sme2-1-invalid.s
Normal file
25
gas/testsuite/gas/aarch64/sve-sme2-1-invalid.s
Normal file
@ -0,0 +1,25 @@
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pfalse pn0.h
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pfalse pn0.s
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pfalse pn0.d
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pfalse pn0.q
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pfalse pn0
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mov pn0.b, p0.b
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mov p0.b, pn0.b
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mov pn0.b, pn1.h
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mov pn0.h, pn1.b
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mov pn0.h, pn1.h
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mov pn0.s, pn1.s
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mov pn0.d, pn1.d
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mov pn0.q, pn1.q
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mov pn0, pn1
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ldr pn0.b, [x0]
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ldr pn0.b, [xzr]
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ldr pn0, [x0, #-257, mul vl]
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ldr pn0, [x0, #256, mul vl]
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str pn0.b, [x0]
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str pn0.b, [xzr]
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str pn0, [x0, #-257, mul vl]
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str pn0, [x0, #256, mul vl]
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3
gas/testsuite/gas/aarch64/sve-sme2-1-noarch.d
Normal file
3
gas/testsuite/gas/aarch64/sve-sme2-1-noarch.d
Normal file
@ -0,0 +1,3 @@
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#as: -march=armv8-a
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#source: sve-sme2-1.s
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#error_output: sve-sme2-1-noarch.l
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25
gas/testsuite/gas/aarch64/sve-sme2-1-noarch.l
Normal file
25
gas/testsuite/gas/aarch64/sve-sme2-1-noarch.l
Normal file
@ -0,0 +1,25 @@
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[^ :]+: Assembler messages:
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[^ :]+:[0-9]+: Error: selected processor does not support `pfalse pn0\.b'
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[^ :]+:[0-9]+: Error: selected processor does not support `pfalse PN0\.B'
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[^ :]+:[0-9]+: Error: selected processor does not support `pfalse pn5\.b'
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[^ :]+:[0-9]+: Error: selected processor does not support `pfalse pn15\.b'
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[^ :]+:[0-9]+: Error: selected processor does not support `mov pn0\.b,pn0\.b'
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[^ :]+:[0-9]+: Error: selected processor does not support `mov pn0\.b,pn15\.b'
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[^ :]+:[0-9]+: Error: selected processor does not support `mov pn15\.b,pn0\.b'
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[^ :]+:[0-9]+: Error: selected processor does not support `mov pn3\.b,pn12\.b'
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[^ :]+:[0-9]+: Error: selected processor does not support `ldr pn0,\[x0\]'
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[^ :]+:[0-9]+: Error: selected processor does not support `ldr pn15,\[x0\]'
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[^ :]+:[0-9]+: Error: selected processor does not support `ldr pn15,\[x30\]'
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[^ :]+:[0-9]+: Error: selected processor does not support `ldr pn0,\[sp\]'
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[^ :]+:[0-9]+: Error: selected processor does not support `ldr pn0,\[x0,#0,mul vl\]'
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[^ :]+:[0-9]+: Error: selected processor does not support `ldr pn0,\[x0,#-256,mul vl\]'
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[^ :]+:[0-9]+: Error: selected processor does not support `ldr pn0,\[x0,#255,mul vl\]'
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[^ :]+:[0-9]+: Error: selected processor does not support `ldr pn11,\[x14,#211,mul vl\]'
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[^ :]+:[0-9]+: Error: selected processor does not support `str pn0,\[x0\]'
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[^ :]+:[0-9]+: Error: selected processor does not support `str pn15,\[x0\]'
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[^ :]+:[0-9]+: Error: selected processor does not support `str pn15,\[x30\]'
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[^ :]+:[0-9]+: Error: selected processor does not support `str pn0,\[sp\]'
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[^ :]+:[0-9]+: Error: selected processor does not support `str pn0,\[x0,#0,mul vl\]'
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[^ :]+:[0-9]+: Error: selected processor does not support `str pn0,\[x0,#-256,mul vl\]'
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[^ :]+:[0-9]+: Error: selected processor does not support `str pn0,\[x0,#255,mul vl\]'
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[^ :]+:[0-9]+: Error: selected processor does not support `str pn5,\[x28,#-56,mul vl\]'
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33
gas/testsuite/gas/aarch64/sve-sme2-1.d
Normal file
33
gas/testsuite/gas/aarch64/sve-sme2-1.d
Normal file
@ -0,0 +1,33 @@
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#as: -march=armv8-a+sve
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#objdump: -dr
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[^:]+: file format .*
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[^:]+:
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[^:]+:
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[^:]+: 2518e400 pfalse p0\.b
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[^:]+: 2518e400 pfalse p0\.b
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[^:]+: 2518e405 pfalse p5\.b
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[^:]+: 2518e40f pfalse p15\.b
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[^:]+: 25804000 mov p0\.b, p0\.b
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[^:]+: 258f7de0 mov p0\.b, p15\.b
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[^:]+: 2580400f mov p15\.b, p0\.b
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[^:]+: 258c7183 mov p3\.b, p12\.b
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[^:]+: 85800000 ldr p0, \[x0\]
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[^:]+: 8580000f ldr p15, \[x0\]
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[^:]+: 858003cf ldr p15, \[x30\]
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[^:]+: 858003e0 ldr p0, \[sp\]
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[^:]+: 85800000 ldr p0, \[x0\]
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[^:]+: 85a00000 ldr p0, \[x0, #-256, mul vl\]
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[^:]+: 859f1c00 ldr p0, \[x0, #255, mul vl\]
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[^:]+: 859a0dcb ldr p11, \[x14, #211, mul vl\]
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[^:]+: e5800000 str p0, \[x0\]
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[^:]+: e580000f str p15, \[x0\]
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[^:]+: e58003cf str p15, \[x30\]
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[^:]+: e58003e0 str p0, \[sp\]
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[^:]+: e5800000 str p0, \[x0\]
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[^:]+: e5a00000 str p0, \[x0, #-256, mul vl\]
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[^:]+: e59f1c00 str p0, \[x0, #255, mul vl\]
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[^:]+: e5b90385 str p5, \[x28, #-56, mul vl\]
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27
gas/testsuite/gas/aarch64/sve-sme2-1.s
Normal file
27
gas/testsuite/gas/aarch64/sve-sme2-1.s
Normal file
@ -0,0 +1,27 @@
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pfalse pn0.b
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PFALSE PN0.B
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pfalse pn5.b
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pfalse pn15.b
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mov pn0.b, pn0.b
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mov pn0.b, pn15.b
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mov pn15.b, pn0.b
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mov pn3.b, pn12.b
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ldr pn0, [x0]
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ldr pn15, [x0]
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ldr pn15, [x30]
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ldr pn0, [sp]
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ldr pn0, [x0, #0, mul vl]
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ldr pn0, [x0, #-256, mul vl]
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ldr pn0, [x0, #255, mul vl]
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ldr pn11, [x14, #211, mul vl]
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str pn0, [x0]
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str pn15, [x0]
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str pn15, [x30]
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str pn0, [sp]
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str pn0, [x0, #0, mul vl]
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str pn0, [x0, #-256, mul vl]
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str pn0, [x0, #255, mul vl]
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str pn5, [x28, #-56, mul vl]
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3
gas/testsuite/gas/aarch64/sve2-sme2-1-invalid.d
Normal file
3
gas/testsuite/gas/aarch64/sve2-sme2-1-invalid.d
Normal file
@ -0,0 +1,3 @@
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#as: -march=armv8-a
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#source: sve2-sme2-1-invalid.s
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#error_output: sve2-sme2-1-invalid.l
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9
gas/testsuite/gas/aarch64/sve2-sme2-1-invalid.l
Normal file
9
gas/testsuite/gas/aarch64/sve2-sme2-1-invalid.l
Normal file
@ -0,0 +1,9 @@
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[^ :]+: Assembler messages:
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[^ :]+:[0-9]+: Error: expected a predicate-as-counter rather than predicate-as-mask register at operand 2 -- `psel pn0,p0,p0\.b\[w12,0\]'
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[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 1 -- `psel pn,pn0,p0\.b\[w12,0\]'
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[^ :]+:[0-9]+: Error: expected a predicate-as-mask rather than predicate-as-counter register at operand 3 -- `psel p0,p0,pn0\.b\[w12,0\]'
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[^ :]+:[0-9]+: Error: expected a predicate-as-mask rather than predicate-as-counter register at operand 3 -- `psel pn0,pn0,pn0\.b\[w12,0\]'
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[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 3 -- `psel pn0,pn0,p0\.b\[w11,0\]'
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[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 3 -- `psel pn0,pn0,p0\.b\[w16,0\]'
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[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 15 at operand 3 -- `psel pn0,pn0,p0\.b\[w12,-1\]'
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[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 15 at operand 3 -- `psel pn0,pn0,p0\.b\[w12,16\]'
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8
gas/testsuite/gas/aarch64/sve2-sme2-1-invalid.s
Normal file
8
gas/testsuite/gas/aarch64/sve2-sme2-1-invalid.s
Normal file
@ -0,0 +1,8 @@
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psel pn0, p0, p0.b[w12, 0]
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psel pn, pn0, p0.b[w12, 0]
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psel p0, p0, pn0.b[w12, 0]
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psel pn0, pn0, pn0.b[w12, 0]
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psel pn0, pn0, p0.b[w11, 0]
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psel pn0, pn0, p0.b[w16, 0]
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psel pn0, pn0, p0.b[w12, -1]
|
||||
psel pn0, pn0, p0.b[w12, 16]
|
||||
3
gas/testsuite/gas/aarch64/sve2-sme2-1-noarch.d
Normal file
3
gas/testsuite/gas/aarch64/sve2-sme2-1-noarch.d
Normal file
@ -0,0 +1,3 @@
|
||||
#as: -march=armv8-a+sve2
|
||||
#source: sve2-sme2-1.s
|
||||
#error_output: sve2-sme2-1-noarch.l
|
||||
33
gas/testsuite/gas/aarch64/sve2-sme2-1-noarch.l
Normal file
33
gas/testsuite/gas/aarch64/sve2-sme2-1-noarch.l
Normal file
@ -0,0 +1,33 @@
|
||||
[^ :]+: Assembler messages:
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `psel pn0,pn0,p0\.b\[w12,0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `psel PN0,PN0,P0\.B\[W12,0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `psel pn15,pn0,p0\.b\[w12,0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `psel pn0,pn15,p0\.b\[w12,0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `psel pn0,pn0,p15\.b\[w12,0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `psel pn0,pn0,p0\.b\[w15,0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `psel pn0,pn0,p0\.b\[w12,15\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `psel pn1,pn13,p6\.b\[w14,11\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `psel pn0,pn0,p0\.h\[w12,0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `psel PN0,PN0,P0\.H\[W12,0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `psel pn15,pn0,p0\.h\[w12,0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `psel pn0,pn15,p0\.h\[w12,0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `psel pn0,pn0,p15\.h\[w12,0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `psel pn0,pn0,p0\.h\[w15,0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `psel pn0,pn0,p0\.h\[w12,7\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `psel pn12,pn7,p14\.h\[w13,5\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `psel pn0,pn0,p0\.s\[w12,0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `psel PN0,PN0,P0\.S\[W12,0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `psel pn15,pn0,p0\.s\[w12,0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `psel pn0,pn15,p0\.s\[w12,0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `psel pn0,pn0,p15\.s\[w12,0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `psel pn0,pn0,p0\.s\[w15,0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `psel pn0,pn0,p0\.s\[w12,3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `psel pn6,pn11,p11\.s\[w13,2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `psel pn0,pn0,p0\.d\[w12,0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `psel PN0,PN0,P0\.D\[W12,0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `psel pn15,pn0,p0\.d\[w12,0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `psel pn0,pn15,p0\.d\[w12,0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `psel pn0,pn0,p15\.d\[w12,0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `psel pn0,pn0,p0\.d\[w15,0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `psel pn0,pn0,p0\.d\[w12,1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `psel pn7,pn9,p5\.d\[w13,1\]'
|
||||
41
gas/testsuite/gas/aarch64/sve2-sme2-1.d
Normal file
41
gas/testsuite/gas/aarch64/sve2-sme2-1.d
Normal file
@ -0,0 +1,41 @@
|
||||
#as: -march=armv8-a+sme
|
||||
#objdump: -dr
|
||||
|
||||
[^:]+: file format .*
|
||||
|
||||
|
||||
[^:]+:
|
||||
|
||||
[^:]+:
|
||||
[^:]+: 25244000 psel p0, p0, p0\.b\[w12, 0\]
|
||||
[^:]+: 25244000 psel p0, p0, p0\.b\[w12, 0\]
|
||||
[^:]+: 2524400f psel p15, p0, p0\.b\[w12, 0\]
|
||||
[^:]+: 25247c00 psel p0, p15, p0\.b\[w12, 0\]
|
||||
[^:]+: 252441e0 psel p0, p0, p15\.b\[w12, 0\]
|
||||
[^:]+: 25274000 psel p0, p0, p0\.b\[w15, 0\]
|
||||
[^:]+: 25fc4000 psel p0, p0, p0\.b\[w12, 15\]
|
||||
[^:]+: 25be74c1 psel p1, p13, p6\.b\[w14, 11\]
|
||||
[^:]+: 25284000 psel p0, p0, p0\.h\[w12, 0\]
|
||||
[^:]+: 25284000 psel p0, p0, p0\.h\[w12, 0\]
|
||||
[^:]+: 2528400f psel p15, p0, p0\.h\[w12, 0\]
|
||||
[^:]+: 25287c00 psel p0, p15, p0\.h\[w12, 0\]
|
||||
[^:]+: 252841e0 psel p0, p0, p15\.h\[w12, 0\]
|
||||
[^:]+: 252b4000 psel p0, p0, p0\.h\[w15, 0\]
|
||||
[^:]+: 25f84000 psel p0, p0, p0\.h\[w12, 7\]
|
||||
[^:]+: 25b95dcc psel p12, p7, p14\.h\[w13, 5\]
|
||||
[^:]+: 25304000 psel p0, p0, p0\.s\[w12, 0\]
|
||||
[^:]+: 25304000 psel p0, p0, p0\.s\[w12, 0\]
|
||||
[^:]+: 2530400f psel p15, p0, p0\.s\[w12, 0\]
|
||||
[^:]+: 25307c00 psel p0, p15, p0\.s\[w12, 0\]
|
||||
[^:]+: 253041e0 psel p0, p0, p15\.s\[w12, 0\]
|
||||
[^:]+: 25334000 psel p0, p0, p0\.s\[w15, 0\]
|
||||
[^:]+: 25f04000 psel p0, p0, p0\.s\[w12, 3\]
|
||||
[^:]+: 25b16d66 psel p6, p11, p11\.s\[w13, 2\]
|
||||
[^:]+: 25604000 psel p0, p0, p0\.d\[w12, 0\]
|
||||
[^:]+: 25604000 psel p0, p0, p0\.d\[w12, 0\]
|
||||
[^:]+: 2560400f psel p15, p0, p0\.d\[w12, 0\]
|
||||
[^:]+: 25607c00 psel p0, p15, p0\.d\[w12, 0\]
|
||||
[^:]+: 256041e0 psel p0, p0, p15\.d\[w12, 0\]
|
||||
[^:]+: 25634000 psel p0, p0, p0\.d\[w15, 0\]
|
||||
[^:]+: 25e04000 psel p0, p0, p0\.d\[w12, 1\]
|
||||
[^:]+: 25e164a7 psel p7, p9, p5\.d\[w13, 1\]
|
||||
35
gas/testsuite/gas/aarch64/sve2-sme2-1.s
Normal file
35
gas/testsuite/gas/aarch64/sve2-sme2-1.s
Normal file
@ -0,0 +1,35 @@
|
||||
psel pn0, pn0, p0.b[w12, 0]
|
||||
PSEL PN0, PN0, P0.B[W12, 0]
|
||||
psel pn15, pn0, p0.b[w12, 0]
|
||||
psel pn0, pn15, p0.b[w12, 0]
|
||||
psel pn0, pn0, p15.b[w12, 0]
|
||||
psel pn0, pn0, p0.b[w15, 0]
|
||||
psel pn0, pn0, p0.b[w12, 15]
|
||||
psel pn1, pn13, p6.b[w14, 11]
|
||||
|
||||
psel pn0, pn0, p0.h[w12, 0]
|
||||
PSEL PN0, PN0, P0.H[W12, 0]
|
||||
psel pn15, pn0, p0.h[w12, 0]
|
||||
psel pn0, pn15, p0.h[w12, 0]
|
||||
psel pn0, pn0, p15.h[w12, 0]
|
||||
psel pn0, pn0, p0.h[w15, 0]
|
||||
psel pn0, pn0, p0.h[w12, 7]
|
||||
psel pn12, pn7, p14.h[w13, 5]
|
||||
|
||||
psel pn0, pn0, p0.s[w12, 0]
|
||||
PSEL PN0, PN0, P0.S[W12, 0]
|
||||
psel pn15, pn0, p0.s[w12, 0]
|
||||
psel pn0, pn15, p0.s[w12, 0]
|
||||
psel pn0, pn0, p15.s[w12, 0]
|
||||
psel pn0, pn0, p0.s[w15, 0]
|
||||
psel pn0, pn0, p0.s[w12, 3]
|
||||
psel pn6, pn11, p11.s[w13, 2]
|
||||
|
||||
psel pn0, pn0, p0.d[w12, 0]
|
||||
PSEL PN0, PN0, P0.D[W12, 0]
|
||||
psel pn15, pn0, p0.d[w12, 0]
|
||||
psel pn0, pn15, p0.d[w12, 0]
|
||||
psel pn0, pn0, p15.d[w12, 0]
|
||||
psel pn0, pn0, p0.d[w15, 0]
|
||||
psel pn0, pn0, p0.d[w12, 1]
|
||||
psel pn7, pn9, p5.d[w13, 1]
|
||||
@ -439,13 +439,17 @@ enum aarch64_opnd
|
||||
AARCH64_OPND_SVE_PATTERN_SCALED, /* Likewise, with additional MUL factor. */
|
||||
AARCH64_OPND_SVE_PRFOP, /* SVE prefetch operation. */
|
||||
AARCH64_OPND_SVE_Pd, /* SVE p0-p15 in Pd. */
|
||||
AARCH64_OPND_SVE_PNd, /* SVE pn0-pn15 in Pd. */
|
||||
AARCH64_OPND_SVE_Pg3, /* SVE p0-p7 in Pg. */
|
||||
AARCH64_OPND_SVE_Pg4_5, /* SVE p0-p15 in Pg, bits [8,5]. */
|
||||
AARCH64_OPND_SVE_Pg4_10, /* SVE p0-p15 in Pg, bits [13,10]. */
|
||||
AARCH64_OPND_SVE_PNg4_10, /* SVE pn0-pn15 in Pg, bits [13,10]. */
|
||||
AARCH64_OPND_SVE_Pg4_16, /* SVE p0-p15 in Pg, bits [19,16]. */
|
||||
AARCH64_OPND_SVE_Pm, /* SVE p0-p15 in Pm. */
|
||||
AARCH64_OPND_SVE_Pn, /* SVE p0-p15 in Pn. */
|
||||
AARCH64_OPND_SVE_PNn, /* SVE pn0-pn15 in Pn. */
|
||||
AARCH64_OPND_SVE_Pt, /* SVE p0-p15 in Pt. */
|
||||
AARCH64_OPND_SVE_PNt, /* SVE pn0-pn15 in Pt. */
|
||||
AARCH64_OPND_SVE_Rm, /* Integer Rm or ZR, alt. SVE position. */
|
||||
AARCH64_OPND_SVE_Rn_SP, /* Integer Rn or SP, alt. SVE position. */
|
||||
AARCH64_OPND_SVE_SHLIMM_PRED, /* SVE shift left amount (predicated). */
|
||||
@ -783,6 +787,7 @@ enum aarch64_op
|
||||
OP_UXTL2,
|
||||
|
||||
OP_MOV_P_P,
|
||||
OP_MOV_PN_PN,
|
||||
OP_MOV_Z_P_Z,
|
||||
OP_MOV_Z_V,
|
||||
OP_MOV_Z_Z,
|
||||
|
||||
@ -479,124 +479,125 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
|
||||
case 1236: /* wfit */
|
||||
value = 1236; /* --> wfit. */
|
||||
break;
|
||||
case 2049: /* bic */
|
||||
case 1299: /* and */
|
||||
value = 1299; /* --> and. */
|
||||
case 2053: /* bic */
|
||||
case 1300: /* and */
|
||||
value = 1300; /* --> and. */
|
||||
break;
|
||||
case 1282: /* mov */
|
||||
case 1301: /* and */
|
||||
value = 1301; /* --> and. */
|
||||
case 1283: /* mov */
|
||||
case 1302: /* and */
|
||||
value = 1302; /* --> and. */
|
||||
break;
|
||||
case 1286: /* movs */
|
||||
case 1302: /* ands */
|
||||
value = 1302; /* --> ands. */
|
||||
case 1287: /* movs */
|
||||
case 1303: /* ands */
|
||||
value = 1303; /* --> ands. */
|
||||
break;
|
||||
case 2050: /* cmple */
|
||||
case 1337: /* cmpge */
|
||||
value = 1337; /* --> cmpge. */
|
||||
case 2054: /* cmple */
|
||||
case 1338: /* cmpge */
|
||||
value = 1338; /* --> cmpge. */
|
||||
break;
|
||||
case 2053: /* cmplt */
|
||||
case 1340: /* cmpgt */
|
||||
value = 1340; /* --> cmpgt. */
|
||||
case 2057: /* cmplt */
|
||||
case 1341: /* cmpgt */
|
||||
value = 1341; /* --> cmpgt. */
|
||||
break;
|
||||
case 2051: /* cmplo */
|
||||
case 1342: /* cmphi */
|
||||
value = 1342; /* --> cmphi. */
|
||||
case 2055: /* cmplo */
|
||||
case 1343: /* cmphi */
|
||||
value = 1343; /* --> cmphi. */
|
||||
break;
|
||||
case 2052: /* cmpls */
|
||||
case 1345: /* cmphs */
|
||||
value = 1345; /* --> cmphs. */
|
||||
case 2056: /* cmpls */
|
||||
case 1346: /* cmphs */
|
||||
value = 1346; /* --> cmphs. */
|
||||
break;
|
||||
case 1279: /* mov */
|
||||
case 1367: /* cpy */
|
||||
value = 1367; /* --> cpy. */
|
||||
break;
|
||||
case 1281: /* mov */
|
||||
case 1280: /* mov */
|
||||
case 1368: /* cpy */
|
||||
value = 1368; /* --> cpy. */
|
||||
break;
|
||||
case 2060: /* fmov */
|
||||
case 1284: /* mov */
|
||||
case 1282: /* mov */
|
||||
case 1369: /* cpy */
|
||||
value = 1369; /* --> cpy. */
|
||||
break;
|
||||
case 1274: /* mov */
|
||||
case 1381: /* dup */
|
||||
value = 1381; /* --> dup. */
|
||||
case 2064: /* fmov */
|
||||
case 1285: /* mov */
|
||||
case 1370: /* cpy */
|
||||
value = 1370; /* --> cpy. */
|
||||
break;
|
||||
case 1276: /* mov */
|
||||
case 1273: /* mov */
|
||||
case 1274: /* mov */
|
||||
case 1382: /* dup */
|
||||
value = 1382; /* --> dup. */
|
||||
break;
|
||||
case 2059: /* fmov */
|
||||
case 1278: /* mov */
|
||||
case 1277: /* mov */
|
||||
case 1273: /* mov */
|
||||
case 1383: /* dup */
|
||||
value = 1383; /* --> dup. */
|
||||
break;
|
||||
case 1277: /* mov */
|
||||
case 1384: /* dupm */
|
||||
value = 1384; /* --> dupm. */
|
||||
case 2063: /* fmov */
|
||||
case 1279: /* mov */
|
||||
case 1384: /* dup */
|
||||
value = 1384; /* --> dup. */
|
||||
break;
|
||||
case 2054: /* eon */
|
||||
case 1386: /* eor */
|
||||
value = 1386; /* --> eor. */
|
||||
case 1278: /* mov */
|
||||
case 1385: /* dupm */
|
||||
value = 1385; /* --> dupm. */
|
||||
break;
|
||||
case 1287: /* not */
|
||||
case 1388: /* eor */
|
||||
value = 1388; /* --> eor. */
|
||||
case 2058: /* eon */
|
||||
case 1387: /* eor */
|
||||
value = 1387; /* --> eor. */
|
||||
break;
|
||||
case 1288: /* nots */
|
||||
case 1389: /* eors */
|
||||
value = 1389; /* --> eors. */
|
||||
case 1288: /* not */
|
||||
case 1389: /* eor */
|
||||
value = 1389; /* --> eor. */
|
||||
break;
|
||||
case 2055: /* facle */
|
||||
case 1394: /* facge */
|
||||
value = 1394; /* --> facge. */
|
||||
case 1289: /* nots */
|
||||
case 1390: /* eors */
|
||||
value = 1390; /* --> eors. */
|
||||
break;
|
||||
case 2056: /* faclt */
|
||||
case 1395: /* facgt */
|
||||
value = 1395; /* --> facgt. */
|
||||
case 2059: /* facle */
|
||||
case 1395: /* facge */
|
||||
value = 1395; /* --> facge. */
|
||||
break;
|
||||
case 2057: /* fcmle */
|
||||
case 1408: /* fcmge */
|
||||
value = 1408; /* --> fcmge. */
|
||||
case 2060: /* faclt */
|
||||
case 1396: /* facgt */
|
||||
value = 1396; /* --> facgt. */
|
||||
break;
|
||||
case 2058: /* fcmlt */
|
||||
case 1410: /* fcmgt */
|
||||
value = 1410; /* --> fcmgt. */
|
||||
case 2061: /* fcmle */
|
||||
case 1409: /* fcmge */
|
||||
value = 1409; /* --> fcmge. */
|
||||
break;
|
||||
case 2062: /* fcmlt */
|
||||
case 1411: /* fcmgt */
|
||||
value = 1411; /* --> fcmgt. */
|
||||
break;
|
||||
case 1271: /* fmov */
|
||||
case 1416: /* fcpy */
|
||||
value = 1416; /* --> fcpy. */
|
||||
case 1417: /* fcpy */
|
||||
value = 1417; /* --> fcpy. */
|
||||
break;
|
||||
case 1270: /* fmov */
|
||||
case 1439: /* fdup */
|
||||
value = 1439; /* --> fdup. */
|
||||
case 1440: /* fdup */
|
||||
value = 1440; /* --> fdup. */
|
||||
break;
|
||||
case 1272: /* mov */
|
||||
case 1770: /* orr */
|
||||
value = 1770; /* --> orr. */
|
||||
case 1772: /* orr */
|
||||
value = 1772; /* --> orr. */
|
||||
break;
|
||||
case 2061: /* orn */
|
||||
case 1771: /* orr */
|
||||
value = 1771; /* --> orr. */
|
||||
break;
|
||||
case 1275: /* mov */
|
||||
case 2065: /* orn */
|
||||
case 1773: /* orr */
|
||||
value = 1773; /* --> orr. */
|
||||
break;
|
||||
case 1285: /* movs */
|
||||
case 1774: /* orrs */
|
||||
value = 1774; /* --> orrs. */
|
||||
case 1276: /* mov */
|
||||
case 1275: /* mov */
|
||||
case 1775: /* orr */
|
||||
value = 1775; /* --> orr. */
|
||||
break;
|
||||
case 1280: /* mov */
|
||||
case 1836: /* sel */
|
||||
value = 1836; /* --> sel. */
|
||||
case 1286: /* movs */
|
||||
case 1776: /* orrs */
|
||||
value = 1776; /* --> orrs. */
|
||||
break;
|
||||
case 1283: /* mov */
|
||||
case 1837: /* sel */
|
||||
value = 1837; /* --> sel. */
|
||||
case 1281: /* mov */
|
||||
case 1839: /* sel */
|
||||
value = 1839; /* --> sel. */
|
||||
break;
|
||||
case 1284: /* mov */
|
||||
case 1840: /* sel */
|
||||
value = 1840; /* --> sel. */
|
||||
break;
|
||||
default: return NULL;
|
||||
}
|
||||
@ -651,20 +652,24 @@ aarch64_insert_operand (const aarch64_operand *self,
|
||||
case 174:
|
||||
case 175:
|
||||
case 176:
|
||||
case 191:
|
||||
case 192:
|
||||
case 193:
|
||||
case 194:
|
||||
case 177:
|
||||
case 178:
|
||||
case 179:
|
||||
case 180:
|
||||
case 195:
|
||||
case 196:
|
||||
case 197:
|
||||
case 198:
|
||||
case 199:
|
||||
case 205:
|
||||
case 208:
|
||||
case 210:
|
||||
case 211:
|
||||
case 200:
|
||||
case 201:
|
||||
case 202:
|
||||
case 203:
|
||||
case 209:
|
||||
case 212:
|
||||
case 214:
|
||||
case 215:
|
||||
case 218:
|
||||
return aarch64_ins_regno (self, info, code, inst, errors);
|
||||
case 15:
|
||||
return aarch64_ins_reg_extended (self, info, code, inst, errors);
|
||||
@ -676,7 +681,7 @@ aarch64_insert_operand (const aarch64_operand *self,
|
||||
case 33:
|
||||
case 34:
|
||||
case 35:
|
||||
case 222:
|
||||
case 226:
|
||||
return aarch64_ins_reglane (self, info, code, inst, errors);
|
||||
case 36:
|
||||
return aarch64_ins_reglist (self, info, code, inst, errors);
|
||||
@ -713,18 +718,18 @@ aarch64_insert_operand (const aarch64_operand *self,
|
||||
case 84:
|
||||
case 164:
|
||||
case 166:
|
||||
case 183:
|
||||
case 184:
|
||||
case 185:
|
||||
case 186:
|
||||
case 187:
|
||||
case 188:
|
||||
case 189:
|
||||
case 190:
|
||||
case 215:
|
||||
case 221:
|
||||
case 226:
|
||||
case 227:
|
||||
case 191:
|
||||
case 192:
|
||||
case 193:
|
||||
case 194:
|
||||
case 219:
|
||||
case 225:
|
||||
case 230:
|
||||
case 231:
|
||||
return aarch64_ins_imm (self, info, code, inst, errors);
|
||||
case 44:
|
||||
case 45:
|
||||
@ -865,40 +870,40 @@ aarch64_insert_operand (const aarch64_operand *self,
|
||||
return aarch64_ins_sve_limm_mov (self, info, code, inst, errors);
|
||||
case 165:
|
||||
return aarch64_ins_sve_scale (self, info, code, inst, errors);
|
||||
case 177:
|
||||
case 178:
|
||||
case 179:
|
||||
return aarch64_ins_sve_shlimm (self, info, code, inst, errors);
|
||||
case 180:
|
||||
case 181:
|
||||
case 182:
|
||||
case 183:
|
||||
return aarch64_ins_sve_shlimm (self, info, code, inst, errors);
|
||||
case 184:
|
||||
case 185:
|
||||
case 186:
|
||||
return aarch64_ins_sve_shrimm (self, info, code, inst, errors);
|
||||
case 200:
|
||||
case 201:
|
||||
case 202:
|
||||
case 203:
|
||||
case 204:
|
||||
return aarch64_ins_sve_quad_index (self, info, code, inst, errors);
|
||||
case 205:
|
||||
case 206:
|
||||
return aarch64_ins_sve_index (self, info, code, inst, errors);
|
||||
case 207:
|
||||
case 209:
|
||||
return aarch64_ins_sve_reglist (self, info, code, inst, errors);
|
||||
case 212:
|
||||
case 208:
|
||||
return aarch64_ins_sve_quad_index (self, info, code, inst, errors);
|
||||
case 210:
|
||||
return aarch64_ins_sve_index (self, info, code, inst, errors);
|
||||
case 211:
|
||||
case 213:
|
||||
return aarch64_ins_sve_reglist (self, info, code, inst, errors);
|
||||
case 216:
|
||||
return aarch64_ins_sme_za_hv_tiles (self, info, code, inst, errors);
|
||||
case 217:
|
||||
return aarch64_ins_sme_za_array (self, info, code, inst, errors);
|
||||
case 218:
|
||||
return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors);
|
||||
case 219:
|
||||
return aarch64_ins_sme_sm_za (self, info, code, inst, errors);
|
||||
case 220:
|
||||
return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors);
|
||||
return aarch64_ins_sme_za_hv_tiles (self, info, code, inst, errors);
|
||||
case 221:
|
||||
return aarch64_ins_sme_za_array (self, info, code, inst, errors);
|
||||
case 222:
|
||||
return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors);
|
||||
case 223:
|
||||
return aarch64_ins_sme_sm_za (self, info, code, inst, errors);
|
||||
case 224:
|
||||
case 225:
|
||||
return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors);
|
||||
case 227:
|
||||
case 228:
|
||||
case 229:
|
||||
return aarch64_ins_x0_to_x30 (self, info, code, inst, errors);
|
||||
default: assert (0); abort ();
|
||||
}
|
||||
|
||||
@ -1643,6 +1643,7 @@ do_misc_encoding (aarch64_inst *inst)
|
||||
encode_asisd_fcvtxn (inst);
|
||||
break;
|
||||
case OP_MOV_P_P:
|
||||
case OP_MOV_PN_PN:
|
||||
case OP_MOVS_P_P:
|
||||
/* Copy Pn to Pm and Pg. */
|
||||
value = extract_field (FLD_SVE_Pn, inst->value, 0);
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -192,13 +192,17 @@ const struct aarch64_operand aarch64_operands[] =
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_PATTERN_SCALED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_pattern}, "an enumeration value such as POW2"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_PRFOP", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_prfop}, "an enumeration value such as PLDL1KEEP"},
|
||||
{AARCH64_OPND_CLASS_PRED_REG, "SVE_Pd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pd}, "an SVE predicate register"},
|
||||
{AARCH64_OPND_CLASS_PRED_REG, "SVE_PNd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pd}, "an SVE predicate-as-counter register"},
|
||||
{AARCH64_OPND_CLASS_PRED_REG, "SVE_Pg3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pg3}, "an SVE predicate register"},
|
||||
{AARCH64_OPND_CLASS_PRED_REG, "SVE_Pg4_5", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pg4_5}, "an SVE predicate register"},
|
||||
{AARCH64_OPND_CLASS_PRED_REG, "SVE_Pg4_10", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pg4_10}, "an SVE predicate register"},
|
||||
{AARCH64_OPND_CLASS_PRED_REG, "SVE_PNg4_10", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pg4_10}, "an SVE predicate-as-counter register"},
|
||||
{AARCH64_OPND_CLASS_PRED_REG, "SVE_Pg4_16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pg4_16}, "an SVE predicate register"},
|
||||
{AARCH64_OPND_CLASS_PRED_REG, "SVE_Pm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pm}, "an SVE predicate register"},
|
||||
{AARCH64_OPND_CLASS_PRED_REG, "SVE_Pn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pn}, "an SVE predicate register"},
|
||||
{AARCH64_OPND_CLASS_PRED_REG, "SVE_PNn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pn}, "an SVE predicate register"},
|
||||
{AARCH64_OPND_CLASS_PRED_REG, "SVE_Pt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pt}, "an SVE predicate register"},
|
||||
{AARCH64_OPND_CLASS_PRED_REG, "SVE_PNt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pt}, "an SVE predicate register"},
|
||||
{AARCH64_OPND_CLASS_INT_REG, "SVE_Rm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Rm}, "an integer register or zero"},
|
||||
{AARCH64_OPND_CLASS_INT_REG, "SVE_Rn_SP", OPD_F_MAYBE_SP | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Rn}, "an integer register or SP"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHLIMM_PRED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_tszh,FLD_SVE_imm5}, "a shift-left immediate operand"},
|
||||
@ -330,16 +334,17 @@ static const unsigned op_enum_table [] =
|
||||
413,
|
||||
415,
|
||||
1275,
|
||||
1280,
|
||||
1276,
|
||||
1281,
|
||||
1273,
|
||||
1272,
|
||||
1276,
|
||||
1283,
|
||||
1285,
|
||||
1277,
|
||||
1284,
|
||||
1286,
|
||||
1282,
|
||||
1288,
|
||||
1287,
|
||||
1283,
|
||||
1289,
|
||||
1288,
|
||||
131,
|
||||
};
|
||||
|
||||
|
||||
@ -3679,6 +3679,19 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
|
||||
aarch64_get_qualifier_name (opnd->qualifier)));
|
||||
break;
|
||||
|
||||
case AARCH64_OPND_SVE_PNd:
|
||||
case AARCH64_OPND_SVE_PNg4_10:
|
||||
case AARCH64_OPND_SVE_PNn:
|
||||
case AARCH64_OPND_SVE_PNt:
|
||||
if (opnd->qualifier == AARCH64_OPND_QLF_NIL)
|
||||
snprintf (buf, size, "%s",
|
||||
style_reg (styler, "pn%d", opnd->reg.regno));
|
||||
else
|
||||
snprintf (buf, size, "%s",
|
||||
style_reg (styler, "pn%d.%s", opnd->reg.regno,
|
||||
aarch64_get_qualifier_name (opnd->qualifier)));
|
||||
break;
|
||||
|
||||
case AARCH64_OPND_SVE_Za_5:
|
||||
case AARCH64_OPND_SVE_Za_16:
|
||||
case AARCH64_OPND_SVE_Zd:
|
||||
|
||||
@ -4110,6 +4110,7 @@ const struct aarch64_opcode aarch64_opcode_table[] =
|
||||
_SVE_INSN ("mov", 0x05202000, 0xff20fc00, sve_index, OP_MOV_Z_V, OP2 (SVE_Zd, SVE_VZn), OP_SVE_VV_BHSDQ, F_ALIAS | F_MISC, 0),
|
||||
_SVE_INSN ("mov", 0x05203800, 0xff3ffc00, sve_size_bhsd, 0, OP2 (SVE_Zd, Rn_SP), OP_SVE_VR_BHSD, F_ALIAS, 0),
|
||||
_SVE_INSN ("mov", 0x25804000, 0xfff0c210, sve_misc, OP_MOV_P_P, OP2 (SVE_Pd, SVE_Pn), OP_SVE_BB, F_ALIAS | F_MISC, 0),
|
||||
_SVE_INSN ("mov", 0x25804000, 0xfff0c210, sve_misc, OP_MOV_PN_PN, OP2 (SVE_PNd, SVE_PNn), OP_SVE_BB, F_ALIAS | F_MISC, 0),
|
||||
_SVE_INSN ("mov", 0x05202000, 0xff20fc00, sve_index, OP_MOV_Z_Zi, OP2 (SVE_Zd, SVE_Zn_INDEX), OP_SVE_VV_BHSDQ, F_ALIAS | F_MISC, 0),
|
||||
_SVE_INSN ("mov", 0x05c00000, 0xfffc0000, sve_limm, 0, OP2 (SVE_Zd, SVE_LIMM_MOV), OP_SVE_VU_BHSD, F_ALIAS, 0),
|
||||
_SVE_INSN ("mov", 0x2538c000, 0xff3fc000, sve_size_bhsd, 0, OP2 (SVE_Zd, SVE_ASIMM), OP_SVE_VU_BHSD, F_ALIAS, 0),
|
||||
@ -4583,6 +4584,7 @@ const struct aarch64_opcode aarch64_opcode_table[] =
|
||||
_SVE_INSN ("ldnt1w", 0xa500c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL2), OP_SVE_SZU, F_OD(1), 0),
|
||||
_SVE_INSN ("ldnt1w", 0xa500e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_SZU, F_OD(1), 0),
|
||||
_SVE_INSN ("ldr", 0x85800000, 0xffc0e010, sve_misc, 0, OP2 (SVE_Pt, SVE_ADDR_RI_S9xVL), {}, 0, 0),
|
||||
_SVE_INSN ("ldr", 0x85800000, 0xffc0e010, sve_misc, 0, OP2 (SVE_PNt, SVE_ADDR_RI_S9xVL), {}, 0, 0),
|
||||
_SVE_INSN ("ldr", 0x85804000, 0xffc0e000, sve_misc, 0, OP2 (SVE_Zt, SVE_ADDR_RI_S9xVL), {}, 0, 0),
|
||||
_SVE_INSN ("lsl", 0x04208c00, 0xff20fc00, sve_size_bhs, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVD_BHS, 0, 0),
|
||||
_SVE_INSN ("lsl", 0x04209c00, 0xff20fc00, sve_shift_unpred, 0, OP3 (SVE_Zd, SVE_Zn, SVE_SHLIMM_UNPRED), OP_SVE_VVU_BHSD, 0, 0),
|
||||
@ -4619,6 +4621,7 @@ const struct aarch64_opcode aarch64_opcode_table[] =
|
||||
_SVE_INSN ("orrs", 0x25c04000, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BZBB, F_HAS_ALIAS, 0),
|
||||
_SVE_INSN ("orv", 0x04182000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_BHSD, 0, 0),
|
||||
_SVE_INSN ("pfalse", 0x2518e400, 0xfffffff0, sve_misc, 0, OP1 (SVE_Pd), OP_SVE_B, 0, 0),
|
||||
_SVE_INSN ("pfalse", 0x2518e400, 0xfffffff0, sve_misc, 0, OP1 (SVE_PNd), OP_SVE_B, 0, 0),
|
||||
_SVE_INSN ("pfirst", 0x2558c000, 0xfffffe10, sve_misc, 0, OP3 (SVE_Pd, SVE_Pg4_5, SVE_Pd), OP_SVE_BUB, 0, 2),
|
||||
_SVE_INSN ("pnext", 0x2519c400, 0xff3ffe10, sve_size_bhsd, 0, OP3 (SVE_Pd, SVE_Pg4_5, SVE_Pd), OP_SVE_VUV_BHSD, 0, 2),
|
||||
_SVE_INSN ("prfb", 0x8400c000, 0xffe0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_RX), {}, 0, 0),
|
||||
@ -4800,6 +4803,7 @@ const struct aarch64_opcode aarch64_opcode_table[] =
|
||||
_SVE_INSN ("stnt1w", 0xe5006000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL2), OP_SVE_SUU, F_OD(1), 0),
|
||||
_SVE_INSN ("stnt1w", 0xe510e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_SUU, F_OD(1), 0),
|
||||
_SVE_INSN ("str", 0xe5800000, 0xffc0e010, sve_misc, 0, OP2 (SVE_Pt, SVE_ADDR_RI_S9xVL), {}, 0, 0),
|
||||
_SVE_INSN ("str", 0xe5800000, 0xffc0e010, sve_misc, 0, OP2 (SVE_PNt, SVE_ADDR_RI_S9xVL), {}, 0, 0),
|
||||
_SVE_INSN ("str", 0xe5804000, 0xffc0e000, sve_misc, 0, OP2 (SVE_Zt, SVE_ADDR_RI_S9xVL), {}, 0, 0),
|
||||
_SVE_INSN ("sub", 0x04200400, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0),
|
||||
_SVE_INSNC ("sub", 0x2521c000, 0xff3fc000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zd, SVE_AIMM), OP_SVE_VVU_BHSD, 0, C_SCAN_MOVPRFX, 1),
|
||||
@ -5272,6 +5276,7 @@ const struct aarch64_opcode aarch64_opcode_table[] =
|
||||
SME_INSNC ("sclamp", 0x4400c000, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, C_SCAN_MOVPRFX, 0),
|
||||
SME_INSNC ("uclamp", 0x4400c400, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, C_SCAN_MOVPRFX, 0),
|
||||
SME_INSN ("psel", 0x25204000, 0xff20c210, sme_psel, 0, OP3 (SVE_Pd, SVE_Pg4_10, SME_PnT_Wm_imm), OP_SVE_NN_BHSD, 0, 0),
|
||||
SME_INSN ("psel", 0x25204000, 0xff20c210, sme_psel, 0, OP3 (SVE_PNd, SVE_PNg4_10, SME_PnT_Wm_imm), OP_SVE_NN_BHSD, 0, 0),
|
||||
|
||||
/* SIMD Dot Product (optional in v8.2-A). */
|
||||
DOT_INSN ("udot", 0x2e009400, 0xbf20fc00, dotproduct, OP3 (Vd, Vn, Vm), QL_V3DOT, F_SIZEQ),
|
||||
@ -5817,20 +5822,28 @@ const struct aarch64_opcode aarch64_opcode_table[] =
|
||||
"an enumeration value such as PLDL1KEEP") \
|
||||
Y(PRED_REG, regno, "SVE_Pd", 0, F(FLD_SVE_Pd), \
|
||||
"an SVE predicate register") \
|
||||
Y(PRED_REG, regno, "SVE_PNd", 0, F(FLD_SVE_Pd), \
|
||||
"an SVE predicate-as-counter register") \
|
||||
Y(PRED_REG, regno, "SVE_Pg3", 0, F(FLD_SVE_Pg3), \
|
||||
"an SVE predicate register") \
|
||||
Y(PRED_REG, regno, "SVE_Pg4_5", 0, F(FLD_SVE_Pg4_5), \
|
||||
"an SVE predicate register") \
|
||||
Y(PRED_REG, regno, "SVE_Pg4_10", 0, F(FLD_SVE_Pg4_10), \
|
||||
"an SVE predicate register") \
|
||||
Y(PRED_REG, regno, "SVE_PNg4_10", 0, F(FLD_SVE_Pg4_10), \
|
||||
"an SVE predicate-as-counter register") \
|
||||
Y(PRED_REG, regno, "SVE_Pg4_16", 0, F(FLD_SVE_Pg4_16), \
|
||||
"an SVE predicate register") \
|
||||
Y(PRED_REG, regno, "SVE_Pm", 0, F(FLD_SVE_Pm), \
|
||||
"an SVE predicate register") \
|
||||
Y(PRED_REG, regno, "SVE_Pn", 0, F(FLD_SVE_Pn), \
|
||||
"an SVE predicate register") \
|
||||
Y(PRED_REG, regno, "SVE_PNn", 0, F(FLD_SVE_Pn), \
|
||||
"an SVE predicate register") \
|
||||
Y(PRED_REG, regno, "SVE_Pt", 0, F(FLD_SVE_Pt), \
|
||||
"an SVE predicate register") \
|
||||
Y(PRED_REG, regno, "SVE_PNt", 0, F(FLD_SVE_Pt), \
|
||||
"an SVE predicate register") \
|
||||
Y(INT_REG, regno, "SVE_Rm", 0, F(FLD_SVE_Rm), \
|
||||
"an integer register or zero") \
|
||||
Y(INT_REG, regno, "SVE_Rn_SP", OPD_F_MAYBE_SP, F(FLD_SVE_Rn), \
|
||||
|
||||
Loading…
Reference in New Issue
Block a user