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opcodes/arm: adjust whitespace in cpsie instruction
While I was working on the disassembler styling for ARM I noticed that the whitespace in the cpsie instruction was inconsistent with most of the other ARM disassembly output, the disassembly for cpsie looks like this: cpsie if,#10 notice there's no space before the '#10' immediate, most other ARM instructions have a space before each operand. This commit updates the disassembler to add the missing space, and updates the tests I found that tested this instruction.
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@ -219,7 +219,7 @@ Disassembly of section .text:
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0+34c <[^>]*> e6ef2475 ? uxtb r2, r5, ror #8
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0+350 <[^>]*> 16ef2075 ? uxtbne r2, r5
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0+354 <[^>]*> 16ef2475 ? uxtbne r2, r5, ror #8
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0+358 <[^>]*> f10a00ca ? cpsie if,#10
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0+35c <[^>]*> f10a00d5 ? cpsie if,#21
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0+358 <[^>]*> f10a00ca ? cpsie if, #10
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0+35c <[^>]*> f10a00d5 ? cpsie if, #21
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0+360 <[^>]*> f8cd0510 ? srsia sp, #16
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0+364 <[^>]*> f9ed0510 ? srsib sp!, #16
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@ -131,8 +131,8 @@ l:
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@ Miscellaneous
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bkpt #257
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cpsie ai,#5
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cpsid ai,#5
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cpsie ai, #5
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cpsid ai, #5
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@ Conditional suffixes
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addeq r0,r1,r2
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@ -3828,11 +3828,11 @@ static const struct opcode32 arm_opcodes[] =
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
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0xf1080000, 0xfffffe3f, "cpsie\t%{B:%8'a%7'i%6'f%}"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
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0xf10a0000, 0xfffffe20, "cpsie\t%{B:%8'a%7'i%6'f%},%{I:#%0-4d%}"},
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0xf10a0000, 0xfffffe20, "cpsie\t%{B:%8'a%7'i%6'f%}, %{I:#%0-4d%}"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
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0xf10C0000, 0xfffffe3f, "cpsid\t%{B:%8'a%7'i%6'f%}"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
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0xf10e0000, 0xfffffe20, "cpsid\t%{B:%8'a%7'i%6'f%},%{I:#%0-4d%}"},
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0xf10e0000, 0xfffffe20, "cpsid\t%{B:%8'a%7'i%6'f%}, %{I:#%0-4d%}"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
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0xf1000000, 0xfff1fe20, "cps\t%{I:#%0-4d%}"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
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