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[ARM] Add ARMv8.3 VJCVT instruction

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Add support for VJCVT javascript conversion instruction.

gas/
	* config/tc-arm.c (arm_ext_v8_3, do_vjcvt): Define.
	(insns): Add vjcvt.
	* testsuite/gas/aarch64/armv8_3-a-fp.s: New.
	* testsuite/gas/aarch64/armv8_3-a-fp.d: New.
	* testsuite/gas/aarch64/armv8_3-a-fp-bad.s: New.
	* testsuite/gas/aarch64/armv8_3-a-fp-bad.d: New.
	* testsuite/gas/aarch64/armv8_3-a-fp-bad.l: New.

opcodes/
	* arm-dis.c (coprocessor_opcodes): Add vjcvt.
This commit is contained in:
Szabolcs Nagy 2016-12-05 14:13:27 +00:00
parent a12fd8e1b1
commit 49e8a72582
9 changed files with 76 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
gas/ChangeLog
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@ -1,3 +1,13 @@
2016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com>
* config/tc-arm.c (arm_ext_v8_3, do_vjcvt): Define.
(insns): Add vjcvt.
* testsuite/gas/aarch64/armv8_3-a-fp.s: New.
* testsuite/gas/aarch64/armv8_3-a-fp.d: New.
* testsuite/gas/aarch64/armv8_3-a-fp-bad.s: New.
* testsuite/gas/aarch64/armv8_3-a-fp-bad.d: New.
* testsuite/gas/aarch64/armv8_3-a-fp-bad.l: New.
2016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com> 2016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com>
* config/tc-arm.c (arm_archs): Add "armv8.3-a". * config/tc-arm.c (arm_archs): Add "armv8.3-a".

18
gas/config/tc-arm.c
View File

@ -234,6 +234,8 @@ static const arm_feature_set arm_ext_ras =
/* FP16 instructions. */ /* FP16 instructions. */
static const arm_feature_set arm_ext_fp16 = static const arm_feature_set arm_ext_fp16 =
ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST); ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST);
static const arm_feature_set arm_ext_v8_3 =
ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A);
static const arm_feature_set arm_arch_any = ARM_ANY; static const arm_feature_set arm_arch_any = ARM_ANY;
static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED = ARM_FEATURE (-1, -1, -1); static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED = ARM_FEATURE (-1, -1, -1);
@ -17440,6 +17442,16 @@ do_crc32cw (void)
do_crc32_1 (1, 2); do_crc32_1 (1, 2);
} }
static void
do_vjcvt (void)
{
constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
_(BAD_FPU));
neon_check_type (2, NS_FD, N_S32, N_F64);
do_vfp_sp_dp_cvt ();
do_vfp_cond_or_thumb ();
}
/* Overall per-instruction processing. */ /* Overall per-instruction processing. */
@ -19782,6 +19794,12 @@ static const struct asm_opcode insns[] =
#define THUMB_VARIANT & arm_ext_ras #define THUMB_VARIANT & arm_ext_ras
TUE ("esb", 320f010, f3af8010, 0, (), noargs, noargs), TUE ("esb", 320f010, f3af8010, 0, (), noargs, noargs),
#undef ARM_VARIANT
#define ARM_VARIANT & arm_ext_v8_3
#undef THUMB_VARIANT
#define THUMB_VARIANT & arm_ext_v8_3
NCE (vjcvt, eb90bc0, 2, (RVS, RVD), vjcvt),
#undef ARM_VARIANT #undef ARM_VARIANT
#define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */ #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
#undef THUMB_VARIANT #undef THUMB_VARIANT

2
gas/testsuite/gas/arm/armv8_3-a-fp-bad.d Normal file
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@ -0,0 +1,2 @@
#as: -march=armv8.3-a+fp
#error-output: armv8_3-a-fp-bad.l

7
gas/testsuite/gas/arm/armv8_3-a-fp-bad.l Normal file
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@ -0,0 +1,7 @@
[^:]+: Assembler messages:
[^:]+:3: Error: operand types can't be inferred -- `vjcvt s0,d1'
[^:]+:4: Error: VFP single precision register expected -- `vjcvt\.s32\.f64 r0,d1'
[^:]+:5: Error: VFP/Neon double precision register expected -- `vjcvt\.s32\.f64 s0,s1'
[^:]+:6: Error: VFP/Neon double precision register expected -- `vjcvt\.s32\.f32 s0,s1'
[^:]+:7: Error: bad type in Neon instruction -- `vjcvt\.s32\.f32 s0,d1'
[^:]+:8: Error: bad type in Neon instruction -- `vjcvt\.f32\.f64 s0,d1'

8
gas/testsuite/gas/arm/armv8_3-a-fp-bad.s Normal file
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@ -0,0 +1,8 @@
.text
.arm
vjcvt s0, d1
vjcvt.s32.f64 r0, d1
vjcvt.s32.f64 s0, s1
vjcvt.s32.f32 s0, s1
vjcvt.s32.f32 s0, d1
vjcvt.f32.f64 s0, d1

15
gas/testsuite/gas/arm/armv8_3-a-fp.d Normal file
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@ -0,0 +1,15 @@
#as: -march=armv8.3-a+fp
#objdump: -dr
#skip: *-*-pe *-wince-* *-*-coff
.*: +file format .*arm.*
Disassembly of section .text:
[0-9a-f]+ <.*>:
[0-9a-f]+: eef90bc7 vjcvt.s32.f64 s1, d7
[0-9a-f]+: eef90bc7 vjcvt.s32.f64 s1, d7
[0-9a-f]+ <.*>:
[0-9a-f]+: eef9 0bc7 vjcvt.s32.f64 s1, d7

8
gas/testsuite/gas/arm/armv8_3-a-fp.s Normal file
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@ -0,0 +1,8 @@
.text
A1:
.arm
vjcvt.s32.f64 s1, d7
vjcvtal.s32.f64 s1, d7
T1:
.thumb
vjcvt.s32.f64 s1, d7

4
opcodes/ChangeLog
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@ -1,3 +1,7 @@
2016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com>
* arm-dis.c (coprocessor_opcodes): Add vjcvt.
2016-12-01 Nick Clifton <nickc@redhat.com> 2016-12-01 Nick Clifton <nickc@redhat.com>
PR binutils/20893 PR binutils/20893

4
opcodes/arm-dis.c
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@ -971,6 +971,10 @@ static const struct opcode32 coprocessor_opcodes[] =
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"}, 0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
/* ARMv8.3 javascript conversion instruction. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
{ARM_FEATURE_CORE_LOW (0), 0, 0, 0} {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
}; };