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* dcache.c: Change default value of remotecache to off. It just
screws up too many targets. * sparcl-stub.c: Add prototypes to many forward decls. * Create private copies of strlen, strcpy, and memcpy to prevent chaos when user steps into them. * (trap_low handle_exception): Clean up DSU support code (hardware breakpoints). Move lots of stuff from asm-land to C-land (make it much easier to #ifdef if necessary). Also, use trap 255 to get into break mode instead of doing a DSU register write, which may trash the register. * (putpacket): Don't check return value of putDebugChar. It returns void...
This commit is contained in:
Stu Grossman
parent
d75c2e0f5e
commit
4930f0a7f4
@ -2,6 +2,21 @@ Sun Oct 15 16:19:27 1995 Stan Shebs <shebs@andros.cygnus.com>
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* rs6000-tdep.c: Don't include a.out.h, improve some formatting.
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Fri Oct 13 15:27:49 1995 Stu Grossman (grossman@cygnus.com)
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* dcache.c: Change default value of remotecache to off. It just
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screws up too many targets.
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* sparcl-stub.c: Add prototypes to many forward decls.
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* Create private copies of strlen, strcpy, and memcpy to prevent
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chaos when user steps into them.
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* (trap_low handle_exception): Clean up DSU support code
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(hardware breakpoints). Move lots of stuff from asm-land to
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C-land (make it much easier to #ifdef if necessary). Also, use
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trap 255 to get into break mode instead of doing a DSU register
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write, which may trash the register.
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* (putpacket): Don't check return value of putDebugChar. It
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returns void...
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Fri Oct 13 14:16:17 1995 steve chamberlain <sac@slash.cygnus.com>
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* remote-sim.h: Always include callback.h.
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@ -148,7 +148,7 @@ struct dcache_struct
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int cache_has_stuff;
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} ;
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int remote_dcache = 1;
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int remote_dcache = 0;
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DCACHE *last_cache; /* Used by info dcache */
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@ -95,8 +95,8 @@
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* external low-level support routines
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*/
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extern putDebugChar(); /* write a single character */
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extern getDebugChar(); /* read and return a single char */
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extern void putDebugChar (int c); /* write a single character */
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extern int getDebugChar (void); /* read and return a single char */
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/************************************************************************/
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/* BUFMAX defines the maximum number of characters in inbound/outbound buffers*/
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@ -105,10 +105,9 @@ extern getDebugChar(); /* read and return a single char */
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static int initialized = 0; /* !0 means we've been initialized */
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extern void breakinst();
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static void hw_breakpoint();
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static void set_mem_fault_trap();
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static void get_in_break_mode();
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extern void breakinst ();
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static void set_mem_fault_trap (int enable);
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static void get_in_break_mode (void);
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static const char hexchars[]="0123456789abcdef";
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@ -133,6 +132,43 @@ enum regnames {G0, G1, G2, G3, G4, G5, G6, G7,
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extern void trap_low();
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/* Create private copies of common functions used by the stub. This prevents
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nasty interactions between app code and the stub (for instance if user steps
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into strlen, etc..) */
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static int
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strlen (const char *s)
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{
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const char *s1 = s;
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while (*s1++ != '\000');
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return s1 - s;
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}
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static char *
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strcpy (char *dst, const char *src)
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{
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char *retval = dst;
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while ((*dst++ = *src++) != '\000');
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return retval;
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}
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static void *
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memcpy (void *vdst, const void *vsrc, int n)
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{
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char *dst = vdst;
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const char *src = vsrc;
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char *retval = dst;
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while (n-- > 0)
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*dst++ = *src++;
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return retval;
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}
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asm("
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.reserve trapstack, 1000 * 4, \"bss\", 8
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@ -149,6 +185,18 @@ asm("
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! underflow) occurs. It makes sure that the invalid register window is still
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! available before jumping into C code. It will also restore the world if you
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! return from handle_exception.
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!
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! On entry, trap_low expects l1 and l2 to contain pc and npc respectivly.
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! Register usage throughout the routine is as follows:
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!
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! l0 - psr
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! l1 - pc
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! l2 - npc
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! l3 - wim
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! l4 - scratch and y reg
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! l5 - scratch and tbr
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! l6 - unused
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! l7 - unused
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.globl _trap_low
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_trap_low:
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@ -239,9 +287,6 @@ asm("
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or %l0, 0xf20, %l4
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mov %l4, %psr ! Turn on traps, disable interrupts
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nop
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nop
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nop
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set 0x1000, %l1
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btst %l1, %l0 ! FP enabled?
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@ -271,26 +316,6 @@ asm("
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std %f30, [%sp + (24 + 62) * 4]
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no_fpstore:
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call _get_in_break_mode
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nop
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set 0xff00, %l3
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ldda [%l3]0x1, %l4
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std %l4, [%sp + (24 + 72) * 4] ! DIA1, debug instr addr 1
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! DIA2, debug instr addr 2
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inc 8, %l3
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ldda [%l3]0x1, %l4
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std %l4, [%sp + (24 + 74) * 4] ! DDA1, debug data addr 1
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! DDA2, debug data addr 2
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inc 8, %l3
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ldda [%l3]0x1, %l4
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std %l4, [%sp + (24 + 76) * 4] ! DDV1, debug data val 1
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! DDV2, debug data val 2
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inc 8, %l3
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ldda [%l3]0x1, %l4
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std %l4, [%sp + (24 + 78) * 4] ! DCR, debug control reg
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! DSR, debug status reg
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call _handle_exception
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add %sp, 24 * 4, %o0 ! Pass address of registers
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@ -306,24 +331,6 @@ asm("
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ldd [%sp + (24 + 12) * 4], %i4
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ldd [%sp + (24 + 14) * 4], %i6
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set 0xff00, %l2
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ldd [%sp + (24 + 72) * 4], %l4
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stda %l4, [%l2]0x1 ! DIA1, debug instr addr 1
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! DIA2, debug instr addr 2
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inc 8, %l2
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ldd [%sp + (24 + 74) * 4], %l4
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stda %l4, [%l2]0x1 ! DDA1, debug data addr 1
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! DDA2, debug data addr 2
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inc 8, %l2
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ldd [%sp + (24 + 76) * 4], %l4
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stda %l4, [%l2]0x1 ! DDV1, debug data value 1
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! DDV2, debug data val 2
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inc 8, %l2
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ldd [%sp + (24 + 78) * 4], %l4
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bset 0x200, %l4
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stda %l4, [%l2]0x1 ! DCR, debug control reg
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! DSR, debug control reg
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ldd [%sp + (24 + 64) * 4], %l0 ! Y & PSR
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ldd [%sp + (24 + 68) * 4], %l2 ! PC & NPC
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@ -470,8 +477,7 @@ putpacket(buffer)
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while (ch = buffer[count])
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{
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if (! putDebugChar(ch))
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return;
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putDebugChar (ch);
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checksum += ch;
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count += 1;
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}
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@ -651,7 +657,7 @@ get_in_break_mode()
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exceptionHandler (255, dummy_hw_breakpoint);
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write_asi (1, 0xff10, 0);
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asm ("ta 255");
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exceptionHandler (255, trap_low);
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}
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@ -705,7 +711,6 @@ hexToInt(char **ptr, int *intValue)
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* otherwise.
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*/
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static void
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handle_exception (registers)
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unsigned long *registers;
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@ -738,6 +743,17 @@ handle_exception (registers)
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restore
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");
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get_in_break_mode (); /* Enable DSU register writes */
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registers[DIA1] = read_asi (1, 0xff00);
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registers[DIA2] = read_asi (1, 0xff04);
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registers[DDA1] = read_asi (1, 0xff08);
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registers[DDA2] = read_asi (1, 0xff0c);
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registers[DDV1] = read_asi (1, 0xff10);
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registers[DDV2] = read_asi (1, 0xff14);
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registers[DCR] = read_asi (1, 0xff18);
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registers[DSR] = read_asi (1, 0xff1c);
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if (registers[PC] == (unsigned long)breakinst)
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{
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registers[PC] = registers[NPC];
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@ -916,7 +932,21 @@ handle_exception (registers)
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some location may have changed something that is in the instruction cache.
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*/
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flush_i_cache();
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flush_i_cache ();
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if (!(registers[DSR] & 0x1) /* DSU enabled? */
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&& !(registers[DCR] & 0x200)) /* Are we in break state? */
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{ /* Yes, set the DSU regs */
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write_asi (1, 0xff00, registers[DIA1]);
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write_asi (1, 0xff04, registers[DIA2]);
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write_asi (1, 0xff08, registers[DDA1]);
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write_asi (1, 0xff0c, registers[DDA2]);
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write_asi (1, 0xff10, registers[DDV1]);
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write_asi (1, 0xff14, registers[DDV2]);
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write_asi (1, 0xff1c, registers[DSR]);
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write_asi (1, 0xff18, registers[DCR] | 0x200); /* Clear break */
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}
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return;
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/* kill the program */
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