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RISC-V: PR29342, Fix RV32 disassembler address computation
If either the base register is `zero', `tp' or `gp' and XLEN is 32, an incorrectly sign-extended address is produced when printing. This commit fixes this by fitting an address into a 32-bit value on RV32. Besides, H. Peter Anvin discovered that we have wrong address computation for JALR instruction (the initial bug is back in 2018). This commit also fixes that based on the idea of Palmer Dabbelt. gas/ pr29342 * testsuite/gas/riscv/lla32.d: Reflect RV32 address computation fix. * testsuite/gas/riscv/dis-addr-overflow.s: New testcase. * testsuite/gas/riscv/dis-addr-overflow-32.d: Likewise. * testsuite/gas/riscv/dis-addr-overflow-64.d: Likewise. opcodes/ pr29342 * riscv-dis.c (maybe_print_address): Fit address into 32-bit on RV32. (print_insn_args): Fix JALR address by adding EXTRACT_ITYPE_IMM.
This commit is contained in:
Tsukasa OI
Nelson Chu
parent
e9f7ba21f0
commit
48525554d5
30
gas/testsuite/gas/riscv/dis-addr-overflow-32.d
Normal file
30
gas/testsuite/gas/riscv/dis-addr-overflow-32.d
Normal file
@ -0,0 +1,30 @@
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#as: -march=rv32ic
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#source: dis-addr-overflow.s
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#objdump: -d
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.*: file format elf32-(little|big)riscv
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Disassembly of section .text:
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0+000 <target>:
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[ ]+[0-9a-f]+:[ ]+fffff2b7[ ]+lui[ ]+t0,0xfffff
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[ ]+[0-9a-f]+:[ ]+ffc2a903[ ]+lw[ ]+s2,-4\(t0\) # ffffeffc <addr_load>
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[ ]+[0-9a-f]+:[ ]+ffffe337[ ]+lui[ ]+t1,0xffffe
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[ ]+[0-9a-f]+:[ ]+ff332c23[ ]+sw[ ]+s3,-8\(t1\) # ffffdff8 <addr_store>
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[ ]+[0-9a-f]+:[ ]+ffffd3b7[ ]+lui[ ]+t2,0xffffd
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[ ]+[0-9a-f]+:[ ]+000380e7[ ]+jalr[ ]+t2 # ffffd000 <addr_jalr_1>
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[ ]+[0-9a-f]+:[ ]+ffffce37[ ]+lui[ ]+t3,0xffffc
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[ ]+[0-9a-f]+:[ ]+ff4e00e7[ ]+jalr[ ]+-12\(t3\) # ffffbff4 <addr_jalr_2>
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[ ]+[0-9a-f]+:[ ]+ffffbeb7[ ]+lui[ ]+t4,0xffffb
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[ ]+[0-9a-f]+:[ ]+000e8a67[ ]+jalr[ ]+s4,t4 # ffffb000 <addr_jalr_3>
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[ ]+[0-9a-f]+:[ ]+ffffaf37[ ]+lui[ ]+t5,0xffffa
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[ ]+[0-9a-f]+:[ ]+ff0f0a93[ ]+addi[ ]+s5,t5,-16 # ffff9ff0 <addr_loadaddr>
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[ ]+[0-9a-f]+:[ ]+ffff9fb7[ ]+lui[ ]+t6,0xffff9
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[ ]+[0-9a-f]+:[ ]+1fb1[ ]+addi[ ]+t6,t6,-20 # ffff8fec <addr_loadaddr_c>
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[ ]+[0-9a-f]+:[ ]+4001a283[ ]+lw[ ]+t0,1024\(gp\) # 600 <addr_rel_gp_pos>
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[ ]+[0-9a-f]+:[ ]+c001a303[ ]+lw[ ]+t1,-1024\(gp\) # fffffe00 <addr_rel_gp_neg>
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[ ]+[0-9a-f]+:[ ]+10002383[ ]+lw[ ]+t2,256\(zero\) # 100 <addr_rel_zero_pos>
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[ ]+[0-9a-f]+:[ ]+80002e03[ ]+lw[ ]+t3,-2048\(zero\) # fffff800 <addr_rel_zero_neg>
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[ ]+[0-9a-f]+:[ ]+10400ee7[ ]+jalr[ ]+t4,260\(zero\) # 104 <addr_jalr_rel_zero_pos>
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[ ]+[0-9a-f]+:[ ]+80400f67[ ]+jalr[ ]+t5,-2044\(zero\) # fffff804 <addr_jalr_rel_zero_neg>
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34
gas/testsuite/gas/riscv/dis-addr-overflow-64.d
Normal file
34
gas/testsuite/gas/riscv/dis-addr-overflow-64.d
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@ -0,0 +1,34 @@
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#as: -march=rv64ic -defsym rv64=1
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#source: dis-addr-overflow.s
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#objdump: -d
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.*: file format elf64-(little|big)riscv
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Disassembly of section .text:
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0+000 <target>:
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[ ]+[0-9a-f]+:[ ]+fffff2b7[ ]+lui[ ]+t0,0xfffff
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[ ]+[0-9a-f]+:[ ]+ffc2a903[ ]+lw[ ]+s2,-4\(t0\) # ffffffffffffeffc <addr_load>
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[ ]+[0-9a-f]+:[ ]+ffffe337[ ]+lui[ ]+t1,0xffffe
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[ ]+[0-9a-f]+:[ ]+ff332c23[ ]+sw[ ]+s3,-8\(t1\) # ffffffffffffdff8 <addr_store>
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[ ]+[0-9a-f]+:[ ]+ffffd3b7[ ]+lui[ ]+t2,0xffffd
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[ ]+[0-9a-f]+:[ ]+000380e7[ ]+jalr[ ]+t2 # ffffffffffffd000 <addr_jalr_1>
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[ ]+[0-9a-f]+:[ ]+ffffce37[ ]+lui[ ]+t3,0xffffc
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[ ]+[0-9a-f]+:[ ]+ff4e00e7[ ]+jalr[ ]+-12\(t3\) # ffffffffffffbff4 <addr_jalr_2>
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[ ]+[0-9a-f]+:[ ]+ffffbeb7[ ]+lui[ ]+t4,0xffffb
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[ ]+[0-9a-f]+:[ ]+000e8a67[ ]+jalr[ ]+s4,t4 # ffffffffffffb000 <addr_jalr_3>
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[ ]+[0-9a-f]+:[ ]+ffffaf37[ ]+lui[ ]+t5,0xffffa
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[ ]+[0-9a-f]+:[ ]+ff0f0a93[ ]+addi[ ]+s5,t5,-16 # ffffffffffff9ff0 <addr_loadaddr>
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[ ]+[0-9a-f]+:[ ]+ffff9fb7[ ]+lui[ ]+t6,0xffff9
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[ ]+[0-9a-f]+:[ ]+1fb1[ ]+addi[ ]+t6,t6,-20 # ffffffffffff8fec <addr_loadaddr_c>
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[ ]+[0-9a-f]+:[ ]+ffff8b37[ ]+lui[ ]+s6,0xffff8
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[ ]+[0-9a-f]+:[ ]+fe8b0b9b[ ]+addiw[ ]+s7,s6,-24 # ffffffffffff7fe8 <addr_loadaddr_w>
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[ ]+[0-9a-f]+:[ ]+ffff7c37[ ]+lui[ ]+s8,0xffff7
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[ ]+[0-9a-f]+:[ ]+3c11[ ]+addiw[ ]+s8,s8,-28 # ffffffffffff6fe4 <addr_loadaddr_w_c>
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[ ]+[0-9a-f]+:[ ]+4001a283[ ]+lw[ ]+t0,1024\(gp\) # 600 <addr_rel_gp_pos>
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[ ]+[0-9a-f]+:[ ]+c001a303[ ]+lw[ ]+t1,-1024\(gp\) # fffffffffffffe00 <addr_rel_gp_neg>
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[ ]+[0-9a-f]+:[ ]+10002383[ ]+lw[ ]+t2,256\(zero\) # 100 <addr_rel_zero_pos>
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[ ]+[0-9a-f]+:[ ]+80002e03[ ]+lw[ ]+t3,-2048\(zero\) # fffffffffffff800 <addr_rel_zero_neg>
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[ ]+[0-9a-f]+:[ ]+10400ee7[ ]+jalr[ ]+t4,260\(zero\) # 104 <addr_jalr_rel_zero_pos>
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[ ]+[0-9a-f]+:[ ]+80400f67[ ]+jalr[ ]+t5,-2044\(zero\) # fffffffffffff804 <addr_jalr_rel_zero_neg>
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70
gas/testsuite/gas/riscv/dis-addr-overflow.s
Normal file
70
gas/testsuite/gas/riscv/dis-addr-overflow.s
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@ -0,0 +1,70 @@
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.set __global_pointer$, 0x00000200
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.ifdef rv64
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topbase = 0xffffffff00000000
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.else
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topbase = 0
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.endif
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.set addr_load, topbase + 0xffffeffc # -0x1000 -4
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.set addr_store, topbase + 0xffffdff8 # -0x2000 -8
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.set addr_jalr_1, topbase + 0xffffd000 # -0x3000
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.set addr_jalr_2, topbase + 0xffffbff4 # -0x4000 -12
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.set addr_jalr_3, topbase + 0xffffb000 # -0x5000
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.set addr_loadaddr, topbase + 0xffff9ff0 # -0x6000 -16
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.set addr_loadaddr_c, topbase + 0xffff8fec # -0x7000 -20
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.set addr_loadaddr_w, topbase + 0xffff7fe8 # -0x8000 -24
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.set addr_loadaddr_w_c, topbase + 0xffff6fe4 # -0x9000 -28
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.set addr_rel_gp_pos, 0x00000600 # __global_pointer$ + 0x400
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.set addr_rel_gp_neg, topbase + 0xfffffe00 # __global_pointer$ - 0x400
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.set addr_rel_zero_pos, 0x00000100
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.set addr_rel_zero_neg, topbase + 0xfffff800 # -0x800
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.set addr_jalr_rel_zero_pos, 0x00000104
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.set addr_jalr_rel_zero_neg, topbase + 0xfffff804 # -0x7fc
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target:
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.option push
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.option arch, -c
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## Use hi_addr
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# Load
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lui t0, 0xfffff
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lw s2, -4(t0)
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# Store
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lui t1, 0xffffe
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sw s3, -8(t1)
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# JALR (implicit destination, no offset)
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lui t2, 0xffffd
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jalr t2
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# JALR (implicit destination, with offset)
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lui t3, 0xffffc
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jalr -12(t3)
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# JALR (explicit destination, no offset)
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lui t4, 0xffffb
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jalr s4, t4
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# ADDI (not compressed)
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lui t5, 0xffffa
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addi s5, t5, -16
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# C.ADDI
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lui t6, 0xffff9
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.option pop
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c.addi t6, -20
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.ifdef rv64
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.option push
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.option arch, -c
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# ADDIW (not compressed)
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lui s6, 0xffff8
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addiw s7, s6, -24
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# C.ADDIW
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lui s8, 0xffff7
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.option pop
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c.addiw s8, -28
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.endif
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# Use addresses relative to gp
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lw t0, 0x400(gp)
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lw t1, -0x400(gp)
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# Use addresses relative to zero
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lw t2, 0x100(zero)
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lw t3, -0x800(zero)
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jalr t4, 0x104(zero)
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jalr t5, -0x7fc(zero)
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@ -14,6 +14,6 @@ Disassembly of section .text:
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10: 00001537 lui a0,0x1
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14: fff50513 addi a0,a0,-1 # fff <d>
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18: 80000537 lui a0,0x80000
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1c: fff50513 addi a0,a0,-1 # 7fffffff <h\+0x80000000>
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1c: fff50513 addi a0,a0,-1 # 7fffffff <e>
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20: 00000513 li a0,0
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24: fff00513 li a0,-1
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@ -181,10 +181,16 @@ maybe_print_address (struct riscv_private_data *pd, int base_reg, int offset,
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pd->print_addr = pd->gp + offset;
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else if (base_reg == X_TP || base_reg == 0)
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pd->print_addr = offset;
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else
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return; /* Don't print the address. */
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/* Sign-extend a 32-bit value to a 64-bit value. */
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if (wide)
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pd->print_addr = (bfd_vma)(int32_t) pd->print_addr;
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/* Fit into a 32-bit value on RV32. */
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if (xlen == 32)
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pd->print_addr = (bfd_vma)(uint32_t)pd->print_addr;
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}
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/* Print insn arguments for 32/64-bit code. */
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@ -397,7 +403,7 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
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case 'b':
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case 's':
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if ((l & MASK_JALR) == MATCH_JALR)
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maybe_print_address (pd, rs1, 0, 0);
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maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), 0);
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print (info->stream, dis_style_register, "%s", riscv_gpr_names[rs1]);
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break;
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