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aarch64: Add +xs flag for existing instructions

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Additionally, change FEAT_XS tlbi variants to be gated on "+xs" instead of
"+d128".  This is an incremental improvement; there are still some FEAT_XS tlbi
variants that are gated incorrectly or missing entirely.
This commit is contained in:
Andrew Carlotti 2024-01-12 01:45:25 +00:00 committed by Nick Clifton
parent 59255bf7d2
commit 43291582c0
6 changed files with 31 additions and 2 deletions
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1
gas/config/tc-aarch64.c
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@ -10323,6 +10323,7 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
{"flagm", AARCH64_FEATURE (FLAGM), AARCH64_NO_FEATURES},
{"flagm2", AARCH64_FEATURE (FLAGMANIP), AARCH64_FEATURE (FLAGM)},
{"pauth", AARCH64_FEATURE (PAC), AARCH64_NO_FEATURES},
{"xs", AARCH64_FEATURE (XS), AARCH64_NO_FEATURES},
{"wfxt", AARCH64_FEATURE (WFXT), AARCH64_NO_FEATURES},
{"mops", AARCH64_FEATURE (MOPS), AARCH64_NO_FEATURES},
{"hbc", AARCH64_FEATURE (HBC), AARCH64_NO_FEATURES},

8
gas/testsuite/gas/aarch64/system-4.d
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@ -14,3 +14,11 @@ Disassembly of section \.text:
.*: d503363f dsb nshnxs
.*: d5033a3f dsb ishnxs
.*: d5033e3f dsb synxs
.*: d503323f dsb oshnxs
.*: d503363f dsb nshnxs
.*: d5033a3f dsb ishnxs
.*: d5033e3f dsb synxs
.*: d503323f dsb oshnxs
.*: d503363f dsb nshnxs
.*: d5033a3f dsb ishnxs
.*: d5033e3f dsb synxs

12
gas/testsuite/gas/aarch64/system-4.s
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@ -10,3 +10,15 @@
dsb nshnxs
dsb ishnxs
dsb synxs
.arch armv8-a+xs
dsb #16
dsb #20
dsb #24
dsb #28
dsb oshnxs
dsb nshnxs
dsb ishnxs
dsb synxs

3
include/opcode/aarch64.h
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@ -141,6 +141,8 @@ enum aarch64_feature_bit {
AARCH64_FEATURE_MEMTAG,
/* Transactional Memory Extension. */
AARCH64_FEATURE_TME,
/* XS memory attribute. */
AARCH64_FEATURE_XS,
/* WFx instructions with timeout. */
AARCH64_FEATURE_WFXT,
/* Standardization of memory operations. */
@ -273,6 +275,7 @@ enum aarch64_feature_bit {
| AARCH64_FEATBIT (X, BFLOAT16) \
| AARCH64_FEATBIT (X, I8MM))
#define AARCH64_ARCH_V8_7A_FEATURES(X) (AARCH64_FEATBIT (X, V8_7A) \
| AARCH64_FEATBIT (X, XS) \
| AARCH64_FEATBIT (X, WFXT) \
| AARCH64_FEATBIT (X, LS64))
#define AARCH64_ARCH_V8_8A_FEATURES(X) (AARCH64_FEATBIT (X, V8_8A) \

2
opcodes/aarch64-opc.c
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@ -5171,7 +5171,7 @@ aarch64_sys_ins_reg_supported_p (const aarch64_feature_set features,
|| reg_value == CPENS (6, C9, C6, 5)
|| reg_value == CPENS (6, C9, C7, 1)
|| reg_value == CPENS (6, C9, C7, 5))
&& AARCH64_CPU_HAS_FEATURE (features, D128))
&& AARCH64_CPU_HAS_FEATURE (features, XS))
return true;
/* AT S1E1RP, AT S1E1WP. Values are from aarch64_sys_regs_at. */

7
opcodes/aarch64-tbl.h
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@ -2598,6 +2598,8 @@ static const aarch64_feature_set aarch64_feature_ls64 =
AARCH64_FEATURE (LS64);
static const aarch64_feature_set aarch64_feature_flagm =
AARCH64_FEATURE (FLAGM);
static const aarch64_feature_set aarch64_feature_xs =
AARCH64_FEATURE (XS);
static const aarch64_feature_set aarch64_feature_wfxt =
AARCH64_FEATURE (WFXT);
static const aarch64_feature_set aarch64_feature_mops =
@ -2678,6 +2680,7 @@ static const aarch64_feature_set aarch64_feature_d128_the =
#define ARMV8_7A &aarch64_feature_v8_7a
#define LS64 &aarch64_feature_ls64
#define FLAGM &aarch64_feature_flagm
#define XS &aarch64_feature_xs
#define WFXT &aarch64_feature_wfxt
#define MOPS &aarch64_feature_mops
#define MOPS_MEMTAG &aarch64_feature_mops_memtag
@ -2828,6 +2831,8 @@ static const aarch64_feature_set aarch64_feature_d128_the =
{ NAME, OPCODE, MASK, CLASS, 0, ARMV8R, OPS, QUALS, FLAGS, 0, 0, NULL }
#define V8_7A_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, 0, ARMV8_7A, OPS, QUALS, FLAGS, 0, 0, NULL }
#define XS_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, 0, XS, OPS, QUALS, FLAGS, 0, 0, NULL }
#define WFXT_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, 0, WFXT, OPS, QUALS, FLAGS, 0, 0, NULL }
#define _LS64_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
@ -4225,7 +4230,7 @@ const struct aarch64_opcode aarch64_opcode_table[] =
CORE_INSN ("clearbhb", 0xd50322df, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
CORE_INSN ("clrex", 0xd503305f, 0xfffff0ff, ic_system, 0, OP1 (UIMM4), {}, F_OPD0_OPT | F_DEFAULT (0xF)),
CORE_INSN ("dsb", 0xd503309f, 0xfffff0ff, ic_system, 0, OP1 (BARRIER), {}, F_HAS_ALIAS),
V8_7A_INSN ("dsb", 0xd503323f, 0xfffff3ff, ic_system, OP1 (BARRIER_DSB_NXS), {}, F_HAS_ALIAS),
XS_INSN ("dsb", 0xd503323f, 0xfffff3ff, ic_system, OP1 (BARRIER_DSB_NXS), {}, F_HAS_ALIAS),
V8R_INSN ("dfb", 0xd5033c9f, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS),
CORE_INSN ("ssbb", 0xd503309f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
CORE_INSN ("pssbb", 0xd503349f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),