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PowerPC64 extended instructions in powerpc_macros
The extended instructions implemented in powerpc_macros aren't used by the disassembler. That means instructions like "sldi r3,r3,2" appear in disassembly as "rldicr r3,r3,2,61", which is annoying since many other extended instructions are shown. Note that some of the instructions moved out of the macro table to the opcode table won't appear in disassembly, because they are aliases rather than a subset of the underlying raw instruction. If enabled, rotrdi, extrdi, extldi, clrlsldi, and insrdi would replace all occurrences of rotldi, rldicl, rldicr, rldic and rldimi. (Or many occurrences in the case of clrlsldi if n <= b was added to the extract functions.) The patch also fixes a small bug in opcode sanity checking. include/ * opcode/ppc.h (PPC_OPSHIFT_SH6): Define. opcodes/ * ppc-opc.c (insert_erdn, extract_erdn, insert_eldn, extract_eldn), (insert_crdn, extract_crdn, insert_rrdn, extract_rrdn), (insert_sldn, extract_sldn, insert_srdn, extract_srdn), (insert_erdb, extract_erdb, insert_csldn, extract_csldb), (insert_irdb, extract_irdn): New functions. (ELDn, ERDn, ERDn, RRDn, SRDn, ERDb, CSLDn, CSLDb, IRDn, IRDb): Define and add associated powerpc_operands entries. (powerpc_opcodes): Add "rotrdi", "srdi", "extrdi", "clrrdi", "sldi", "extldi", "clrlsldi", "insrdi" and corresponding record (ie. dot suffix) forms. (powerpc_macros): Delete same from here. gas/ * config/tc-ppc.c (insn_validate): Don't modify value passed to operand->insert for PPC_OPERAND_PLUS1 when calculating mask. Handle PPC_OPSHIFT_SH6. * testsuite/gas/ppc/prefix-reloc.d: Update. * testsuite/gas/ppc/simpshft.d: Update. ld/ * testsuite/ld-powerpc/elfv2so.d: Update. * testsuite/ld-powerpc/notoc.d: Update. * testsuite/ld-powerpc/notoc3.d: Update. * testsuite/ld-powerpc/tlsdesc2.d: Update. * testsuite/ld-powerpc/tlsget.d: Update. * testsuite/ld-powerpc/tlsget2.d: Update. * testsuite/ld-powerpc/tlsopt5.d: Update. * testsuite/ld-powerpc/tlsopt6.d: Update.
This commit is contained in:
Alan Modra
parent
8f50b4b574
commit
42952a9605
@ -1589,10 +1589,10 @@ insn_validate (const struct powerpc_opcode *op)
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val = -1;
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if ((operand->flags & PPC_OPERAND_NEGATIVE) != 0)
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val = -val;
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else if ((operand->flags & PPC_OPERAND_PLUS1) != 0)
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val += 1;
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mask = (*operand->insert) (0, val, ppc_cpu, &errmsg);
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}
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else if (operand->shift == (int) PPC_OPSHIFT_SH6)
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mask = (0x1f << 11) | 0x2;
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else if (operand->shift >= 0)
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mask = operand->bitm << operand->shift;
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else
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@ -10,7 +10,7 @@ Disassembly of section \.text:
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0: (00 00 00 06|06 00 00 00) pli r9,0
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4: (00 00 20 39|39 20 00 00)
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0: R_PPC64_D34_HA30 ext
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8: (46 17 29 79|79 29 17 46) rldicr r9,r9,34,29
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8: (46 17 29 79|79 29 17 46) sldi r9,r9,34
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c: (00 00 00 06|06 00 00 00) paddi r9,r9,0
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10: (00 00 29 39|39 29 00 00)
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c: R_PPC64_D34_LO ext
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@ -7,19 +7,19 @@
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Disassembly of section .text:
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0+ <.text>:
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0: (e0 0f 64 78|78 64 0f e0) rldicl r4,r3,1,63
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0: (e0 0f 64 78|78 64 0f e0) srdi r4,r3,63
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4: (0e f8 83 78|78 83 f8 0e) rldimi r3,r4,63,0
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8: (e4 45 a5 78|78 a5 45 e4) rldicr r5,r5,8,55
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8: (e4 45 a5 78|78 a5 45 e4) sldi r5,r5,8
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c: (20 00 64 78|78 64 00 20) clrldi r4,r3,32
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10: (fe 0f 64 54|54 64 0f fe) rlwinm r4,r3,1,31,31
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14: (00 f8 83 50|50 83 f8 00) rlwimi r3,r4,31,0,0
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18: (2e 40 a5 54|54 a5 40 2e) rlwinm r5,r5,8,0,23
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1c: (3e 04 64 54|54 64 04 3e) clrlwi r4,r3,16
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20: (04 00 64 78|78 64 00 04) rldicr r4,r3,0,0
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24: (e4 07 64 78|78 64 07 e4) rldicr r4,r3,0,63
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28: (06 f8 64 78|78 64 f8 06) rldicr r4,r3,63,0
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20: (04 00 64 78|78 64 00 04) clrrdi r4,r3,63
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24: (e4 07 64 78|78 64 07 e4) clrrdi r4,r3,0
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28: (06 f8 64 78|78 64 f8 06) sldi r4,r3,63
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2c: (e6 ff 64 78|78 64 ff e6) rldicr r4,r3,63,63
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30: (42 f8 64 78|78 64 f8 42) rldicl r4,r3,63,1
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30: (42 f8 64 78|78 64 f8 42) srdi r4,r3,1
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34: (e2 ff 64 78|78 64 ff e2) rldicl r4,r3,63,63
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38: (0c 00 64 78|78 64 00 0c) rldimi r4,r3,0,0
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3c: (0c 08 64 78|78 64 08 0c) rldimi r4,r3,1,0
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@ -32,17 +32,17 @@ Disassembly of section .text:
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58: (02 f8 64 78|78 64 f8 02) rotldi r4,r3,63
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5c: (00 08 64 78|78 64 08 00) rotldi r4,r3,1
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60: (10 20 65 78|78 65 20 10) rotld r5,r3,r4
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64: (e4 07 64 78|78 64 07 e4) rldicr r4,r3,0,63
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68: (06 f8 64 78|78 64 f8 06) rldicr r4,r3,63,0
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64: (e4 07 64 78|78 64 07 e4) clrrdi r4,r3,0
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68: (06 f8 64 78|78 64 f8 06) sldi r4,r3,63
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6c: (00 00 64 78|78 64 00 00) rotldi r4,r3,0
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70: (42 f8 64 78|78 64 f8 42) rldicl r4,r3,63,1
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74: (e0 0f 64 78|78 64 0f e0) rldicl r4,r3,1,63
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70: (42 f8 64 78|78 64 f8 42) srdi r4,r3,1
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74: (e0 0f 64 78|78 64 0f e0) srdi r4,r3,63
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78: (00 00 64 78|78 64 00 00) rotldi r4,r3,0
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7c: (40 00 64 78|78 64 00 40) clrldi r4,r3,1
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80: (e0 07 64 78|78 64 07 e0) clrldi r4,r3,63
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84: (e4 07 64 78|78 64 07 e4) rldicr r4,r3,0,63
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88: (a4 07 64 78|78 64 07 a4) rldicr r4,r3,0,62
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8c: (04 00 64 78|78 64 00 04) rldicr r4,r3,0,0
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84: (e4 07 64 78|78 64 07 e4) clrrdi r4,r3,0
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88: (a4 07 64 78|78 64 07 a4) clrrdi r4,r3,1
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8c: (04 00 64 78|78 64 00 04) clrrdi r4,r3,63
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90: (08 00 64 78|78 64 00 08) rldic r4,r3,0,0
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94: (48 00 64 78|78 64 00 48) rldic r4,r3,0,1
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98: (e8 07 64 78|78 64 07 e8) rldic r4,r3,0,63
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@ -336,9 +336,11 @@ extern const struct powerpc_operand powerpc_operands[];
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extern const unsigned int num_powerpc_operands;
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/* Use with the shift field of a struct powerpc_operand to indicate
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that BITM and SHIFT cannot be used to determine where the operand
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goes in the insn. */
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#define PPC_OPSHIFT_INV (-1U << 31)
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that BITM and SHIFT cannot be used to determine where the operand
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goes in the insn. */
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#define PPC_OPSHIFT_INV (1U << 30)
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/* A special case, 6-bit SH field. */
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#define PPC_OPSHIFT_SH6 (2U << 30)
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/* Values defined for the flags field of a struct powerpc_operand.
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Keep the register bits low: They need to fit in an unsigned short. */
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@ -80,7 +80,7 @@ Disassembly of section \.text:
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.*: (7d 60 5a 14|14 5a 60 7d) add r11,r0,r11
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.*: (38 0c ff d4|d4 ff 0c 38) addi r0,r12,-44
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.*: (e9 8b 00 00|00 00 8b e9) ld r12,0\(r11\)
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.*: (78 00 f0 82|82 f0 00 78) rldicl r0,r0,62,2
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.*: (78 00 f0 82|82 f0 00 78) srdi r0,r0,2
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.*: (7d 89 03 a6|a6 03 89 7d) mtctr r12
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.*: (e9 6b 00 08|08 00 6b e9) ld r11,8\(r11\)
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.*: (4e 80 04 20|20 04 80 4e) bctr
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@ -23,7 +23,7 @@ Disassembly of section \.text:
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.*: (a6 03 88 7d|7d 88 03 a6) mtlr r12
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.*: (ff 7f 80 3d|3d 80 7f ff) lis r12,32767
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.*: (ff ff 8c 61|61 8c ff ff) ori r12,r12,65535
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.*: (c6 07 9c 79|79 9c 07 c6) rldicr r28,r12,32,31
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.*: (c6 07 9c 79|79 9c 07 c6) sldi r28,r12,32
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.*: (ff ef 8c 65|65 8c ef ff) oris r12,r12,61439
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.*: (28 ff 8c 61|61 8c ff 28) ori r12,r12,65320
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.*: (14 62 8b 7d|7d 8b 62 14) add r12,r11,r12
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@ -20,7 +20,7 @@ Disassembly of section \.text:
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.*: (00 00 6b 61|61 6b 00 00) ori r11,r11,0
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.*: (ff ef 13 06|06 13 ef ff) pla r12,-268435736 # 0
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.*: (e8 fe 80 39|39 80 fe e8)
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.*: (46 17 6b 79|79 6b 17 46) rldicr r11,r11,34,29
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.*: (46 17 6b 79|79 6b 17 46) sldi r11,r11,34
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.*: (14 62 8b 7d|7d 8b 62 14) add r12,r11,r12
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.*: (a6 03 89 7d|7d 89 03 a6) mtctr r12
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.*: (20 04 80 4e|4e 80 04 20) bctr
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@ -59,7 +59,7 @@ Disassembly of section \.text:
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.*: (7d 60 5a 14|14 5a 60 7d) add r11,r0,r11
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.*: (38 0c ff d4|d4 ff 0c 38) addi r0,r12,-44
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.*: (e9 8b 00 00|00 00 8b e9) ld r12,0\(r11\)
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.*: (78 00 f0 82|82 f0 00 78) rldicl r0,r0,62,2
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.*: (78 00 f0 82|82 f0 00 78) srdi r0,r0,2
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.*: (7d 89 03 a6|a6 03 89 7d) mtctr r12
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.*: (e9 6b 00 08|08 00 6b e9) ld r11,8\(r11\)
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.*: (4e 80 04 20|20 04 80 4e) bctr
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@ -80,7 +80,7 @@ Disassembly of section \.text:
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.*: (7d 60 5a 14|14 5a 60 7d) add r11,r0,r11
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.*: (38 0c ff d4|d4 ff 0c 38) addi r0,r12,-44
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.*: (e9 8b 00 00|00 00 8b e9) ld r12,0\(r11\)
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.*: (78 00 f0 82|82 f0 00 78) rldicl r0,r0,62,2
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.*: (78 00 f0 82|82 f0 00 78) srdi r0,r0,2
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.*: (7d 89 03 a6|a6 03 89 7d) mtctr r12
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.*: (e9 6b 00 08|08 00 6b e9) ld r11,8\(r11\)
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.*: (4e 80 04 20|20 04 80 4e) bctr
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@ -67,7 +67,7 @@ Disassembly of section \.text:
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.*: (7d 60 5a 14|14 5a 60 7d) add r11,r0,r11
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.*: (38 0c ff d4|d4 ff 0c 38) addi r0,r12,-44
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.*: (e9 8b 00 00|00 00 8b e9) ld r12,0\(r11\)
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.*: (78 00 f0 82|82 f0 00 78) rldicl r0,r0,62,2
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.*: (78 00 f0 82|82 f0 00 78) srdi r0,r0,2
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.*: (7d 89 03 a6|a6 03 89 7d) mtctr r12
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.*: (e9 6b 00 08|08 00 6b e9) ld r11,8\(r11\)
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.*: (4e 80 04 20|20 04 80 4e) bctr
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@ -55,7 +55,7 @@ Disassembly of section \.text:
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.*: (14 5a 60 7d|7d 60 5a 14) add r11,r0,r11
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.*: (d4 ff 0c 38|38 0c ff d4) addi r0,r12,-44
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.*: (00 00 8b e9|e9 8b 00 00) ld r12,0\(r11\)
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.*: (82 f0 00 78|78 00 f0 82) rldicl r0,r0,62,2
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.*: (82 f0 00 78|78 00 f0 82) srdi r0,r0,2
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.*: (a6 03 89 7d|7d 89 03 a6) mtctr r12
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.*: (08 00 6b e9|e9 6b 00 08) ld r11,8\(r11\)
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.*: (20 04 80 4e|4e 80 04 20) bctr
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@ -73,7 +73,7 @@ Disassembly of section \.text:
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.*: (14 5a 60 7d|7d 60 5a 14) add r11,r0,r11
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.*: (d4 ff 0c 38|38 0c ff d4) addi r0,r12,-44
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.*: (00 00 8b e9|e9 8b 00 00) ld r12,0\(r11\)
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.*: (82 f0 00 78|78 00 f0 82) rldicl r0,r0,62,2
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.*: (82 f0 00 78|78 00 f0 82) srdi r0,r0,2
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.*: (a6 03 89 7d|7d 89 03 a6) mtctr r12
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.*: (08 00 6b e9|e9 6b 00 08) ld r11,8\(r11\)
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.*: (20 04 80 4e|4e 80 04 20) bctr
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@ -1166,6 +1166,63 @@ extract_mb6 (uint64_t insn,
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return ((insn >> 6) & 0x1f) | (insn & 0x20);
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}
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/* The n operand of extrdi, which sets MB field. */
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static uint64_t
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insert_erdn (uint64_t insn,
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int64_t value,
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ppc_cpu_t dialect,
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const char **errmsg)
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{
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return insert_mb6 (insn, -value, dialect, errmsg);
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}
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static int64_t
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extract_erdn (uint64_t insn,
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ppc_cpu_t dialect,
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int *invalid)
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{
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return (~extract_mb6 (insn, dialect, invalid) & 63) + 1;
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}
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/* The n operand of extldi, which sets ME field. */
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static uint64_t
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insert_eldn (uint64_t insn,
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int64_t value,
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ppc_cpu_t dialect,
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const char **errmsg)
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{
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return insert_mb6 (insn, value - 1, dialect, errmsg);
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}
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static int64_t
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extract_eldn (uint64_t insn,
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ppc_cpu_t dialect,
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int *invalid)
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{
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return extract_mb6 (insn, dialect, invalid) + 1;
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}
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/* The n operand of clrrdi, which set ME field. */
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static uint64_t
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insert_crdn (uint64_t insn,
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int64_t value,
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ppc_cpu_t dialect,
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const char **errmsg)
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{
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return insert_mb6 (insn, 63 - value, dialect, errmsg);
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}
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static int64_t
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extract_crdn (uint64_t insn,
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ppc_cpu_t dialect,
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int *invalid)
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{
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return 63 - extract_mb6 (insn, dialect, invalid);
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}
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/* The NB field in an X form instruction. The value 32 is stored as
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0. */
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@ -1551,6 +1608,143 @@ extract_sh6 (uint64_t insn,
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return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
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}
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/* The n operand of rotrdi, which writes to SH field. */
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static uint64_t
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insert_rrdn (uint64_t insn,
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int64_t value,
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ppc_cpu_t dialect,
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const char **errmsg)
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{
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return insert_sh6 (insn, -value, dialect, errmsg);
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}
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static int64_t
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extract_rrdn (uint64_t insn,
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ppc_cpu_t dialect,
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int *invalid)
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{
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return -extract_sh6 (insn, dialect, invalid) & 63;
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}
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/* The n operand of sldi, which writes to SH and ME fields. */
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static uint64_t
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insert_sldn (uint64_t insn,
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int64_t value,
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ppc_cpu_t dialect,
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const char **errmsg)
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{
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insn = insert_sh6 (insn, value, dialect, errmsg);
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return insert_crdn (insn, value, dialect, errmsg);
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}
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static int64_t
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extract_sldn (uint64_t insn,
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ppc_cpu_t dialect,
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int *invalid)
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{
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int64_t sh = extract_sh6 (insn, dialect, invalid);
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int64_t me = extract_crdn (insn, dialect, invalid);
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if (me != sh)
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*invalid = 1;
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return sh;
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}
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/* The n operand of srdi, which writes to SH and MB fields. */
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static uint64_t
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insert_srdn (uint64_t insn,
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int64_t value,
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ppc_cpu_t dialect,
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const char **errmsg)
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{
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insn = insert_rrdn (insn, value, dialect, errmsg);
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return insert_mb6 (insn, value, dialect, errmsg);
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}
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static int64_t
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extract_srdn (uint64_t insn,
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ppc_cpu_t dialect,
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int *invalid)
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{
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int64_t sh = extract_rrdn (insn, dialect, invalid);
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int64_t mb = extract_mb6 (insn, dialect, invalid);
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if (mb != sh)
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*invalid = 1;
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return sh;
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}
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/* The b operand of extrdi, which sets SH field. */
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static uint64_t
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insert_erdb (uint64_t insn,
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int64_t value,
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ppc_cpu_t dialect,
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const char **errmsg)
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{
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int64_t n = extract_erdn (insn, dialect, NULL);
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return insert_sh6 (insn, value + n, dialect, errmsg);
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}
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static int64_t
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extract_erdb (uint64_t insn,
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ppc_cpu_t dialect,
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int *invalid)
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{
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int64_t sh = extract_sh6 (insn, dialect, invalid);
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int64_t n = extract_erdn (insn, dialect, invalid);
|
||||
return (sh - n) & 63;
|
||||
}
|
||||
|
||||
/* The b and n operands of clrlsldi. */
|
||||
|
||||
static uint64_t
|
||||
insert_csldn (uint64_t insn,
|
||||
int64_t value,
|
||||
ppc_cpu_t dialect,
|
||||
const char **errmsg)
|
||||
{
|
||||
uint64_t mb6 = 0x3f << 5;
|
||||
int64_t b = extract_mb6 (insn, dialect, NULL);
|
||||
insn = insert_mb6 (insn & ~mb6, b - value, dialect, errmsg);
|
||||
return insert_sh6 (insn, value, dialect, errmsg);
|
||||
}
|
||||
|
||||
static int64_t
|
||||
extract_csldb (uint64_t insn,
|
||||
ppc_cpu_t dialect,
|
||||
int *invalid)
|
||||
{
|
||||
int64_t sh = extract_sh6 (insn, dialect, invalid);
|
||||
int64_t mb = extract_mb6 (insn, dialect, invalid);
|
||||
return (mb + sh) & 63;
|
||||
}
|
||||
|
||||
/* The b and n operands of insrdi. */
|
||||
|
||||
static uint64_t
|
||||
insert_irdb (uint64_t insn,
|
||||
int64_t value,
|
||||
ppc_cpu_t dialect,
|
||||
const char **errmsg)
|
||||
{
|
||||
uint64_t sh6 = (0x1f << 11) | 2;
|
||||
int64_t n = extract_sh6 (insn, dialect, NULL);
|
||||
insn = insert_sh6 (insn & ~sh6, -(value + n), dialect, errmsg);
|
||||
return insert_mb6 (insn, value, dialect, errmsg);
|
||||
}
|
||||
|
||||
static int64_t
|
||||
extract_irdn (uint64_t insn,
|
||||
ppc_cpu_t dialect,
|
||||
int *invalid)
|
||||
{
|
||||
int64_t sh = extract_sh6 (insn, dialect, invalid);
|
||||
int64_t mb = extract_mb6 (insn, dialect, invalid);
|
||||
return (~(mb + sh) & 63) + 1;
|
||||
}
|
||||
|
||||
/* The SPR field in an XFX form instruction. This is flipped--the
|
||||
lower 5 bits are stored in the upper 5 and vice- versa. */
|
||||
|
||||
@ -2754,9 +2948,18 @@ const struct powerpc_operand powerpc_operands[] =
|
||||
#define MB6_MASK (0x3f << 5)
|
||||
{ 0x3f, 5, insert_mb6, extract_mb6, 0 },
|
||||
|
||||
#define ELDn MB6 + 1
|
||||
{ 0x3f, 5, insert_eldn, extract_eldn, PPC_OPERAND_PLUS1 },
|
||||
|
||||
#define ERDn ELDn + 1
|
||||
{ 0x3f, 5, insert_erdn, extract_erdn, 0 },
|
||||
|
||||
#define CRDn ERDn + 1
|
||||
{ 0x3f, 5, insert_crdn, extract_crdn, 0 },
|
||||
|
||||
/* The NB field in an X form instruction. The value 32 is stored as
|
||||
0. */
|
||||
#define NB MB6 + 1
|
||||
#define NB CRDn + 1
|
||||
{ 0x1f, 11, NULL, extract_nb, PPC_OPERAND_PLUS1 },
|
||||
|
||||
/* The NBI field in an lswi instruction, which has special value
|
||||
@ -2942,9 +3145,33 @@ const struct powerpc_operand powerpc_operands[] =
|
||||
#define SH6_MASK ((0x1f << 11) | (1 << 1))
|
||||
{ 0x3f, PPC_OPSHIFT_INV, insert_sh6, extract_sh6, 0 },
|
||||
|
||||
#define RRDn SH6 + 1
|
||||
{ 0x3f, PPC_OPSHIFT_INV, insert_rrdn, extract_rrdn, 0 },
|
||||
|
||||
#define SLDn RRDn + 1
|
||||
{ 0x3f, PPC_OPSHIFT_INV, insert_sldn, extract_sldn, 0 },
|
||||
|
||||
#define SRDn SLDn + 1
|
||||
{ 0x3f, PPC_OPSHIFT_INV, insert_srdn, extract_srdn, 0 },
|
||||
|
||||
#define ERDb SRDn + 1
|
||||
{ 0x3f, PPC_OPSHIFT_INV, insert_erdb, extract_erdb, 0 },
|
||||
|
||||
#define CSLDn ERDb + 1
|
||||
{ 0x3f, PPC_OPSHIFT_SH6, insert_csldn, extract_sh6, 0 },
|
||||
|
||||
#define CSLDb CSLDn + 1
|
||||
{ 0x3f, 5, insert_mb6, extract_csldb, 0 },
|
||||
|
||||
#define IRDn CSLDb + 1
|
||||
{ 0x3f, PPC_OPSHIFT_INV, insert_sh6, extract_irdn, PPC_OPERAND_PLUS1 },
|
||||
|
||||
#define IRDb IRDn + 1
|
||||
{ 0x3f, 5, insert_irdb, extract_mb6, 0 },
|
||||
|
||||
/* The SH field of some variants of the tlbre and tlbwe
|
||||
instructions, and the ELEV field of the e_sc instruction. */
|
||||
#define SHO SH6 + 1
|
||||
#define SHO IRDb + 1
|
||||
#define ELEV SHO
|
||||
{ 0x1f, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
|
||||
|
||||
@ -6244,20 +6471,36 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
||||
{"andiu.", OP(29), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
|
||||
|
||||
{"rotldi", MD(30,0,0), MDMB_MASK, PPC64, PPCVLE|EXT, {RA, RS, SH6}},
|
||||
{"rotrdi", MD(30,0,0), MDMB_MASK, PPC64, PPCVLE|EXT, {RA, RS, RRDn}},
|
||||
{"clrldi", MD(30,0,0), MDSH_MASK, PPC64, PPCVLE|EXT, {RA, RS, MB6}},
|
||||
{"srdi", MD(30,0,0), MD_MASK, PPC64, PPCVLE|EXT, {RA, RS, SRDn}},
|
||||
{"rldicl", MD(30,0,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
|
||||
{"extrdi", MD(30,0,0), MD_MASK, PPC64, PPCVLE|EXT, {RA, RS, ERDn, ERDb}},
|
||||
{"rotldi.", MD(30,0,1), MDMB_MASK, PPC64, PPCVLE|EXT, {RA, RS, SH6}},
|
||||
{"rotrdi.", MD(30,0,1), MDMB_MASK, PPC64, PPCVLE|EXT, {RA, RS, RRDn}},
|
||||
{"clrldi.", MD(30,0,1), MDSH_MASK, PPC64, PPCVLE|EXT, {RA, RS, MB6}},
|
||||
{"srdi.", MD(30,0,1), MD_MASK, PPC64, PPCVLE|EXT, {RA, RS, SRDn}},
|
||||
{"rldicl.", MD(30,0,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
|
||||
{"extrdi.", MD(30,0,1), MD_MASK, PPC64, PPCVLE|EXT, {RA, RS, ERDn, ERDb}},
|
||||
|
||||
{"clrrdi", MD(30,1,0), MDSH_MASK, PPC64, PPCVLE|EXT, {RA, RS, CRDn}},
|
||||
{"sldi", MD(30,1,0), MD_MASK, PPC64, PPCVLE|EXT, {RA, RS, SLDn}},
|
||||
{"rldicr", MD(30,1,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, ME6}},
|
||||
{"extldi", MD(30,1,0), MD_MASK, PPC64, PPCVLE, {RA, RS, ELDn, SH6}},
|
||||
{"clrrdi.", MD(30,1,1), MDSH_MASK, PPC64, PPCVLE|EXT, {RA, RS, CRDn}},
|
||||
{"sldi.", MD(30,1,1), MD_MASK, PPC64, PPCVLE|EXT, {RA, RS, SLDn}},
|
||||
{"rldicr.", MD(30,1,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, ME6}},
|
||||
{"extldi.", MD(30,1,1), MD_MASK, PPC64, PPCVLE, {RA, RS, ELDn, SH6}},
|
||||
|
||||
{"rldic", MD(30,2,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
|
||||
{"clrlsldi", MD(30,2,0), MD_MASK, PPC64, PPCVLE|EXT, {RA, RS, CSLDb, CSLDn}},
|
||||
{"rldic.", MD(30,2,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
|
||||
{"clrlsldi.", MD(30,2,1), MD_MASK, PPC64, PPCVLE|EXT, {RA, RS, CSLDb, CSLDn}},
|
||||
|
||||
{"rldimi", MD(30,3,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
|
||||
{"insrdi", MD(30,3,0), MD_MASK, PPC64, PPCVLE|EXT, {RA, RS, IRDn, IRDb}},
|
||||
{"rldimi.", MD(30,3,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
|
||||
{"insrdi.", MD(30,3,1), MD_MASK, PPC64, PPCVLE|EXT, {RA, RS, IRDn, IRDb}},
|
||||
|
||||
{"rotld", MDS(30,8,0), MDSMB_MASK, PPC64, PPCVLE|EXT, {RA, RS, RB}},
|
||||
{"rldcl", MDS(30,8,0), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, MB6}},
|
||||
@ -9949,23 +10192,6 @@ const unsigned int vle_num_opcodes =
|
||||
support extracting the whole word (32 bits in this case). */
|
||||
|
||||
const struct powerpc_macro powerpc_macros[] = {
|
||||
{"extldi", 4, PPC64, "rldicr %0,%1,%3,(%2)-1"},
|
||||
{"extldi.", 4, PPC64, "rldicr. %0,%1,%3,(%2)-1"},
|
||||
{"extrdi", 4, PPC64, "rldicl %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"},
|
||||
{"extrdi.", 4, PPC64, "rldicl. %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"},
|
||||
{"insrdi", 4, PPC64, "rldimi %0,%1,64-((%2)+(%3)),%3"},
|
||||
{"insrdi.", 4, PPC64, "rldimi. %0,%1,64-((%2)+(%3)),%3"},
|
||||
{"rotrdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0"},
|
||||
{"rotrdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0"},
|
||||
{"sldi", 3, PPC64, "rldicr %0,%1,%2,63-(%2)"},
|
||||
{"sldi.", 3, PPC64, "rldicr. %0,%1,%2,63-(%2)"},
|
||||
{"srdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2"},
|
||||
{"srdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2"},
|
||||
{"clrrdi", 3, PPC64, "rldicr %0,%1,0,63-(%2)"},
|
||||
{"clrrdi.", 3, PPC64, "rldicr. %0,%1,0,63-(%2)"},
|
||||
{"clrlsldi", 4, PPC64, "rldic %0,%1,%3,(%2)-(%3)"},
|
||||
{"clrlsldi.",4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)"},
|
||||
|
||||
{"extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1"},
|
||||
{"extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1"},
|
||||
{"extrwi", 4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user