mirror/binutils-gdb
2
0
Fork 0
mirror of https://sourceware.org/git/binutils-gdb.git synced 2025-03-31 14:11:36 +08:00
Code Issues Packages Projects Releases Wiki Activity

Add LD and GAS testsuites for CRX port.

Browse Source 
Fix several crx bugs.
This commit is contained in:
Nick Clifton 2004-09-03 14:31:41 +00:00
parent 6e3b68350d
commit 42851540ac
67 changed files with 3582 additions and 81 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
gas/ChangeLog
View File

@ -1,3 +1,13 @@
2004-09-03 Tomer Levi <Tomer.Levi@nsc.com>
* config/tc-crx.c (gettrap): Exception vector can be case
insensitive.
(process_label_constant): Fix a 32-bit displacement bug in branch
instructions.
(get_operandtype) : Bug fix, wrong operand was used.
(process_label_constant): Initialize relocation type to
BFD_RELOC_NONE
2004-09-01 Richard Earnshaw < reanrsha@arm.com>
* tc-arm.c (arm_cpus, arm_fpus): Allow <cpu>-s as well as <cpu>s

94
gas/config/tc-crx.c
View File

@ -28,7 +28,6 @@
#include "opcode/crx.h"
#include "elf/crx.h"
/* Include <limits.h> do define ULONG_MAX, LONG_MAX, LONG_MIN. */
#include <limits.h>
/* Word is considered here as a 16-bit unsigned short int. */
@ -123,7 +122,8 @@ const char FLT_CHARS[] = "f'";
/* Target-specific multicharacter options, not const-declared at usage. */
const char *md_shortopts = "";
struct option md_longopts[] = {
struct option md_longopts[] =
{
{NULL, no_argument, NULL, 0}
};
size_t md_longopts_size = sizeof (md_longopts);
@ -282,7 +282,7 @@ reset_vars (char *op, ins *crx_ins)
processing_arg_number = relocatable = size_was_set
= signflag = post_inc_mode = cst4flag = 0;
memset (&output_opcode, '\0', sizeof (output_opcode));
memset (& output_opcode, '\0', sizeof (output_opcode));
/* Memset the 'signflag' field in every argument. */
for (i = 0; i < MAX_OPERANDS; i++)
@ -328,7 +328,7 @@ tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS * fixP)
arelent * reloc;
reloc = xmalloc (sizeof (arelent));
reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
*reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy);
reloc->address = fixP->fx_frag->fr_address + fixP->fx_where;
reloc->addend = fixP->fx_offset;
@ -340,7 +340,7 @@ tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS * fixP)
/* Keep the current difference in the addend. */
reloc->addend = (S_GET_VALUE (fixP->fx_addsy)
- S_GET_VALUE (fixP->fx_subsy) + fixP->fx_offset);
switch (fixP->fx_r_type)
{
case BFD_RELOC_CRX_NUM8:
@ -879,17 +879,25 @@ process_label_constant (char *str, ins * crx_ins, int number)
switch (crx_ins->exp.X_op)
{
case O_big:
case O_absent:
/* Missing or bad expr becomes absolute 0. */
as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
str);
crx_ins->exp.X_op = O_constant;
crx_ins->exp.X_add_number = 0;
crx_ins->exp.X_add_symbol = (symbolS *) 0;
crx_ins->exp.X_op_symbol = (symbolS *) 0;
break;
case O_constant:
crx_ins->arg[number].constant = crx_ins->exp.X_add_number;
constant_val = crx_ins->exp.X_add_number;
if ((IS_INSN_TYPE (CMPBR_INS) || IS_INSN_TYPE (COP_BRANCH_INS))
&& number == 2)
{
/* This variable causes a warning (is to be handles by string
type implementation). */
LONGLONG temp64 = 0;
char ptr[20];
char ptr;
char temp_str[30];
unsigned int jump_value = 0;
int BR_MASK = 0, BR_SIZE = 0;
@ -900,27 +908,7 @@ process_label_constant (char *str, ins * crx_ins, int number)
temp_str[1] = '\0';
}
strncat (temp_str, str, strlen (str));
temp64 = strtol (temp_str, (char **) &ptr,0);
/* This is not accurate :
Actually overflow is allowed here (see comment below).
Originally the call was to 'strtoll', which isn't
identified by MSVC. */
if ((temp64 == LONG_MAX) || (temp64 == LONG_MIN))
as_bad (_("Overflow in displacement in Instruction `%s'"),
ins_parse);
/* If br *+x
It will be returned as '0' padded with 'x' uptill 64 bits
If br *-x
It will be returned as sign extended form
Then search for validity of representation
Check whether upper 38 bits are all zeroes or all ones
If not report error. */
if (!(((temp64 & UPPER31_MASK) == UPPER31_MASK)
|| ((temp64 & UPPER31_MASK) == 0x0)))
as_bad (_("Overflow in displacement in Instruction `%s'"),
ins_parse);
temp64 = strtoll (temp_str, (char **) &ptr,0);
if (temp64 % 2 != 0)
as_bad (_("Odd Offset in displacement in Instruction `%s'"),
@ -955,7 +943,7 @@ process_label_constant (char *str, ins * crx_ins, int number)
|| IS_INSN_TYPE (DCR_BRANCH_INS))
{
LONGLONG temp64 = 0;
char ptr[20];
char ptr;
char temp_str[30];
unsigned int jump_value = 0;
int BR_MASK = 0, BR_SIZE = 0;
@ -967,27 +955,7 @@ process_label_constant (char *str, ins * crx_ins, int number)
temp_str[1] = '\0';
}
strncat (temp_str, str, strlen (str));
temp64 = strtol (temp_str, (char **) &ptr,0);
/* This is not accurate :
Actually overflow is allowed here (see comment below).
Originally the call was to 'strtoll', which isn't
identified by MSVC. */
if ((temp64 == LONG_MAX) || (temp64 == LONG_MIN))
as_bad (_("Overflow in displacement in Instruction `%s'"),
ins_parse);
/* If br *+x
It will be returned as '0' padded with 'x' uptill 64 bits
If br *-x
It will be returned as sign extended form
Then search for validity of representation
Check whether upper 31 bits are all zeroes or all ones
If not report error. */
if (!(((temp64 & UPPER31_MASK) == UPPER31_MASK)
|| ((temp64 & UPPER31_MASK) == 0x0)))
as_bad (_("Overflow in displacement in Instruction `%s'"),
ins_parse);
temp64 = strtoll (temp_str, (char **) &ptr,0);
if (temp64 % 2 != 0)
as_bad (_("Odd Offset in displacement in Instruction `%s'"),
@ -1002,9 +970,8 @@ process_label_constant (char *str, ins * crx_ins, int number)
BR_MASK = 0xFF;
BR_SIZE = 8;
}
else
if (((jump_value & 0xFFFF0000) == 0xFFFF0000)
|| ((jump_value & 0xFFFF0000) == 0x0))
else if (((jump_value & 0xFFFF0000) == 0xFFFF0000)
|| ((jump_value & 0xFFFF0000) == 0x0))
{
BR_MASK = 0xFFFF;
BR_SIZE = 16;
@ -1069,28 +1036,24 @@ process_label_constant (char *str, ins * crx_ins, int number)
~(crx_ins->arg[number].constant) + 1;
if (IS_INSN_TYPE (ARITH_INS) || IS_INSN_TYPE (ARITH_BYTE_INS))
{
char ptr[30];
char ptr;
LONGLONG temp64;
/* Tomer - Originally the call was to 'strtoull', which isn't
identified by MSVC. Instead we check for overflow. */
temp64 = strtoul (str, (char **) &ptr, 0);
temp64 = strtoull (str, (char **) &ptr, 0);
if (cnt < 4)
crx_ins->arg[number].size = 5;
if (IS_INSN_TYPE (ARITH_INS))
{
if (crx_ins->arg[number].size > 32
/* Tomer - check for overflow. */
|| (temp64 == ULONG_MAX))
|| (temp64 > ULONG_MAX))
{
if (crx_ins->arg[number].size > 32)
as_bad (_("In Instruction `%s': Immediate size is \
%lu bits cannot be accomodated"),
ins_parse, cnt + 1);
/* Tomer - check for overflow. */
if (temp64 == ULONG_MAX)
if (temp64 > ULONG_MAX)
as_bad (_("Value given more than 32 bits in \
Instruction `%s'"), ins_parse);
}
@ -1191,6 +1154,7 @@ process_label_constant (char *str, ins * crx_ins, int number)
case O_symbol:
case O_subtract:
crx_ins->arg[number].constant = 0;
crx_ins->rtype = BFD_RELOC_NONE;
relocatable = 1;
switch (crx_ins->arg[number].type)
@ -1536,7 +1500,7 @@ get_operandtype (char *operand, int number, ins * crx_ins)
{
crx_ins->arg[number].type = arg_cr;
crx_ins->arg[number].constant = 0;
set_cons_rparams (operand, crx_ins, number);
set_cons_rparams (temp_operand, crx_ins, number);
get_number_of_bits (crx_ins, number);
if ((! strneq (instruction->mnemonic, "load", 4))
&& (! strneq (instruction->mnemonic, "stor", 4)))
@ -1696,7 +1660,7 @@ gettrap (char *s)
const trap_entry *trap;
for (trap = crx_traps; trap < (crx_traps + NUMTRAPS); trap++)
if (streq (trap->name, s))
if (strcasecmp (trap->name, s) == 0)
return trap->entry;
as_bad (_("Unknown exception: `%s'"), s);

29
gas/testsuite/ChangeLog
View File

@ -1,3 +1,32 @@
2004-09-03 Tomer Levi <Tomer.Levi@nsc.com>
* gas/crx: New directory.
* gas/crx/allinsn.exp: New test script.
* gas/crx/arith_insn.s: New file.
* gas/crx/arith_insn.d: Likewise.
* gas/crx/beq_insn.s: Likewise.
* gas/crx/beq_insn.d: Likewise.
* gas/crx/bit_insn.s: Likewise.
* gas/crx/bit_insn.d: Likewise.
* gas/crx/br_insn.s: Likewise.
* gas/crx/br_insn.d: Likewise.
* gas/crx/cmov_insn.s: Likewise.
* gas/crx/cmov_insn.d: Likewise.
* gas/crx/cmpbr_insn.s: Likewise.
* gas/crx/cmpbr_insn.d: Likewise.
* gas/crx/jscond_insn.s: Likewise.
* gas/crx/jscond_insn.d: Likewise.
* gas/crx/list_insn.s: Likewise.
* gas/crx/list_insn.d: Likewise.
* gas/crx/load_stor_insn.s: Likewise.
* gas/crx/load_stor_insn.d: Likewise.
* gas/crx/misc_insn.s: Likewise.
* gas/crx/misc_insn.d: Likewise.
* gas/crx/no_op_insn.s: Likewise.
* gas/crx/no_op_insn.d: Likewise.
* gas/crx/shift_insn.s: Likewise.
* gas/crx/shift_insn.d: Likewise.
2004-08-27 Richard Sandiford <rsandifo@redhat.com>
* gas/frv/fr550-pack1.[sd]: New test.

27
gas/testsuite/gas/crx/allinsn.exp Normal file
View File

@ -0,0 +1,27 @@
#
# Driver for CRX assembler testsuite
#
proc run_list_test { name opts } {
global srcdir subdir
set testname "CRX $name"
set file $srcdir/$subdir/$name
gas_run ${name}.s $opts ">&dump.out"
if {[regexp_diff "dump.out" "${file}.l"] } {
fail $testname
verbose "output is [file_contents "dump.out"]" 2
return
}
pass $testname
}
if ![istarget crx-*-*] {
return
}
set test_list [lsort [glob -nocomplain $srcdir/$subdir/*.d]]
foreach test $test_list {
# We need to strip the ".d", but can leave the dirname.
verbose [file rootname $test]
run_dump_test [file rootname $test]
}

192
gas/testsuite/gas/crx/arith_insn.d Normal file
View File

@ -0,0 +1,192 @@
#as:
#objdump: -dr
#name: arith_insn
.*: +file format .*
Disassembly of section .text:
00000000 <addub>:
0: 01 00 addub \$0x0, r1
2: e2 00 05 00 addub \$0x5, r2
6: 34 40 addub r3, r4
00000008 <addb>:
8: 15 01 addb \$0x1, r5
a: e6 01 06 00 addb \$0x6, r6
e: 78 41 addb r7, r8
00000010 <addcb>:
10: 29 02 addcb \$0x2, r9
12: ea 02 09 00 addcb \$0x9, r10
16: bc 42 addcb r11, r12
00000018 <andb>:
18: 3d 03 andb \$0x3, r13
1a: 9e 03 andb \$0x10, r14
1c: fe 43 andb r15, r14
0000001e <cmpb>:
1e: 4f 04 cmpb \$0x4, r15
20: e1 04 11 00 cmpb \$0x11, r1
24: 23 44 cmpb r2, r3
00000026 <movb>:
26: 54 05 movb \$0xfffffffc, r4
28: e5 05 36 02 movb \$0x236, r5
2c: 67 45 movb r6, r7
0000002e <orb>:
2e: 68 06 orb \$0xffffffff, r8
30: e9 06 80 69 orb \$0x6980, r9
34: ab 46 orb r10, r11
00000036 <subb>:
36: 7c 07 subb \$0x7, r12
38: ed 07 ff 7f subb \$0x7fff, r13
3c: ef 47 subb r14, r15
0000003e <subcb>:
3e: 8e 08 subcb \$0x8, r14
40: ef 08 aa ff subcb \$0xffaa, r15
44: 12 48 subcb r1, r2
00000046 <xorb>:
46: e3 09 16 00 xorb \$0x16, r3
4a: e4 09 02 90 xorb \$0x9002, r4
4e: 56 49 xorb r5, r6
00000050 <mulb>:
50: e7 0a 32 00 mulb \$0x32, r7
54: e8 0a fa 0e mulb \$0xefa, r8
58: 9a 4a mulb r9, r10
0000005a <adduw>:
5a: ab 10 adduw \$0x20, r11
5c: ec 10 ff 7f adduw \$0x7fff, r12
60: de 50 adduw r13, r14
00000062 <addw>:
62: ef 11 12 00 addw \$0x12, r15
66: ee 11 01 80 addw \$0x8001, r14
6a: f1 51 addw r15, r1
0000006c <addcw>:
6c: e2 12 48 00 addcw \$0x48, r2
70: e3 12 1b 00 addcw \$0x1b, r3
74: 45 52 addcw r4, r5
00000076 <andw>:
76: 06 13 andw \$0x0, r6
78: e7 13 e5 ff andw \$0xffe5, r7
7c: 89 53 andw r8, r9
0000007e <cmpw>:
7e: 1a 14 cmpw \$0x1, r10
80: eb 14 11 00 cmpw \$0x11, r11
84: cd 54 cmpw r12, r13
00000086 <movw>:
86: 2e 15 movw \$0x2, r14
88: ef 15 00 0e movw \$0xe00, r15
8c: ef 55 movw r14, r15
0000008e <orw>:
8e: 31 16 orw \$0x3, r1
90: e2 16 fe ff orw \$0xfffe, r2
94: 34 56 orw r3, r4
00000096 <subw>:
96: 45 17 subw \$0x4, r5
98: e6 17 12 00 subw \$0x12, r6
9c: 78 57 subw r7, r8
0000009e <subcw>:
9e: 59 18 subcw \$0xfffffffc, r9
a0: ea 18 f7 ff subcw \$0xfff7, r10
a4: bc 58 subcw r11, r12
000000a6 <xorw>:
a6: 6d 19 xorw \$0xffffffff, r13
a8: ee 19 21 00 xorw \$0x21, r14
ac: fe 59 xorw r15, r14
000000ae <mulw>:
ae: 7f 1a mulw \$0x7, r15
b0: e1 1a 17 00 mulw \$0x17, r1
b4: 23 5a mulw r2, r3
000000b6 <addud>:
b6: 01 20 addud \$0x0, r1
b8: e2 20 05 00 addud \$0x5, r2
bc: f2 20 05 00 addud \$0x55555, r2
c0: 55 55
c2: 34 60 addud r3, r4
000000c4 <addd>:
c4: 15 21 addd \$0x1, r5
c6: e6 21 06 00 addd \$0x6, r6
ca: f6 21 ff 7f addd \$0x7fffffff, r6
ce: ff ff
d0: 78 61 addd r7, r8
000000d2 <addcd>:
d2: 29 22 addcd \$0x2, r9
d4: ea 22 09 00 addcd \$0x9, r10
d8: fa 22 00 80 addcd \$0x80000001, r10
dc: 01 00
de: bc 62 addcd r11, r12
000000e0 <andd>:
e0: 3d 23 andd \$0x3, r13
e2: 9e 23 andd \$0x10, r14
e4: 6e 23 andd \$0xffffffff, r14
e6: fe 63 andd r15, r14
000000e8 <cmpd>:
e8: 4f 24 cmpd \$0x4, r15
ea: e1 24 11 00 cmpd \$0x11, r1
ee: f1 24 00 f0 cmpd \$0xf0000001, r1
f2: 01 00
f4: 23 64 cmpd r2, r3
000000f6 <movd>:
f6: 54 25 movd \$0xfffffffc, r4
f8: e5 25 36 02 movd \$0x236, r5
fc: f5 25 00 80 movd \$0x80000000, r5
100: 00 00
102: 67 65 movd r6, r7
00000104 <ord>:
104: 68 26 ord \$0xffffffff, r8
106: e9 26 80 69 ord \$0x6980, r9
10a: f9 26 01 00 ord \$0x10000, r9
10e: 00 00
110: ab 66 ord r10, r11
00000112 <subd>:
112: 7c 27 subd \$0x7, r12
114: ed 27 ff 7f subd \$0x7fff, r13
118: fd 27 ff ff subd \$0xffff0000, r13
11c: 00 00
11e: ef 67 subd r14, r15
00000120 <subcd>:
120: 8e 28 subcd \$0x8, r14
122: ef 28 aa ff subcd \$0xffaa, r15
126: 6f 28 subcd \$0xffffffff, r15
128: 12 68 subcd r1, r2
0000012a <xord>:
12a: e3 29 16 00 xord \$0x16, r3
12e: e4 29 02 90 xord \$0x9002, r4
132: f4 29 ff 7f xord \$0x7fffffff, r4
136: ff ff
138: 56 69 xord r5, r6
0000013a <muld>:
13a: e7 2a 32 00 muld \$0x32, r7
13e: e8 2a fa 0e muld \$0xefa, r8
142: f8 2a 00 80 muld \$0x80000001, r8
146: 01 00
148: 9a 6a muld r9, r10

214
gas/testsuite/gas/crx/arith_insn.s Normal file
View File

@ -0,0 +1,214 @@
# Arithmetic instructions.
.data
foodata: .word 42
.text
footext:
.global addub
addub:
addub $0x0 , r1
addub $0x5 , r2
addub r3 , r4
.global addb
addb:
addb $0x1 , r5
addb $0x6 , r6
addb r7 , r8
.global addcb
addcb:
addcb $2 , r9
addcb $0x9 , r10
addcb r11 , r12
.global andb
andb:
andb $0x3 , r13
andb $0x10 , r14
andb r15 , ra
.global cmpb
cmpb:
cmpb $0x4 , sp
cmpb $0x11 , r1
cmpb r2 , r3
.global movb
movb:
movb $-4 , r4
movb $0x236 , r5
movb r6 , r7
.global orb
orb:
orb $-0x1 , r8
orb $0x6980 , r9
orb r10 , r11
.global subb
subb:
subb $07 , r12
subb $0x7fff , r13
subb r14 , r15
.global subcb
subcb:
subcb $010 , ra
subcb $-0x56 , sp
subcb r1 , r2
.global xorb
xorb:
xorb $0x16 , r3
xorb $-0x6ffe , r4
xorb r5 , r6
.global mulb
mulb:
mulb $0x32 , r7
mulb $0xefa , r8
mulb r9 , r10
.global adduw
adduw:
adduw $0x20 , r11
adduw $32767 , r12
adduw r13 , r14
.global addw
addw:
addw $0x12 , r15
addw $-32767 , ra
addw sp , r1
.global addcw
addcw:
addcw $0x48 , r2
addcw $27 , r3
addcw r4 , r5
.global andw
andw:
andw $0 , r6
andw $-27 , r7
andw r8 , r9
.global cmpw
cmpw:
cmpw $1 , r10
cmpw $0x11 , r11
cmpw r12 , r13
.global movw
movw:
movw $0x2 , r14
movw $07000 , r15
movw ra , sp
.global orw
orw:
orw $0x3 , r1
orw $-2 , r2
orw r3 , r4
.global subw
subw:
subw $04 , r5
subw $022 , r6
subw r7 , r8
.global subcw
subcw:
subcw $-0x4 , r9
subcw $-9 , r10
subcw r11 , r12
.global xorw
xorw:
xorw $-1 , r13
xorw $0x21 , r14
xorw r15 , ra
.global mulw
mulw:
mulw $0x7 , sp
mulw $027 , r1
mulw r2 , r3
.global addud
addud:
addud $0x0 , r1
addud $0x5 , r2
addud $0x55555 , r2
addud r3 , r4
.global addd
addd:
addd $0x1 , r5
addd $0x6 , r6
addd $0x7fffffff , r6
addd r7 , r8
.global addcd
addcd:
addcd $2 , r9
addcd $0x9 , r10
addcd $-0x7fffffff , r10
addcd r11 , r12
.global andd
andd:
andd $0x3 , r13
andd $0x10 , r14
andd $0xffffffff , r14
andd r15 , ra
.global cmpd
cmpd:
cmpd $0x4 , sp
cmpd $0x11 , r1
cmpd $0xf0000001 , r1
cmpd r2 , r3
.global movd
movd:
movd $-4 , r4
movd $0x236 , r5
movd $-0x80000000 , r5
movd r6 , r7
.global ord
ord:
ord $-0x1 , r8
ord $0x6980 , r9
ord $0x10000 , r9
ord r10 , r11
.global subd
subd:
subd $07 , r12
subd $0x7fff , r13
subd $-0x10000 , r13
subd r14 , r15
.global subcd
subcd:
subcd $010 , ra
subcd $-0x56 , sp
subcd $4294967295 , sp
subcd r1 , r2
.global xord
xord:
xord $0x16 , r3
xord $-0x6ffe , r4
xord $017777777777 , r4
xord r5 , r6
.global muld
muld:
muld $0x32 , r7
muld $0xefa , r8
muld $-017777777777 , r8
muld r9 , r10

25
gas/testsuite/gas/crx/beq_insn.d Normal file
View File

@ -0,0 +1,25 @@
#as:
#objdump: -dr
#name: beq_insn
.*: +file format .*
Disassembly of section .text:
00000000 <beq0b>:
0: aa b0 beq0b r10, 0x16
00000002 <bne0b>:
2: fb b1 bne0b r11, 0x20
00000004 <beq0w>:
4: 0c b2 beq0w r12, 0x2
00000006 <bne0w>:
6: fd b3 bne0w r13, 0x20
00000008 <beq0d>:
8: fe b4 beq0d r14, 0x20
0000000a <bne0d>:
a: 7f b5 bne0d r15, 0x10

32
gas/testsuite/gas/crx/beq_insn.s Normal file
View File

@ -0,0 +1,32 @@
# 'Branch if Equal to 0' instructions.
.data
foodata: .word 42
.text
footext:
.global beq0b
beq0b:
beq0b r10 , *+22
.global bne0b
bne0b:
bne0b r11 , *+0x20
.global beq0w
beq0w:
beq0w r12 , *+2
.global bne0w
bne0w:
bne0w r13 , *+040
.global beq0d
beq0d:
beq0d ra , *+32
.global bne0d
bne0d:
bne0d sp , *+16

145
gas/testsuite/gas/crx/bit_insn.d Normal file
View File

@ -0,0 +1,145 @@
#as:
#objdump: -dr
#name: bit_insn
.*: +file format .*
Disassembly of section .text:
00000000 <cbitb>:
0: 06 39 00 00 cbitb \$0x6, 0x450
4: 50 04
6: 06 38 50 04 cbitb \$0x6, 0xffff0450
a: 07 39 04 00 cbitb \$0x7, 0x41287
e: 87 12
10: 03 3a 09 50 cbitb \$0x3, 0x9\(r5\)
14: 0f fe cbitb \$0x0, \(r15\)
16: 02 3b ff 10 cbitb \$0x2, 0xffffe1\(r1\)
1a: e1 ff
1c: 04 3d 00 ef cbitb \$0x4, 0xfa\(r14,r15,1\)
20: fa 00
22: 07 3d ff f7 cbitb \$0x7, 0x3ffeb3\(r15,r7,8\)
26: b3 fe
00000028 <cbitw>:
28: 2f 39 00 00 cbitw \$0xf, 0x23
2c: 23 00
2e: 26 38 23 00 cbitw \$0x6, 0xffff0023
32: 21 39 0f 00 cbitw \$0x1, 0xff287
36: 87 f2
38: 2f 3a 01 50 cbitw \$0xf, 0x1\(r5\)
3c: 0e bd cbitw \$0x0, \(r14\)
3e: 25 3b ff 10 cbitw \$0x5, 0xffffe1\(r1\)
42: e1 ff
44: 28 3d 40 ef cbitw \$0x8, 0xaf\(r14,r15,2\)
48: af 00
4a: 27 3d bf 13 cbitw \$0x7, 0x3fff38\(r1,r3,4\)
4e: 38 ff
00000050 <cbitd>:
50: 66 39 00 00 cbitd \$0x6, 0xff
54: ff 00
56: 66 38 ff 0f cbitd \$0x6, 0xffff0fff
5a: 7a 39 01 00 cbitd \$0x1a, 0x10000
5e: 00 00
60: 7f 3a 07 90 cbitd \$0x1f, 0x7\(r9\)
64: 02 f7 cbitd \$0x10, \(r2\)
66: 7a 3b ff 20 cbitd \$0x1a, 0xffffe1\(r2\)
6a: e1 ff
6c: 7e 3c 0a 3f cbitd \$0x1e, 0xa\(r3,r15,1\)
70: 67 3d ff 45 cbitd \$0x7, 0x3ffb80\(r4,r5,8\)
74: 80 fb
76: 08 30 68 38 cbitd r6, r8
7a: 08 30 e4 f7 cbitd \$0x1e, r4
0000007e <sbitb>:
7e: 0e 39 00 00 sbitb \$0x6, 0x450
82: 50 04
84: 0e 38 50 04 sbitb \$0x6, 0xffff0450
88: 0f 39 04 00 sbitb \$0x7, 0x41287
8c: 87 12
8e: 0b 3a 09 50 sbitb \$0x3, 0x9\(r5\)
92: 8f fe sbitb \$0x0, \(r15\)
94: 0a 3b ff 10 sbitb \$0x2, 0xffffe1\(r1\)
98: e1 ff
9a: 0c 3d 00 ef sbitb \$0x4, 0xfa\(r14,r15,1\)
9e: fa 00
a0: 0f 3d ff f7 sbitb \$0x7, 0x3ffeb3\(r15,r7,8\)
a4: b3 fe
000000a6 <sbitw>:
a6: 3f 39 00 00 sbitw \$0xf, 0x23
aa: 23 00
ac: 36 38 23 00 sbitw \$0x6, 0xffff0023
b0: 31 39 0f 00 sbitw \$0x1, 0xff287
b4: 87 f2
b6: 3f 3a 01 50 sbitw \$0xf, 0x1\(r5\)
ba: 0e be sbitw \$0x0, \(r14\)
bc: 35 3b ff 10 sbitw \$0x5, 0xffffe1\(r1\)
c0: e1 ff
c2: 38 3d 40 ef sbitw \$0x8, 0xaf\(r14,r15,2\)
c6: af 00
c8: 37 3d bf 13 sbitw \$0x7, 0x3fff38\(r1,r3,4\)
cc: 38 ff
000000ce <sbitd>:
ce: 86 39 00 00 sbitd \$0x6, 0xff
d2: ff 00
d4: 86 38 ff 0f sbitd \$0x6, 0xffff0fff
d8: 9a 39 01 00 sbitd \$0x1a, 0x10000
dc: 00 00
de: 9f 3a 07 90 sbitd \$0x1f, 0x7\(r9\)
e2: 02 f9 sbitd \$0x10, \(r2\)
e4: 9a 3b ff 20 sbitd \$0x1a, 0xffffe1\(r2\)
e8: e1 ff
ea: 9e 3c 0a 3f sbitd \$0x1e, 0xa\(r3,r15,1\)
ee: 87 3d ff 45 sbitd \$0x7, 0x3ffb80\(r4,r5,8\)
f2: 80 fb
f4: 08 30 68 39 sbitd r6, r8
f8: 08 30 e4 f9 sbitd \$0x1e, r4
000000fc <tbitb>:
fc: 16 39 00 00 tbitb \$0x6, 0x450
100: 50 04
102: 16 38 50 04 tbitb \$0x6, 0xffff0450
106: 17 39 04 00 tbitb \$0x7, 0x41287
10a: 87 12
10c: 13 3a 09 50 tbitb \$0x3, 0x9\(r5\)
110: 0f ff tbitb \$0x0, \(r15\)
112: 12 3b ff 10 tbitb \$0x2, 0xffffe1\(r1\)
116: e1 ff
118: 14 3d 00 ef tbitb \$0x4, 0xfa\(r14,r15,1\)
11c: fa 00
11e: 17 3d ff f7 tbitb \$0x7, 0x3ffeb3\(r15,r7,8\)
122: b3 fe
00000124 <tbitw>:
124: 4f 39 00 00 tbitw \$0xf, 0x23
128: 23 00
12a: 46 38 23 00 tbitw \$0x6, 0xffff0023
12e: 41 39 0f 00 tbitw \$0x1, 0xff287
132: 87 f2
134: 4f 3a 01 50 tbitw \$0xf, 0x1\(r5\)
138: 0e bf tbitw \$0x0, \(r14\)
13a: 45 3b ff 10 tbitw \$0x5, 0xffffe1\(r1\)
13e: e1 ff
140: 48 3d 40 ef tbitw \$0x8, 0xaf\(r14,r15,2\)
144: af 00
146: 47 3d bf 13 tbitw \$0x7, 0x3fff38\(r1,r3,4\)
14a: 38 ff
0000014c <tbitd>:
14c: a6 39 00 00 tbitd \$0x6, 0xff
150: ff 00
152: a6 38 ff 0f tbitd \$0x6, 0xffff0fff
156: ba 39 01 00 tbitd \$0x1a, 0x10000
15a: 00 00
15c: bf 3a 07 90 tbitd \$0x1f, 0x7\(r9\)
160: 02 fb tbitd \$0x10, \(r2\)
162: ba 3b ff 20 tbitd \$0x1a, 0xffffe1\(r2\)
166: e1 ff
168: be 3c 0a 3f tbitd \$0x1e, 0xa\(r3,r15,1\)
16c: a7 3d ff 45 tbitd \$0x7, 0x3ffb80\(r4,r5,8\)
170: 80 fb
172: 08 30 68 3a tbitd r6, r8
176: 08 30 e4 fb tbitd \$0x1e, r4

113
gas/testsuite/gas/crx/bit_insn.s Normal file
View File

@ -0,0 +1,113 @@
# Bit instructions.
.data
foodata: .word 42
.text
footext:
# cbit instructions.
.global cbitb
cbitb:
cbitb $6, 0x450
cbitb $0x6, 0xffff0450
cbitb $7, 0x41287
cbitb $3, 9(r5)
cbitb $0, (sp)
cbitb $2, 0xffffe1(r1)
cbitb $4, 0xfa(ra,sp,1)
cbitb $0x7, -333(r15,r7,8)
.global cbitw
cbitw:
cbitw $0xf, 0x23
cbitw $0x6, 0xffff0023
cbitw $01, 0xff287
cbitw $15, 1(r5)
cbitw $0, (r14)
cbitw $5, 0xffffe1(r1)
cbitw $8, 0xaf(ra,sp,2)
cbitw $0x7, -200(r1,r3,4)
.global cbitd
cbitd:
cbitd $6, 0xff
cbitd $0x6, 0xffff0fff
cbitd $0x1a, 0x10000
cbitd $31, 7(r9)
cbitd $020, (r2)
cbitd $26, 0xffffe1(r2)
cbitd $30, 0xa(r3,sp,1)
cbitd $0x7, -0x480(r4,r5,8)
cbitd r6, r8
cbitd $30, r4
# sbit instructions.
.global sbitb
sbitb:
sbitb $6, 0x450
sbitb $0x6, 0xffff0450
sbitb $7, 0x41287
sbitb $3, 9(r5)
sbitb $0, (sp)
sbitb $2, 0xffffe1(r1)
sbitb $4, 0xfa(ra,sp,1)
sbitb $0x7, -333(r15,r7,8)
.global sbitw
sbitw:
sbitw $0xf, 0x23
sbitw $0x6, 0xffff0023
sbitw $01, 0xff287
sbitw $15, 1(r5)
sbitw $0, (r14)
sbitw $5, 0xffffe1(r1)
sbitw $8, 0xaf(ra,sp,2)
sbitw $0x7, -200(r1,r3,4)
.global sbitd
sbitd:
sbitd $6, 0xff
sbitd $0x6, 0xffff0fff
sbitd $0x1a, 0x10000
sbitd $31, 7(r9)
sbitd $020, (r2)
sbitd $26, 0xffffe1(r2)
sbitd $30, 0xa(r3,sp,1)
sbitd $0x7, -0x480(r4,r5,8)
sbitd r6, r8
sbitd $30, r4
# tbit instructions.
.global tbitb
tbitb:
tbitb $6, 0x450
tbitb $0x6, 0xffff0450
tbitb $7, 0x41287
tbitb $3, 9(r5)
tbitb $0, (sp)
tbitb $2, 0xffffe1(r1)
tbitb $4, 0xfa(ra,sp,1)
tbitb $0x7, -333(r15,r7,8)
.global tbitw
tbitw:
tbitw $0xf, 0x23
tbitw $0x6, 0xffff0023
tbitw $01, 0xff287
tbitw $15, 1(r5)
tbitw $0, (r14)
tbitw $5, 0xffffe1(r1)
tbitw $8, 0xaf(ra,sp,2)
tbitw $0x7, -200(r1,r3,4)
.global tbitd
tbitd:
tbitd $6, 0xff
tbitd $0x6, 0xffff0fff
tbitd $0x1a, 0x10000
tbitd $31, 7(r9)
tbitd $020, (r2)
tbitd $26, 0xffffe1(r2)
tbitd $30, 0xa(r3,sp,1)
tbitd $0x7, -0x480(r4,r5,8)
tbitd r6, r8
tbitd $30, r4

123
gas/testsuite/gas/crx/br_insn.d Normal file
View File

@ -0,0 +1,123 @@
#as:
#objdump: -dr
#name: br_insn
.*: +file format .*
Disassembly of section .text:
00000000 <beq>:
0: 08 70 beq \*\+0x10
2: 7e 70 fd 07 beq \*\+0xffa
6: 7f 70 04 00 beq \*\+0x8aa52
a: 29 55
0000000c <bne>:
c: fc 71 bne \*\-0x8
e: 7e 71 a3 07 bne \*\+0xf46
12: 7f 71 f8 ff bne \*\-0xf7812
16: f7 43
00000018 <bcs>:
18: 7d 72 bcs \*\+0xfa
1a: 7e 72 c6 ec bcs \*\-0x2674
1e: 7f 72 04 00 bcs \*\+0x89052
22: 29 48
00000024 <bcc>:
24: 83 73 bcc \*\-0xfa
26: 7e 73 ff 7f bcc \*\+0xfffe
2a: ff 73 bcc \*\-0x2
0000002c <bhi>:
2c: 7e 74 7f 00 bhi \*\+0xfe
30: 7e 74 01 80 bhi \*\-0xfffe
34: ff 74 bhi \*\-0x2
00000036 <bls>:
36: ff 75 bls \*\-0x2
38: 7e 75 00 80 bls \*\-0x0
3c: 7f 75 00 00 bls \*\+0x10000
40: 00 80
00000042 <bgt>:
42: 18 76 bgt \*\+0x30
44: 7e 76 ff 07 bgt \*\+0xffe
48: 7f 76 ff ff bgt \*\-0x10002
4c: ff 7f
0000004e <ble>:
4e: e0 77 ble \*\-0x40
50: 7e 77 7f ff ble \*\-0x102
54: 7f 77 07 00 ble \*\+0xefff2
58: f9 7f
0000005a <bfs>:
5a: 01 78 bfs \*\+0x2
5c: 7e 78 ff 7f bfs \*\+0xfffe
60: 7f 78 00 00 bfs \*\+0x10000
64: 00 80
00000066 <bfc>:
66: 7e 79 7f 00 bfc \*\+0xfe
6a: 7e 79 ff 7f bfc \*\+0xfffe
6e: 7f 79 04 00 bfc \*\+0x80000
72: 00 00
00000074 <blo>:
74: 81 7a blo \*\-0xfe
76: 7e 7a 01 80 blo \*\-0xfffe
7a: ff 7a blo \*\-0x2
0000007c <bhs>:
7c: 80 7b bhs \*\-0x0
7e: 7e 7b 00 88 bhs \*\-0xf000
82: 7e 7b f9 07 bhs \*\+0xff2
00000086 <blt>:
86: 11 7c blt \*\+0x22
88: 7e 7c 69 02 blt \*\+0x4d2
8c: ff 7c blt \*\-0x2
0000008e <bge>:
8e: 1a 7d bge \*\+0x34
90: 7e 7d e6 f6 bge \*\-0x1234
94: 7f 7d 08 00 bge \*\+0x100002
98: 01 00
0000009a <br>:
9a: 0e 7e br \*\+0x1c
9c: 7e 7e 4e 01 br \*\+0x29c
a0: 7f 7e f7 ff br \*\-0x100002
a4: ff ff
000000a6 <dbnzb>:
a6: 40 30 0e 00 dbnzb r0, \*\+0x1c
aa: 41 30 97 53 dbnzb r1, \*\+0xa72e
000000ae <dbnzw>:
ae: 52 30 cc 0c dbnzw r2, \*\+0x1998
b2: 53 31 31 00 dbnzw r3, \*\+0x63ffb0
b6: d8 ff
000000b8 <dbnzd>:
b8: 6e 30 f9 07 dbnzd r14, \*\+0xff2
bc: 6f 31 97 00 dbnzd r15, \*\+0x12ffff4
c0: fa ff
000000c2 <bal>:
c2: 71 30 01 00 bal r1, \*\+0x2
c6: 71 30 ff ff bal r1, \*\-0x2
ca: 71 30 e7 55 bal r1, \*\+0xabce
ce: 70 30 59 fa bal r0, \*\-0xb4e
d2: 71 31 05 00 bal r1, \*\+0xabcde
d6: 6f 5e
d8: 71 31 fa ff bal r1, \*\-0xabcde
dc: 91 a1
000000de <jal>:
de: 8e ff jal r14
e0: 08 30 1f 37 jal r1, r15
000000e4 <jalid>:
e4: 08 30 ce 33 jalid r12, r14

132
gas/testsuite/gas/crx/br_insn.s Normal file
View File

@ -0,0 +1,132 @@
# Branch instructions.
.data
foodata: .word 42
.text
footext:
# conditional branch instructions.
.global beq
beq:
beq *+16
beq *+4090
beq *+567890
.global bne
bne:
bne *-8
bne *+0xf46
bne *-0xf7812
.global bcs
bcs:
bcs *+250
bcs *-0x2674
bcs *+0x89052
.global bcc
bcc:
bcc *-250
bcc *+0xfffe
bcc *+0xfffffffe
.global bhi
bhi:
bhi *+254
bhi *-0xfffe
bhi *-0xfffffffe
.global bls
bls:
bls *-2
bls *-0x10000
bls *+0x10000
.global bgt
bgt:
bgt *+060
bgt *+0xffe
bgt *-0x10002
.global ble
ble:
ble *-0100
ble *-258
ble *+0xefff2
.global bfs
bfs:
bfs *+0x2
bfs *+0177776
bfs *+0200000
.global bfc
bfc:
bfc *+0xfe
bfc *+65534
bfc *+0x80000
.global blo
blo:
blo *-0xfe
blo *-65534
blo *+4294967294
.global bhs
bhs:
bhs *-0x100
bhs *-0xf000
bhs *+0xff2
.global blt
blt:
blt *+34
blt *+1234
blt *+037777777776
.global bge
bge:
bge *+0x34
bge *-0x1234
bge *+1048578
.global br
br:
br *+034
br *+01234
br *-04000002
# Decrement and Branch instructions.
.global dbnzb
dbnzb:
dbnzb r0, *+034
dbnzb r1, *+01234568
.global dbnzw
dbnzw:
dbnzw r2, *+6552
dbnzw r3, *+6553520
.global dbnzd
dbnzd:
dbnzd ra, *+0xff2
dbnzd sp, *+0x12ffff4
# Branch/Jump and link instructions.
.global bal
bal:
bal r1, 0x2
bal r1, -0x2
bal r1, 0xabce
bal r0, -0xb4e
bal r1, 0xabcde
bal r1, -0xabcde
.global jal
jal:
jal ra
jal r1, sp
.global jalid
jalid:
jalid r12, r14

49
gas/testsuite/gas/crx/cmov_insn.d Normal file
View File

@ -0,0 +1,49 @@
#as:
#objdump: -dr
#name: cmov_insn
.*: +file format .*
Disassembly of section .text:
00000000 <cmoveqd>:
0: 08 30 01 70 cmoveqd r0, r1
00000004 <cmovned>:
4: 08 30 23 71 cmovned r2, r3
00000008 <cmovcsd>:
8: 08 30 45 72 cmovcsd r4, r5
0000000c <cmovccd>:
c: 08 30 67 73 cmovccd r6, r7
00000010 <cmovhid>:
10: 08 30 89 74 cmovhid r8, r9
00000014 <cmovlsd>:
14: 08 30 ab 75 cmovlsd r10, r11
00000018 <cmovgtd>:
18: 08 30 cd 76 cmovgtd r12, r13
0000001c <cmovled>:
1c: 08 30 ef 77 cmovled r14, r15
00000020 <cmovfsd>:
20: 08 30 fe 78 cmovfsd r15, r14
00000024 <cmovfcd>:
24: 08 30 fe 79 cmovfcd r15, r14
00000028 <cmovlod>:
28: 08 30 f0 7a cmovlod r15, r0
0000002c <cmovhsd>:
2c: 08 30 23 7b cmovhsd r2, r3
00000030 <cmovltd>:
30: 08 30 75 7c cmovltd r7, r5
00000034 <cmovged>:
34: 08 30 34 7d cmovged r3, r4

61
gas/testsuite/gas/crx/cmov_insn.s Normal file
View File

@ -0,0 +1,61 @@
# Conditional move instructions.
.data
foodata: .word 42
.text
footext:
.global cmoveqd
cmoveqd:
cmoveqd r0 , r1
.global cmovned
cmovned:
cmovned r2 , r3
.global cmovcsd
cmovcsd:
cmovcsd r4 , r5
.global cmovccd
cmovccd:
cmovccd r6 , r7
.global cmovhid
cmovhid:
cmovhid r8 , r9
.global cmovlsd
cmovlsd:
cmovlsd r10 , r11
.global cmovgtd
cmovgtd:
cmovgtd r12 , r13
.global cmovled
cmovled:
cmovled r14 , sp
.global cmovfsd
cmovfsd:
cmovfsd r15 , ra
.global cmovfcd
cmovfcd:
cmovfcd sp , ra
.global cmovlod
cmovlod:
cmovlod r15 , r0
.global cmovhsd
cmovhsd:
cmovhsd r2 , r3
.global cmovltd
cmovltd:
cmovltd r7 , r5
.global cmovged
cmovged:
cmovged r3 , r4

250
gas/testsuite/gas/crx/cmpbr_insn.d Normal file
View File

@ -0,0 +1,250 @@
#as:
#objdump: -dr
#name: cmpbr_insn
.*: +file format .*
Disassembly of section .text:
00000000 <cmpbeqb>:
0: 81 30 2b 20 cmpbeqb r1, r2, \*\+0x56
4: 83 31 00 40 cmpbeqb r3, r4, \*\+0x4348
8: a4 21
a: c0 30 1b 50 cmpbeqb \$0x0, r5, \*\+0x36
e: c1 31 1a 60 cmpbeqb \$0x1, r6, \*\+0x345678
12: 3c 2b
00000014 <cmpbneb>:
14: 87 30 7d 81 cmpbneb r7, r8, \*\+0xfa
18: 89 31 00 a1 cmpbneb r9, r10, \*\+0xf000
1c: 00 78
1e: c2 30 01 b1 cmpbneb \$0x2, r11, \*\+0x2
22: c3 31 7f c1 cmpbneb \$0x3, r12, \*\+0xfffffe
26: ff ff
00000028 <cmpbhib>:
28: 8d 31 00 e4 cmpbhib r13, r14, \*\+0x100
2c: 80 00
2e: 8f 31 00 e4 cmpbhib r15, r14, \*\+0x102
32: 81 00
34: c4 30 ff f4 cmpbhib \$0x4, r15, \*\-0x2
38: c5 31 ff 14 cmpbhib \$0xfffffffc, r1, \*\-0x104
3c: 7e ff
0000003e <cmpblsb>:
3e: 82 30 3c 35 cmpblsb r2, r3, \*\+0x78
42: 84 31 00 55 cmpblsb r4, r5, \*\+0x100
46: 80 00
48: c6 30 84 65 cmpblsb \$0xffffffff, r6, \*\-0xf8
4c: c7 31 ff 75 cmpblsb \$0x7, r7, \*\-0x102
50: 7f ff
00000052 <cmpbgtb>:
52: 88 30 83 96 cmpbgtb r8, r9, \*\-0xfa
56: 8a 31 00 b6 cmpbgtb r10, r11, \*\+0xfc0
5a: e0 07
5c: c8 30 7f c6 cmpbgtb \$0x8, r12, \*\+0xfe
60: c9 31 7f d6 cmpbgtb \$0x10, r13, \*\+0xfffff2
64: f9 ff
00000066 <cmpbleb>:
66: 8e 30 81 f7 cmpbleb r14, r15, \*\-0xfe
6a: 8e 31 ff f7 cmpbleb r14, r15, \*\-0x200
6e: 00 ff
70: c9 30 1b 17 cmpbleb \$0x10, r1, \*\+0x36
74: c9 31 80 27 cmpbleb \$0x10, r2, \*\-0xffff02
78: 7f 00
0000007a <cmpblob>:
7a: 83 30 e4 4a cmpblob r3, r4, \*\-0x38
7e: 85 31 80 6a cmpblob r5, r6, \*\-0xfffffe
82: 01 00
84: ca 30 12 7a cmpblob \$0x20, r7, \*\+0x24
88: ca 31 7f 8a cmpblob \$0x20, r8, \*\+0xfffffe
8c: ff ff
0000008e <cmpbhsb>:
8e: 89 30 78 ab cmpbhsb r9, r10, \*\+0xf0
92: 8b 31 00 cb cmpbhsb r11, r12, \*\+0x102
96: 81 00
98: ca 30 81 db cmpbhsb \$0x20, r13, \*\-0xfe
9c: cb 31 00 eb cmpbhsb \$0x14, r14, \*\+0x1000
a0: 00 08
000000a2 <cmpbltb>:
a2: 8f 30 08 ec cmpbltb r15, r14, \*\+0x10
a6: 8f 31 00 1c cmpbltb r15, r1, \*\+0x462
aa: 31 02
ac: cc 30 f8 2c cmpbltb \$0xc, r2, \*\-0x10
b0: cc 31 c0 3c cmpbltb \$0xc, r3, \*\-0x800000
b4: 00 00
000000b6 <cmpbgeb>:
b6: 84 30 00 5d cmpbgeb r4, r5, \*\+0x0
ba: 86 31 20 7d cmpbgeb r6, r7, \*\+0x400000
be: 00 00
c0: cd 30 00 8d cmpbgeb \$0x30, r8, \*\+0x0
c4: cd 31 f8 9d cmpbgeb \$0x30, r9, \*\-0x100000
c8: 00 00
000000ca <cmpbeqw>:
ca: 91 30 2b 20 cmpbeqw r1, r2, \*\+0x56
ce: 93 31 00 40 cmpbeqw r3, r4, \*\+0x4348
d2: a4 21
d4: d0 30 1b 50 cmpbeqw \$0x0, r5, \*\+0x36
d8: d1 31 1a 60 cmpbeqw \$0x1, r6, \*\+0x345678
dc: 3c 2b
000000de <cmpbnew>:
de: 97 30 7d 81 cmpbnew r7, r8, \*\+0xfa
e2: 99 31 00 a1 cmpbnew r9, r10, \*\+0xf000
e6: 00 78
e8: d2 30 01 b1 cmpbnew \$0x2, r11, \*\+0x2
ec: d3 31 7f c1 cmpbnew \$0x3, r12, \*\+0xfffffe
f0: ff ff
000000f2 <cmpbhiw>:
f2: 9d 31 00 e4 cmpbhiw r13, r14, \*\+0x100
f6: 80 00
f8: 9f 31 00 e4 cmpbhiw r15, r14, \*\+0x102
fc: 81 00
fe: d4 30 ff f4 cmpbhiw \$0x4, r15, \*\-0x2
102: d5 31 ff 14 cmpbhiw \$0xfffffffc, r1, \*\-0x104
106: 7e ff
00000108 <cmpblsw>:
108: 92 30 3c 35 cmpblsw r2, r3, \*\+0x78
10c: 94 31 00 55 cmpblsw r4, r5, \*\+0x100
110: 80 00
112: d6 30 84 65 cmpblsw \$0xffffffff, r6, \*\-0xf8
116: d7 31 ff 75 cmpblsw \$0x7, r7, \*\-0x102
11a: 7f ff
0000011c <cmpbgtw>:
11c: 98 30 83 96 cmpbgtw r8, r9, \*\-0xfa
120: 9a 31 00 b6 cmpbgtw r10, r11, \*\+0xfc0
124: e0 07
126: d8 30 7f c6 cmpbgtw \$0x8, r12, \*\+0xfe
12a: d9 31 7f d6 cmpbgtw \$0x10, r13, \*\+0xfffff2
12e: f9 ff
00000130 <cmpblew>:
130: 9e 30 81 f7 cmpblew r14, r15, \*\-0xfe
134: 9e 31 ff f7 cmpblew r14, r15, \*\-0x200
138: 00 ff
13a: d9 30 1b 17 cmpblew \$0x10, r1, \*\+0x36
13e: d9 31 80 27 cmpblew \$0x10, r2, \*\-0xffff02
142: 7f 00
00000144 <cmpblow>:
144: 93 30 e4 4a cmpblow r3, r4, \*\-0x38
148: 95 31 80 6a cmpblow r5, r6, \*\-0xfffffe
14c: 01 00
14e: da 30 12 7a cmpblow \$0x20, r7, \*\+0x24
152: da 31 7f 8a cmpblow \$0x20, r8, \*\+0xfffffe
156: ff ff
00000158 <cmpbhsw>:
158: 99 30 78 ab cmpbhsw r9, r10, \*\+0xf0
15c: 9b 31 00 cb cmpbhsw r11, r12, \*\+0x102
160: 81 00
162: da 30 81 db cmpbhsw \$0x20, r13, \*\-0xfe
166: db 31 00 eb cmpbhsw \$0x14, r14, \*\+0x1000
16a: 00 08
0000016c <cmpbltw>:
16c: 9f 30 08 ec cmpbltw r15, r14, \*\+0x10
170: 9f 31 00 1c cmpbltw r15, r1, \*\+0x462
174: 31 02
176: dc 30 f8 2c cmpbltw \$0xc, r2, \*\-0x10
17a: dc 31 c0 3c cmpbltw \$0xc, r3, \*\-0x800000
17e: 00 00
00000180 <cmpbgew>:
180: 94 30 00 5d cmpbgew r4, r5, \*\+0x0
184: 96 31 20 7d cmpbgew r6, r7, \*\+0x400000
188: 00 00
18a: dd 30 00 8d cmpbgew \$0x30, r8, \*\+0x0
18e: dd 31 f8 9d cmpbgew \$0x30, r9, \*\-0x100000
192: 00 00
00000194 <cmpbeqd>:
194: a1 30 2b 20 cmpbeqd r1, r2, \*\+0x56
198: a3 31 00 40 cmpbeqd r3, r4, \*\+0x4348
19c: a4 21
19e: e0 30 1b 50 cmpbeqd \$0x0, r5, \*\+0x36
1a2: e1 31 1a 60 cmpbeqd \$0x1, r6, \*\+0x345678
1a6: 3c 2b
000001a8 <cmpbned>:
1a8: a7 30 7d 81 cmpbned r7, r8, \*\+0xfa
1ac: a9 31 00 a1 cmpbned r9, r10, \*\+0xf000
1b0: 00 78
1b2: e2 30 01 b1 cmpbned \$0x2, r11, \*\+0x2
1b6: e3 31 7f c1 cmpbned \$0x3, r12, \*\+0xfffffe
1ba: ff ff
000001bc <cmpbhid>:
1bc: ad 31 00 e4 cmpbhid r13, r14, \*\+0x100
1c0: 80 00
1c2: af 31 00 e4 cmpbhid r15, r14, \*\+0x102
1c6: 81 00
1c8: e4 30 ff f4 cmpbhid \$0x4, r15, \*\-0x2
1cc: e5 31 ff 14 cmpbhid \$0xfffffffc, r1, \*\-0x104
1d0: 7e ff
000001d2 <cmpblsd>:
1d2: a2 30 3c 35 cmpblsd r2, r3, \*\+0x78
1d6: a4 31 00 55 cmpblsd r4, r5, \*\+0x100
1da: 80 00
1dc: e6 30 84 65 cmpblsd \$0xffffffff, r6, \*\-0xf8
1e0: e7 31 ff 75 cmpblsd \$0x7, r7, \*\-0x102
1e4: 7f ff
000001e6 <cmpbgtd>:
1e6: a8 30 83 96 cmpbgtd r8, r9, \*\-0xfa
1ea: aa 31 00 b6 cmpbgtd r10, r11, \*\+0xfc0
1ee: e0 07
1f0: e8 30 7f c6 cmpbgtd \$0x8, r12, \*\+0xfe
1f4: e9 31 7f d6 cmpbgtd \$0x10, r13, \*\+0xfffff2
1f8: f9 ff
000001fa <cmpbled>:
1fa: ae 30 81 f7 cmpbled r14, r15, \*\-0xfe
1fe: ae 31 ff f7 cmpbled r14, r15, \*\-0x200
202: 00 ff
204: e9 30 1b 17 cmpbled \$0x10, r1, \*\+0x36
208: e9 31 80 27 cmpbled \$0x10, r2, \*\-0xffff02
20c: 7f 00
0000020e <cmpblod>:
20e: a3 30 e4 4a cmpblod r3, r4, \*\-0x38
212: a5 31 80 6a cmpblod r5, r6, \*\-0xfffffe
216: 01 00
218: ea 30 12 7a cmpblod \$0x20, r7, \*\+0x24
21c: ea 31 7f 8a cmpblod \$0x20, r8, \*\+0xfffffe
220: ff ff
00000222 <cmpbhsd>:
222: a9 30 78 ab cmpbhsd r9, r10, \*\+0xf0
226: ab 31 00 cb cmpbhsd r11, r12, \*\+0x102
22a: 81 00
22c: ea 30 81 db cmpbhsd \$0x20, r13, \*\-0xfe
230: eb 31 00 eb cmpbhsd \$0x14, r14, \*\+0x1000
234: 00 08
00000236 <cmpbltd>:
236: af 30 08 ec cmpbltd r15, r14, \*\+0x10
23a: af 31 00 1c cmpbltd r15, r1, \*\+0x462
23e: 31 02
240: ec 30 f8 2c cmpbltd \$0xc, r2, \*\-0x10
244: ec 31 c0 3c cmpbltd \$0xc, r3, \*\-0x800000
248: 00 00
0000024a <cmpbged>:
24a: a4 30 00 5d cmpbged r4, r5, \*\+0x0
24e: a6 31 20 7d cmpbged r6, r7, \*\+0x400000
252: 00 00
254: ed 30 00 8d cmpbged \$0x30, r8, \*\+0x0
258: ed 31 f8 9d cmpbged \$0x30, r9, \*\-0x100000
25c: 00 00

217
gas/testsuite/gas/crx/cmpbr_insn.s Normal file
View File

@ -0,0 +1,217 @@
# 'Compare & Branch' instructions.
.data
foodata: .word 42
.text
footext:
.global cmpbeqb
cmpbeqb:
cmpbeqb r1, r2, 0x56
cmpbeqb r3, r4, 0x4348
cmpbeqb $0, r5, 0x36
cmpbeqb $1, r6, 0x345678
.global cmpbneb
cmpbneb:
cmpbneb r7, r8, 250
cmpbneb r9, r10, 0xf000
cmpbneb $2, r11, 0x2
cmpbneb $3, r12, 0xfffffe
.global cmpbhib
cmpbhib:
cmpbhib r13, r14, 0400
cmpbhib r15, ra, 258
cmpbhib $4, sp, -0x2
cmpbhib $-4, r1, -260
.global cmpblsb
cmpblsb:
cmpblsb r2, r3, 0x78
cmpblsb r4, r5, 0x100
cmpblsb $-1, r6, -0370
cmpblsb $7, r7, -0x102
.global cmpbgtb
cmpbgtb:
cmpbgtb r8, r9, -250
cmpbgtb r10, r11, 07700
cmpbgtb $8, r12, 0xfe
cmpbgtb $16, r13, 0xfffff2
.global cmpbleb
cmpbleb:
cmpbleb r14, r15, -0xfe
cmpbleb ra, sp, -01000
cmpbleb $0x10, r1, 066
cmpbleb $020, r2, -0xffff02
.global cmpblob
cmpblob:
cmpblob r3, r4, -070
cmpblob r5, r6, -0xfffffe
cmpblob $32, r7, +0x24
cmpblob $0x20, r8, 16777214
.global cmpbhsb
cmpbhsb:
cmpbhsb r9, r10, 0xf0
cmpbhsb r11, r12, 0402
cmpbhsb $040, r13, -254
cmpbhsb $20, r14, 0x1000
.global cmpbltb
cmpbltb:
cmpbltb r15, ra, 0x10
cmpbltb sp, r1, 1122
cmpbltb $12, r2, -020
cmpbltb $0xc, r3, -0x800000
.global cmpbgeb
cmpbgeb:
cmpbgeb r4, r5, 0x0
cmpbgeb r6, r7, 0x400000
cmpbgeb $48, r8, 0
cmpbgeb $060, r9, -0x100000
.global cmpbeqw
cmpbeqw:
cmpbeqw r1, r2, 0x56
cmpbeqw r3, r4, 0x4348
cmpbeqw $0, r5, 0x36
cmpbeqw $1, r6, 0x345678
.global cmpbnew
cmpbnew:
cmpbnew r7, r8, 250
cmpbnew r9, r10, 0xf000
cmpbnew $2, r11, 0x2
cmpbnew $3, r12, 0xfffffe
.global cmpbhiw
cmpbhiw:
cmpbhiw r13, r14, 0400
cmpbhiw r15, ra, 258
cmpbhiw $4, sp, -0x2
cmpbhiw $-4, r1, -260
.global cmpblsw
cmpblsw:
cmpblsw r2, r3, 0x78
cmpblsw r4, r5, 0x100
cmpblsw $-1, r6, -0370
cmpblsw $7, r7, -0x102
.global cmpbgtw
cmpbgtw:
cmpbgtw r8, r9, -250
cmpbgtw r10, r11, 07700
cmpbgtw $8, r12, 0xfe
cmpbgtw $16, r13, 0xfffff2
.global cmpblew
cmpblew:
cmpblew r14, r15, -0xfe
cmpblew ra, sp, -01000
cmpblew $0x10, r1, 066
cmpblew $020, r2, -0xffff02
.global cmpblow
cmpblow:
cmpblow r3, r4, -070
cmpblow r5, r6, -0xfffffe
cmpblow $32, r7, +0x24
cmpblow $0x20, r8, 16777214
.global cmpbhsw
cmpbhsw:
cmpbhsw r9, r10, 0xf0
cmpbhsw r11, r12, 0402
cmpbhsw $040, r13, -254
cmpbhsw $20, r14, 0x1000
.global cmpbltw
cmpbltw:
cmpbltw r15, ra, 0x10
cmpbltw sp, r1, 1122
cmpbltw $12, r2, -020
cmpbltw $0xc, r3, -0x800000
.global cmpbgew
cmpbgew:
cmpbgew r4, r5, 0x0
cmpbgew r6, r7, 0x400000
cmpbgew $48, r8, 0
cmpbgew $060, r9, -0x100000
.global cmpbeqd
cmpbeqd:
cmpbeqd r1, r2, 0x56
cmpbeqd r3, r4, 0x4348
cmpbeqd $0, r5, 0x36
cmpbeqd $1, r6, 0x345678
.global cmpbned
cmpbned:
cmpbned r7, r8, 250
cmpbned r9, r10, 0xf000
cmpbned $2, r11, 0x2
cmpbned $3, r12, 0xfffffe
.global cmpbhid
cmpbhid:
cmpbhid r13, r14, 0400
cmpbhid r15, ra, 258
cmpbhid $4, sp, -0x2
cmpbhid $-4, r1, -260
.global cmpblsd
cmpblsd:
cmpblsd r2, r3, 0x78
cmpblsd r4, r5, 0x100
cmpblsd $-1, r6, -0370
cmpblsd $7, r7, -0x102
.global cmpbgtd
cmpbgtd:
cmpbgtd r8, r9, -250
cmpbgtd r10, r11, 07700
cmpbgtd $8, r12, 0xfe
cmpbgtd $16, r13, 0xfffff2
.global cmpbled
cmpbled:
cmpbled r14, r15, -0xfe
cmpbled ra, sp, -01000
cmpbled $0x10, r1, 066
cmpbled $020, r2, -0xffff02
.global cmpblod
cmpblod:
cmpblod r3, r4, -070
cmpblod r5, r6, -0xfffffe
cmpblod $32, r7, +0x24
cmpblod $0x20, r8, 16777214
.global cmpbhsd
cmpbhsd:
cmpbhsd r9, r10, 0xf0
cmpbhsd r11, r12, 0402
cmpbhsd $040, r13, -254
cmpbhsd $20, r14, 0x1000
.global cmpbltd
cmpbltd:
cmpbltd r15, ra, 0x10
cmpbltd sp, r1, 1122
cmpbltd $12, r2, -020
cmpbltd $0xc, r3, -0x800000
.global cmpbged
cmpbged:
cmpbged r4, r5, 0x0
cmpbged r6, r7, 0x400000
cmpbged $48, r8, 0
cmpbged $060, r9, -0x100000

94
gas/testsuite/gas/crx/jscond_insn.d Normal file
View File

@ -0,0 +1,94 @@
#as:
#objdump: -dr
#name: jscond_insn
.*: +file format .*
Disassembly of section .text:
00000000 <jeq>:
0: 01 ba jeq r1
00000002 <jne>:
2: 12 ba jne r2
00000004 <jcs>:
4: 23 ba jcs r3
00000006 <jcc>:
6: 34 ba jcc r4
00000008 <jhi>:
8: 45 ba jhi r5
0000000a <jls>:
a: 56 ba jls r6
0000000c <jgt>:
c: 67 ba jgt r7
0000000e <jle>:
e: 78 ba jle r8
00000010 <jfs>:
10: 89 ba jfs r9
00000012 <jfc>:
12: 9a ba jfc r10
00000014 <jlo>:
14: ab ba jlo r11
00000016 <jhs>:
16: bc ba jhs r12
00000018 <jlt>:
18: cd ba jlt r13
0000001a <jge>:
1a: de ba jge r14
0000001c <jump>:
1c: ef ba jump r15
0000001e <seq>:
1e: 01 bb seq r1
00000020 <sne>:
20: 12 bb sne r2
00000022 <scs>:
22: 23 bb scs r3
00000024 <scc>:
24: 34 bb scc r4
00000026 <shi>:
26: 45 bb shi r5
00000028 <sls>:
28: 56 bb sls r6
0000002a <sgt>:
2a: 67 bb sgt r7
0000002c <sle>:
2c: 78 bb sle r8
0000002e <sfs>:
2e: 89 bb sfs r9
00000030 <sfc>:
30: 9a bb sfc r10
00000032 <slo>:
32: ab bb slo r11
00000034 <shs>:
34: bc bb shs r12
00000036 <slt>:
36: cd bb slt r13
00000038 <sge>:
38: de bb sge r14

121
gas/testsuite/gas/crx/jscond_insn.s Normal file
View File

@ -0,0 +1,121 @@
# JCond/SCond instructions.
.data
foodata: .word 42
.text
footext:
.global jeq
jeq:
jeq r1
.global jne
jne:
jne r2
.global jcs
jcs:
jcs r3
.global jcc
jcc:
jcc r4
.global jhi
jhi:
jhi r5
.global jls
jls:
jls r6
.global jgt
jgt:
jgt r7
.global jle
jle:
jle r8
.global jfs
jfs:
jfs r9
.global jfc
jfc:
jfc r10
.global jlo
jlo:
jlo r11
.global jhs
jhs:
jhs r12
.global jlt
jlt:
jlt r13
.global jge
jge:
jge ra
.global jump
jump:
jump sp
.global seq
seq:
seq r1
.global sne
sne:
sne r2
.global scs
scs:
scs r3
.global scc
scc:
scc r4
.global shi
shi:
shi r5
.global sls
sls:
sls r6
.global sgt
sgt:
sgt r7
.global sle
sle:
sle r8
.global sfs
sfs:
sfs r9
.global sfc
sfc:
sfc r10
.global slo
slo:
slo r11
.global shs
shs:
shs r12
.global slt
slt:
slt r13
.global sge
sge:
sge ra

40
gas/testsuite/gas/crx/list_insn.d Normal file
View File

@ -0,0 +1,40 @@
#as:
#objdump: -dr
#name: list_insn
.*: +file format .*
Disassembly of section .text:
00000000 <push>:
0: 6e 34 18 00 push r14, {r3,r4}
4: b2 ff push r2
00000006 <pushx>:
6: 7f 34 ff 00 pushx r15, {r0,r1,r2,r3,r4,r5,r6,r7}
0000000a <pop>:
a: 40 32 00 04 loadm r0, {r10}
e: c2 ff pop r2
00000010 <popx>:
10: 7f 32 fb 00 popx r15, {r0,r1,r3,r4,r5,r6,r7}
00000014 <popret>:
14: 6e 32 02 40 popret r14, {r1,r14}
18: de ff popret r14
0000001a <loadm>:
1a: 40 32 03 00 loadm r0, {r0,r1}
0000001e <loadma>:
1e: 5d 32 14 10 popa r13, {r2,r4,r12}
00000022 <popa>:
22: 5e 32 00 80 popa r14, {r15}
00000026 <storm>:
26: 4f 34 00 40 storm r15, {r14}
0000002a <storma>:
2a: 53 34 01 00 storma r3, {r0}

49
gas/testsuite/gas/crx/list_insn.s Normal file
View File

@ -0,0 +1,49 @@
# Instructions including a register list (opcode is represented as a mask).
.data
foodata: .word 42
.text
footext:
.global push
push:
push ra, {r3, r4}
push r2
.global pushx
pushx:
pushx sp, {r0, r1, r2, r3, r4, r5, r6, r7}
.global pop
pop:
pop r0, {r10}
pop r2
.global popx
popx:
popx sp, {r0, r1, r3, r4, r5, r6, r7}
.global popret
popret:
popret r14, {ra, r1}
popret ra
.global loadm
loadm:
loadm r0, {r1, r0}
.global loadma
loadma:
loadma r13, {r12, r4, r2}
.global popa
popa:
popa ra, {r15}
.global storm
storm:
storm r15, {ra}
.global storma
storma:
storma r3, {r0}

150
gas/testsuite/gas/crx/load_stor_insn.d Normal file
View File

@ -0,0 +1,150 @@
#as:
#objdump: -dr
#name: load_stor_insn
.*: +file format .*
Disassembly of section .text:
00000000 <loadb>:
0: 01 33 00 00 loadb 0x632, r1
4: 32 06
6: 02 33 08 00 loadb 0x87632, r2
a: 32 76
c: 03 32 34 12 loadb 0xffff1234, r3
10: 95 84 loadb 0x9\(r5\), r4
12: 0f 86 loadb 0x0\(r15\), r6
14: e6 87 56 04 loadb 0x456\(r6\), r7
18: e8 8a aa fb loadb 0xfbaa\(r8\), r10
1c: fd 8c 04 00 loadb 0x45678\(r13\), r12
20: 78 56
22: f9 8f a9 fb loadb 0xfba9876e\(r9\), r15
26: 6e 87
28: 8e 32 09 f0 loadb 0x9\(r15\)\+, r14
2c: 82 32 de df loadb 0xfde\(r13\)\+, r2
30: cd 33 40 9c loadb 0x45\(r9,r12,2\), r13
34: 45 00
36: ce 33 3f f7 loadb 0x3ffd6f\(r15,r7,1\), r14
3a: 6f fd
0000003c <loadw>:
3c: 11 33 00 00 loadw 0x19a, r1
40: 9a 01
42: 12 33 01 00 loadw 0x15650, r2
46: 50 56
48: 13 32 06 00 loadw 0xffff0006, r3
4c: 1f 94 loadw 0x2\(r15\), r4
4e: 0f 96 loadw 0x0\(r15\), r6
50: e6 97 2e 01 loadw 0x12e\(r6\), r7
54: e8 9a 01 f8 loadw 0xf801\(r8\), r10
58: fd 9c 06 00 loadw 0x6f855\(r13\), r12
5c: 55 f8
5e: f9 9f 00 ff loadw 0xff000000\(r9\), r15
62: 00 00
64: 9e 32 08 20 loadw 0x8\(r2\)\+, r14
68: 92 32 cc df loadw 0xfcc\(r13\)\+, r2
6c: dd 33 80 9c loadw 0x25\(r9,r12,4\), r13
70: 25 00
72: de 33 ff f7 loadw 0x3f99a9\(r15,r7,8\), r14
76: a9 99
00000078 <loadd>:
78: 21 33 00 00 loadd 0xfff1, r1
7c: f1 ff
7e: 22 33 ef ff loadd 0xffefffef, r2
82: ef ff
84: 23 32 34 12 loadd 0xffff1234, r3
88: e0 a4 0a 00 loadd 0xa\(r0\), r4
8c: 0f a6 loadd 0x0\(r15\), r6
8e: e6 a7 00 01 loadd 0x100\(r6\), r7
92: e8 aa 00 ff loadd 0xff00\(r8\), r10
96: fd ac 01 00 loadd 0x12000\(r13\), r12
9a: 00 20
9c: f9 af ce ff loadd 0xffce0000\(r9\), r15
a0: 00 00
a2: ae 32 07 f0 loadd 0x7\(r15\)\+, r14
a6: a2 32 ce ef loadd 0xfce\(r14\)\+, r2
aa: ed 33 40 9c loadd 0x2d\(r9,r12,2\), r13
ae: 2d 00
b0: ee 33 3f f7 loadd 0x3ffe51\(r15,r7,1\), r14
b4: 51 fe
000000b6 <storb>:
b6: 01 35 00 00 storb r1, 0x632
ba: 32 06
bc: 02 35 08 00 storb r2, 0x87632
c0: 32 76
c2: 03 34 34 12 storb r3, 0xffff1234
c6: 95 c4 storb r4, 0x9\(r5\)
c8: 0f c6 storb r6, 0x0\(r15\)
ca: e6 c7 56 04 storb r7, 0x456\(r6\)
ce: e8 ca aa fb storb r10, 0xfbaa\(r8\)
d2: fd cc 04 00 storb r12, 0x45678\(r13\)
d6: 78 56
d8: f9 cf a9 fb storb r15, 0xfba9876e\(r9\)
dc: 6e 87
de: 8e 34 09 f0 storb r14, 0x9\(r15\)\+
e2: 82 34 de df storb r2, 0xfde\(r13\)\+
e6: cd 35 40 9c storb r13, 0x45\(r9,r12,2\)
ea: 45 00
ec: ce 35 3f f7 storb r14, 0x3ffd6f\(r15,r7,1\)
f0: 6f fd
f2: 45 36 09 40 storb \$0x5, 0x9\(r4\)
f6: 4f 37 ff 3f storb \$0xf, 0xffff013\(r3\)
fa: 13 f0
000000fc <storw>:
fc: 11 35 00 00 storw r1, 0x19a
100: 9a 01
102: 12 35 01 00 storw r2, 0x15650
106: 50 56
108: 13 34 06 00 storw r3, 0xffff0006
10c: 1f d4 storw r4, 0x2\(r15\)
10e: 0f d6 storw r6, 0x0\(r15\)
110: e6 d7 2e 01 storw r7, 0x12e\(r6\)
114: e8 da 01 f8 storw r10, 0xf801\(r8\)
118: fd dc 06 00 storw r12, 0x6f855\(r13\)
11c: 55 f8
11e: f9 df 00 ff storw r15, 0xff000000\(r9\)
122: 00 00
124: 9e 34 08 20 storw r14, 0x8\(r2\)\+
128: 92 34 cc df storw r2, 0xfcc\(r13\)\+
12c: dd 35 80 9c storw r13, 0x25\(r9,r12,4\)
130: 25 00
132: de 35 ff f7 storw r14, 0x3f99a9\(r15,r7,8\)
136: a9 99
138: 11 37 00 00 storw \$0x1, 0x632
13c: 32 06
13e: 17 37 08 00 storw \$0x7, 0x87632
142: 32 76
00000144 <stord>:
144: 21 35 00 00 stord r1, 0xfff1
148: f1 ff
14a: 22 35 ef ff stord r2, 0xffefffef
14e: ef ff
150: 23 34 01 00 stord r3, 0xffff0001
154: e0 e4 0a 00 stord r4, 0xa\(r0\)
158: 0f e6 stord r6, 0x0\(r15\)
15a: e6 e7 00 01 stord r7, 0x100\(r6\)
15e: e8 ea 00 ff stord r10, 0xff00\(r8\)
162: fd ec 01 00 stord r12, 0x12000\(r13\)
166: 00 20
168: f9 ef ce ff stord r15, 0xffce0000\(r9\)
16c: 00 00
16e: ae 34 07 f0 stord r14, 0x7\(r15\)\+
172: a2 34 ce ef stord r2, 0xfce\(r14\)\+
176: ed 35 40 9c stord r13, 0x2d\(r9,r12,2\)
17a: 2d 00
17c: ee 35 3f f7 stord r14, 0x3ffe51\(r15,r7,1\)
180: 51 fe
182: af 36 05 a0 stord \$0xf, 0x5\(r10\)\+
186: a0 36 e4 bf stord \$0x0, 0xfe4\(r11\)\+
0000018a <loadmcr>:
18a: 13 31 01 30 loadmcr \$0x3, r1, {c2,c3,c5}
18e: 2c 00
00000190 <stormcr>:
190: 1f 31 1e 30 stormcr \$0xf, r14, {c4,c7,c9,c10}
194: 90 06

118
gas/testsuite/gas/crx/load_stor_insn.s Normal file
View File

@ -0,0 +1,118 @@
# Load/Store instructions.
.data
foodata: .word 42
.text
footext:
# Load instructions (memory to register).
.global loadb
loadb:
loadb 0x632, r1
loadb 0x87632, r2
loadb 0xffff1234, r3
loadb 9(r5), r4
loadb 0(sp), r6
loadb 0x456(r6), r7
loadb -0x456(r8), r10
loadb 0x45678(r13), r12
loadb -0x4567892(r9), sp
loadb 0x9(sp)+, ra
loadb -34(r13)+, r2
loadb 0x45(r9,r12,2), r13
loadb -657(r15,r7,1), r14
.global loadw
loadw:
loadw 0632, r1
loadw 87632, r2
loadw 0xffff0006, r3
loadw 2(r15), r4
loadw 0(sp), r6
loadw 0456(r6), r7
loadw -0x7ff(r8), r10
loadw 456789(r13), r12
loadw -16777216(r9), sp
loadw 010(r2)+, ra
loadw -0x34(r13)+, r2
loadw 045(r9,r12,4), r13
loadw -0x6657(r15,r7,8), r14
.global loadd
loadd:
loadd 0xfff1, r1
loadd 0xffefffef, r2
loadd 0xffff1234, r3
loadd 10(r0), r4
loadd 0(sp), r6
loadd 0x100(r6), r7
loadd -0x100(r8), r10
loadd 0220000(r13), r12
loadd -014400000(r9), sp
loadd 07(sp)+, ra
loadd -50(ra)+, r2
loadd 45(r9,r12,2), r13
loadd -0657(r15,r7,1), r14
# Store instructions (register/immediate to memory).
.global storb
storb:
storb r1, 0x632
storb r2, 0x87632
storb r3, 0xffff1234
storb r4, 9(r5)
storb r6, 0(sp)
storb r7, 0x456(r6)
storb r10, -0x456(r8)
storb r12, 0x45678(r13)
storb sp, -0x4567892(r9)
storb ra, 0x9(sp)+
storb r2, -34(r13)+
storb r13, 0x45(r9,r12,2)
storb r14, -657(r15,r7,1)
storb $5, 9(r4)
storb $15, -0xfed(r3)
.global storw
storw:
storw r1, 0632
storw r2, 87632
storw r3, 0xffff0006
storw r4, 2(r15)
storw r6, 0(sp)
storw r7, 0456(r6)
storw r10, -0x7ff(r8)
storw r12, 456789(r13)
storw sp, -16777216(r9)
storw ra, 010(r2)+
storw r2, -0x34(r13)+
storw r13, 045(r9,r12,4)
storw r14, -0x6657(r15,r7,8)
storw $01, 0x632
storw $0x7, 0x87632
.global stord
stord:
stord r1, 0xfff1
stord r2, 0xffefffef
stord r3, 0xffff0001
stord r4, 10(r0)
stord r6, 0(sp)
stord r7, 0x100(r6)
stord r10, -0x100(r8)
stord r12, 0220000(r13)
stord sp, -014400000(r9)
stord ra, 07(sp)+
stord r2, -50(ra)+
stord r13, 45(r9,r12,2)
stord r14, -0657(r15,r7,1)
stord $0xf, 05(r10)+
stord $0x0, -034(r11)+
# CO-processor registers
.global loadmcr
loadmcr:
loadmcr $3, r1, {c2,c3,c5}
.global stormcr
stormcr:
stormcr $15, ra, {c10,c9,c7,c4}

260
gas/testsuite/gas/crx/misc_insn.d Normal file
View File

@ -0,0 +1,260 @@
#as:
#objdump: -dr
#name: load_stor_insn
.*: +file format .*
Disassembly of section .text:
00000000 <macsb>:
0: 08 30 01 40 macsb r0, r1
00000004 <macub>:
4: 08 30 23 41 macub r2, r3
00000008 <macqb>:
8: 08 30 45 42 macqb r4, r5
0000000c <macsw>:
c: 08 30 67 50 macsw r6, r7
00000010 <macuw>:
10: 08 30 89 51 macuw r8, r9
00000014 <macqw>:
14: 08 30 ab 52 macqw r10, r11
00000018 <macsd>:
18: 08 30 cd 60 macsd r12, r13
0000001c <macud>:
1c: 08 30 ef 61 macud r14, r15
00000020 <macqd>:
20: 08 30 ef 62 macqd r14, r15
00000024 <mullsd>:
24: 08 30 02 65 mullsd r0, r2
00000028 <mullud>:
28: 08 30 13 66 mullud r1, r3
0000002c <mulsbw>:
2c: 08 30 46 3b mulsbw r4, r6
00000030 <mulubw>:
30: 08 30 57 3c mulubw r5, r7
00000034 <mulswd>:
34: 08 30 8a 3d mulswd r8, r10
00000038 <muluwd>:
38: 08 30 9b 3e muluwd r9, r11
0000003c <sextbw>:
3c: 08 30 ce 30 sextbw r12, r14
00000040 <sextbd>:
40: 08 30 df 31 sextbd r13, r15
00000044 <sextwd>:
44: 08 30 ef 32 sextwd r14, r15
00000048 <zextbw>:
48: 08 30 50 34 zextbw r5, r0
0000004c <zextbd>:
4c: 08 30 a6 35 zextbd r10, r6
00000050 <zextwd>:
50: 08 30 7f 36 zextwd r7, r15
00000054 <getrfid>:
54: 9e ff getrfid r14
00000056 <setrfid>:
56: af ff setrfid r15
00000058 <bswap>:
58: 08 30 e2 3f bswap r14, r2
0000005c <maxsb>:
5c: 08 30 83 80 maxsb r8, r3
00000060 <minsb>:
60: 08 30 fe 81 minsb r15, r14
00000064 <maxub>:
64: 08 30 dc 82 maxub r13, r12
00000068 <minub>:
68: 08 30 ba 83 minub r11, r10
0000006c <absb>:
6c: 08 30 98 84 absb r9, r8
00000070 <negb>:
70: 08 30 76 85 negb r7, r6
00000074 <cntl0b>:
74: 08 30 54 86 cntl0b r5, r4
00000078 <cntl1b>:
78: 08 30 32 87 cntl1b r3, r2
0000007c <popcntb>:
7c: 08 30 10 88 popcntb r1, r0
00000080 <rotlb>:
80: 08 30 b4 89 rotlb r11, r4
00000084 <rotrb>:
84: 08 30 72 8a rotrb r7, r2
00000088 <mulqb>:
88: 08 30 ee 8b mulqb r14, r14
0000008c <addqb>:
8c: 08 30 ff 8c addqb r15, r15
00000090 <subqb>:
90: 08 30 0a 8d subqb r0, r10
00000094 <cntlsb>:
94: 08 30 2c 8e cntlsb r2, r12
00000098 <maxsw>:
98: 08 30 83 90 maxsw r8, r3
0000009c <minsw>:
9c: 08 30 fe 91 minsw r15, r14
000000a0 <maxuw>:
a0: 08 30 dc 92 maxuw r13, r12
000000a4 <minuw>:
a4: 08 30 ba 93 minuw r11, r10
000000a8 <absw>:
a8: 08 30 98 94 absw r9, r8
000000ac <negw>:
ac: 08 30 76 95 negw r7, r6
000000b0 <cntl0w>:
b0: 08 30 54 96 cntl0w r5, r4
000000b4 <cntl1w>:
b4: 08 30 32 97 cntl1w r3, r2
000000b8 <popcntw>:
b8: 08 30 10 98 popcntw r1, r0
000000bc <rotlw>:
bc: 08 30 b4 99 rotlw r11, r4
000000c0 <rotrw>:
c0: 08 30 72 9a rotrw r7, r2
000000c4 <mulqw>:
c4: 08 30 ee 9b mulqw r14, r14
000000c8 <addqw>:
c8: 08 30 ff 9c addqw r15, r15
000000cc <subqw>:
cc: 08 30 0a 9d subqw r0, r10
000000d0 <cntlsw>:
d0: 08 30 2c 9e cntlsw r2, r12
000000d4 <maxsd>:
d4: 08 30 83 a0 maxsd r8, r3
000000d8 <minsd>:
d8: 08 30 fe a1 minsd r15, r14
000000dc <maxud>:
dc: 08 30 dc a2 maxud r13, r12
000000e0 <minud>:
e0: 08 30 ba a3 minud r11, r10
000000e4 <absd>:
e4: 08 30 98 a4 absd r9, r8
000000e8 <negd>:
e8: 08 30 76 a5 negd r7, r6
000000ec <cntl0d>:
ec: 08 30 54 a6 cntl0d r5, r4
000000f0 <cntl1d>:
f0: 08 30 32 a7 cntl1d r3, r2
000000f4 <popcntd>:
f4: 08 30 10 a8 popcntd r1, r0
000000f8 <rotld>:
f8: 08 30 b4 a9 rotld r11, r4
000000fc <rotrd>:
fc: 08 30 72 aa rotrd r7, r2
00000100 <mulqd>:
100: 08 30 ee ab mulqd r14, r14
00000104 <addqd>:
104: 08 30 ff ac addqd r15, r15
00000108 <subqd>:
108: 08 30 0a ad subqd r0, r10
0000010c <cntlsd>:
10c: 08 30 2c ae cntlsd r2, r12
00000110 <mtpr>:
110: 09 30 10 00 mtpr r0, hi
00000114 <mfpr>:
114: 0a 30 05 11 mfpr lo, r5
118: 0a 30 0a 90 mfpr uhi, r10
0000011c <mtcr>:
11c: 1f 30 1e 30 mtcr \$0xf, r1, c14
00000120 <mfcr>:
120: 13 30 72 31 mfcr \$0x3, c7, r2
00000124 <mtcsr>:
124: 12 30 51 32 mtcsr \$0x2, r5, cs1
00000128 <mfcsr>:
128: 11 30 ce 33 mfcsr \$0x1, cs12, r14
0000012c <bcop>:
12c: 13 30 48 77 bcop \$0x7, \$0x3, \*\+0x90
130: 1c 31 fa 76 bcop \$0x6, \$0xc, \*\-0xbcdfe
134: 01 19
00000136 <excp>:
136: f8 ff excp bpt
138: f5 ff excp svc
0000013a <cinv>:
13a: 10 30 07 00 cinv \[d,i,u\]
0000013e <ram>:
13e: 61 3e ec 21 ram \$0x18, \$0x9, \$0x1, r14, r12
00000142 <rim>:
142: fd 3e 21 ee rim \$0x1f, \$0xf, \$0xe, r2, r1
00000146 <rotb>:
146: f1 fd rotb \$0x7, r1
00000148 <rotw>:
148: d3 b9 rotw \$0xd, r3
0000014a <rotd>:
14a: 08 30 b2 f1 rotd \$0x1b, r2

346
gas/testsuite/gas/crx/misc_insn.s Normal file
View File

@ -0,0 +1,346 @@
# Miscellaneous instructions.
.data
foodata: .word 42
.text
footext:
# Multiply instructions.
.global macsb
macsb:
macsb r0 , r1
.global macub
macub:
macub r2 , r3
.global macqb
macqb:
macqb r4 , r5
.global macsw
macsw:
macsw r6 , r7
.global macuw
macuw:
macuw r8 , r9
.global macqw
macqw:
macqw r10 , r11
.global macsd
macsd:
macsd r12 , r13
.global macud
macud:
macud r14 , r15
.global macqd
macqd:
macqd ra , sp
.global mullsd
mullsd:
mullsd r0 , r2
.global mullud
mullud:
mullud r1 , r3
.global mulsbw
mulsbw:
mulsbw r4 , r6
.global mulubw
mulubw:
mulubw r5 , r7
.global mulswd
mulswd:
mulswd r8 , r10
.global muluwd
muluwd:
muluwd r9 , r11
# Signextend instructions.
.global sextbw
sextbw:
sextbw r12 , ra
.global sextbd
sextbd:
sextbd r13 , sp
.global sextwd
sextwd:
sextwd r14 , r15
.global zextbw
zextbw:
zextbw r5 , r0
.global zextbd
zextbd:
zextbd r10 , r6
.global zextwd
zextwd:
zextwd r7 , r15
# Misc. instructions.
.global getrfid
getrfid:
getrfid r14
.global setrfid
setrfid:
setrfid sp
.global bswap
bswap:
bswap r14 , r2
.global maxsb
maxsb:
maxsb r8 , r3
.global minsb
minsb:
minsb r15 , r14
.global maxub
maxub:
maxub r13 , r12
.global minub
minub:
minub r11 , r10
.global absb
absb:
absb r9 , r8
.global negb
negb:
negb r7 , r6
.global cntl0b
cntl0b:
cntl0b r5 , r4
.global cntl1b
cntl1b:
cntl1b r3 , r2
.global popcntb
popcntb:
popcntb r1 , r0
.global rotlb
rotlb:
rotlb r11 , r4
.global rotrb
rotrb:
rotrb r7 , r2
.global mulqb
mulqb:
mulqb r14 , ra
.global addqb
addqb:
addqb r15 , sp
.global subqb
subqb:
subqb r0 , r10
.global cntlsb
cntlsb:
cntlsb r2 , r12
.global maxsw
maxsw:
maxsw r8 , r3
.global minsw
minsw:
minsw r15 , r14
.global maxuw
maxuw:
maxuw r13 , r12
.global minuw
minuw:
minuw r11 , r10
.global absw
absw:
absw r9 , r8
.global negw
negw:
negw r7 , r6
.global cntl0w
cntl0w:
cntl0w r5 , r4
.global cntl1w
cntl1w:
cntl1w r3 , r2
.global popcntw
popcntw:
popcntw r1 , r0
.global rotlw
rotlw:
rotlw r11 , r4
.global rotrw
rotrw:
rotrw r7 , r2
.global mulqw
mulqw:
mulqw r14 , ra
.global addqw
addqw:
addqw r15 , sp
.global subqw
subqw:
subqw r0 , r10
.global cntlsw
cntlsw:
cntlsw r2 , r12
.global maxsd
maxsd:
maxsd r8 , r3
.global minsd
minsd:
minsd r15 , r14
.global maxud
maxud:
maxud r13 , r12
.global minud
minud:
minud r11 , r10
.global absd
absd:
absd r9 , r8
.global negd
negd:
negd r7 , r6
.global cntl0d
cntl0d:
cntl0d r5 , r4
.global cntl1d
cntl1d:
cntl1d r3 , r2
.global popcntd
popcntd:
popcntd r1 , r0
.global rotld
rotld:
rotld r11 , r4
.global rotrd
rotrd:
rotrd r7 , r2
.global mulqd
mulqd:
mulqd r14 , ra
.global addqd
addqd:
addqd r15 , sp
.global subqd
subqd:
subqd r0 , r10
.global cntlsd
cntlsd:
cntlsd r2 , r12
.global mtpr
mtpr:
mtpr r0 , hi
.global mfpr
mfpr:
mfpr lo , r5
mfpr uhi , r10
.global mtcr
mtcr:
mtcr $0xf, r1, c14
.global mfcr
mfcr:
mfcr $3, c7, r2
.global mtcsr
mtcsr:
mtcsr $0x2, r5, cs1
.global mfcsr
mfcsr:
mfcsr $01, cs12, ra
.global bcop
bcop:
bcop $7, $3, 0x90
bcop $6, $12, -0xbcdfe
.global excp
excp:
excp BPT
excp svc
.global cinv
cinv:
cinv [i,d,u]
.global ram
ram:
ram $24, $9, $1, ra, r12
.global rim
rim:
rim $0x1f, $0xf, $0xe, r2, r1
.global rotb
rotb:
rotb $7, r1
.global rotw
rotw:
rotw $13, r3
.global rotd
rotd:
rotd $27, r2

25
gas/testsuite/gas/crx/no_op_insn.d Normal file
View File

@ -0,0 +1,25 @@
#as:
#objdump: -dr
#name: no_op_insn
.*: +file format .*
Disassembly of section .text:
00000000 <nop>:
0: 02 30 nop
00000002 <retx>:
2: 03 30 retx
00000004 <di>:
4: 04 30 di
00000006 <ei>:
6: 05 30 ei
00000008 <wait>:
8: 06 30 wait
0000000a <eiwait>:
a: 07 30 eiwait

29
gas/testsuite/gas/crx/no_op_insn.s Normal file
View File

@ -0,0 +1,29 @@
# Instruction with no operands.
.data
foodata: .word 42
.text
footext:
.global nop
nop:
nop
.global retx
retx:
retx
.global di
di:
di
.global ei
ei:
ei
.global wait
wait:
wait
.global eiwait
eiwait:
eiwait

43
gas/testsuite/gas/crx/shift_insn.d Normal file
View File

@ -0,0 +1,43 @@
#as:
#objdump: -dr
#name: shift_insn
.*: +file format .*
Disassembly of section .text:
00000000 <sllb>:
0: 71 fc sllb \$0x7, r1
2: 23 4d sllb r2, r3
00000004 <srlb>:
4: d4 fc srlb \$0x5, r4
6: 56 4e srlb r5, r6
00000008 <srab>:
8: 47 fd srab \$0x4, r7
a: 89 4f srab r8, r9
0000000c <sllw>:
c: fa b6 sllw \$0xf, r10
e: bc 5d sllw r11, r12
00000010 <srlw>:
10: ed b7 srlw \$0xe, r13
12: ef 5e srlw r14, r15
00000014 <sraw>:
14: de b8 sraw \$0xd, r14
16: f1 5f sraw r15, r1
00000018 <slld>:
18: f2 f1 slld \$0x1f, r2
1a: 34 6d slld r3, r4
0000001c <srld>:
1c: f5 f3 srld \$0x1f, r5
1e: 67 6e srld r6, r7
00000020 <srad>:
20: 28 f5 srad \$0x12, r8
22: 9a 6f srad r9, r10

51
gas/testsuite/gas/crx/shift_insn.s Normal file
View File

@ -0,0 +1,51 @@
# Shift instructions.
.data
foodata: .word 42
.text
footext:
.global sllb
sllb:
sllb $7 , r1
sllb r2 , r3
.global srlb
srlb:
srlb $0x5 , r4
srlb r5 , r6
.global srab
srab:
srab $04 , r7
srab r8 , r9
.global sllw
sllw:
sllw $15 , r10
sllw r11 , r12
.global srlw
srlw:
srlw $0xe , r13
srlw r14 , r15
.global sraw
sraw:
sraw $015 , ra
sraw sp , r1
.global slld
slld:
slld $31 , r2
slld r3 , r4
.global srld
srld:
srld $0x1f , r5
srld r6 , r7
.global srad
srad:
srad $022 , r8
srad r9 , r10

8
ld/ChangeLog
View File

@ -1,3 +1,11 @@
2004-09-03 Tomer Levi <Tomer.Levi@nsc.com>
* scripttempl/elf32crx.sc: Edit file with comments.
(.init): Add new section.
(.fini): Likewise.
(.ctor): Control the linkage order.
(.dtor): Likewise.
2004-08-27 Nick Clifton <nickc@redhat.com>
* emultempl/pe.em (after_open): Do not assume that either bfd is

139
ld/scripttempl/elf32crx.sc
View File

@ -27,19 +27,105 @@ MEMORY
ram : ORIGIN = 4M, LENGTH = 10M
}
/* Many sections come in three flavours. There is the 'real' section,
like ".data". Then there are the per-procedure or per-variable
sections, generated by -ffunction-sections and -fdata-sections in GCC,
and useful for --gc-sections, which for a variable "foo" might be
".data.foo". Then there are the linkonce sections, for which the linker
eliminates duplicates, which are named like ".gnu.linkonce.d.foo".
The exact correspondences are:
Section Linkonce section
.text .gnu.linkonce.t.foo
.rdata .gnu.linkonce.r.foo
.data .gnu.linkonce.d.foo
.bss .gnu.linkonce.b.foo
.debug_info .gnu.linkonce.wi.foo */
SECTIONS
{
.text : { __TEXT_START = .; *(.text) *(.text.*) *(.gnu.linkonce.t.*) __TEXT_END = .; } > rom
.rdata : { __RDATA_START = .; *(.rdata_4) *(.rdata_2) *(.rdata_1) *(.rdata.*) *(.gnu.linkonce.r.*) __RDATA_END = .; } > rom
.init :
{
__INIT_START = .;
*(.init)
__INIT_END = .;
} > rom
.ctor ALIGN(4) : { __CTOR_LIST = .; *(.ctors) __CTOR_END = .; } > rom
.fini :
{
__FINI_START = .;
*(.fini)
__FINI_END = .;
} > rom
.dtor ALIGN(4) : { __DTOR_LIST = .; *(.dtors) __DTOR_END = .; } > rom
.jcr :
{
*(.jcr)
} > rom
.data : { __DATA_START = .; *(.data_4) *(.data_2) *(.data_1) *(.data) *(.data.*) *(.gnu.linkonce.d.*) __DATA_END = .; } > ram AT > rom
.text :
{
__TEXT_START = .;
*(.text) *(.text.*) *(.gnu.linkonce.t.*)
__TEXT_END = .;
} > rom
.bss (NOLOAD) : { __BSS_START = .; *(.bss_4) *(.bss_2) *(.bss_1) *(.bss) *(COMMON) *(.bss.*) *(.gnu.linkonce.b.*) __BSS_END = .; } > ram
.rdata :
{
__RDATA_START = .;
*(.rdata_4) *(.rdata_2) *(.rdata_1) *(.rdata.*) *(.gnu.linkonce.r.*)
__RDATA_END = .;
} > rom
.ctor ALIGN(4) :
{
__CTOR_START = .;
/* The compiler uses crtbegin.o to find the start
of the constructors, so we make sure it is
first. Because this is a wildcard, it
doesn't matter if the user does not
actually link against crtbegin.o; the
linker won't look for a file to match a
wildcard. The wildcard also means that it
doesn't matter which directory crtbegin.o
is in. */
KEEP (*crtbegin*.o(.ctors))
/* We don't want to include the .ctor section from
the crtend.o file until after the sorted ctors.
The .ctor section from the crtend file contains the
end of ctors marker and it must be last */
KEEP (*(EXCLUDE_FILE (*crtend*.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
__CTOR_END = .;
} > rom
.dtor ALIGN(4) :
{
__DTOR_START = .;
KEEP (*crtbegin*.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend*.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
__DTOR_END = .;
} > rom
.data :
{
__DATA_START = .;
*(.data_4) *(.data_2) *(.data_1) *(.data) *(.data.*) *(.gnu.linkonce.d.*)
__DATA_END = .;
} > ram AT > rom
.bss (NOLOAD) :
{
__BSS_START = .;
*(.bss_4) *(.bss_2) *(.bss_1) *(.bss) *(COMMON) *(.bss.*) *(.gnu.linkonce.b.*)
__BSS_END = .;
} > ram
/* You may change the sizes of the following sections to fit the actual
size your program requires.
@ -47,9 +133,42 @@ SECTIONS
The heap and stack are aligned to the bus width, as a speed optimization
for accessing data located there. */
.heap : { . = ALIGN(4); __HEAP_START = .; . += 0x2000; __HEAP_MAX = .; } > ram
.stack : { . = ALIGN(4); . += 0x6000; __STACK_START = .; } > ram
.istack : { . = ALIGN(4); . += 0x100; __ISTACK_START = .; } > ram
.heap :
{
. = ALIGN(4);
__HEAP_START = .;
. += 0x2000; __HEAP_MAX = .;
} > ram
.stack :
{
. = ALIGN(4);
. += 0x6000;
__STACK_START = .;
} > ram
.istack :
{
. = ALIGN(4);
. += 0x100;
__ISTACK_START = .;
} > ram
.comment 0 : { *(.comment) }
/* DWARF debug sections.
Symbols in the DWARF debugging sections are relative to the beginning
of the section so we begin them at 0. */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
}
__DATA_IMAGE_START = LOADADDR(.data);

38
ld/testsuite/ChangeLog
View File

@ -1,3 +1,41 @@
2004-09-03 Tomer Levi <Tomer.Levi@nsc.com>
* ld-crx: New directory.
* ld-crx/crx.exp: New test script.
* ld-crx/crx.ld: New linker script.
* ld-crx/reloc-abs32.s: New file.
* ld-crx/reloc-abs32.d: Likewise.
* ld-crx/reloc-imm16.s: Likewise.
* ld-crx/reloc-imm16.d: Likewise.
* ld-crx/reloc-imm32.s: Likewise.
* ld-crx/reloc-imm32.d: Likewise.
* ld-crx/reloc-num8.s: Likewise.
* ld-crx/reloc-num8.d: Likewise.
* ld-crx/reloc-num16.s: Likewise.
* ld-crx/reloc-num16.d: Likewise.
* ld-crx/reloc-num32.s: Likewise.
* ld-crx/reloc-num32.d: Likewise.
* ld-crx/reloc-regrel12.s: Likewise.
* ld-crx/reloc-regrel12.d: Likewise.
* ld-crx/reloc-regrel22.s: Likewise.
* ld-crx/reloc-regrel22.d: Likewise.
* ld-crx/reloc-regrel28.s: Likewise.
* ld-crx/reloc-regrel28.d: Likewise.
* ld-crx/reloc-regrel32.s: Likewise.
* ld-crx/reloc-regrel32.d: Likewise.
* ld-crx/reloc-rel4.s: Likewise.
* ld-crx/reloc-rel4.d: Likewise.
* ld-crx/reloc-rel8.s: Likewise.
* ld-crx/reloc-rel8.d: Likewise.
* ld-crx/reloc-rel8-cmp.s: Likewise.
* ld-crx/reloc-rel8-cmp.d: Likewise.
* ld-crx/reloc-rel16.s: Likewise.
* ld-crx/reloc-rel16.d: Likewise.
* ld-crx/reloc-rel24.s: Likewise.
* ld-crx/reloc-rel24.d: Likewise.
* ld-crx/reloc-rel32.s: Likewise.
* ld-crx/reloc-rel32.d: Likewise.
2004-08-21 Hans-Peter Nilsson <hp@axis.com>
* ld-cris/expdyn1.d, ld-cris/expdyn5.d, ld-cris/expdyn6.d,

32
ld/testsuite/ld-crx/crx.exp Normal file
View File

@ -0,0 +1,32 @@
# Expect script for ld-crx tests
# Copyright 2004 Free Software Foundation, Inc.
#
# This file is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
#
# Written by Tomer Levi, Tomer.Levi@nsc.com
#
# Test CRX
if ![istarget crx-*-*] {
return
}
set test_list [lsort [glob -nocomplain $srcdir/$subdir/*.d]]
foreach test $test_list {
# We need to strip the ".d", but can leave the dirname.
verbose [file rootname $test]
run_dump_test [file rootname $test]
}

84
ld/testsuite/ld-crx/crx.ld Normal file
View File

@ -0,0 +1,84 @@
/* 8 bit data address relocations (R_CRX_NUM8). */
d8 = 0x12;
/* 16 bit data address relocations (R_CRX_NUM16). */
d16 = 0x1234;
/* 32 bit data address relocations (R_CRX_NUM32). */
d32 = 0x12345678;
SECTIONS
{
/* 4 bit relocations:
Relative address (R_CRX_REL4) : 0x6 + 2 = 0x8
*/
.text_4 0xa :
{
*(.text_4)
foo4 = (. + 0x6);
}
/* 8 bit relocations:
Relative address (R_CRX_REL8): 0x10 + 2 = 0x12
Relative address (R_CRX_REL8_CMP) : 0x10 + 4 = 0x14
*/
.text_8 0xe0 :
{
*(.text_8)
foo8 = (. + 0x10);
}
/* 12 bit relocations:
Absolute address (R_CRX_REGREL12) : 0x0101 + 0x700 + 4 = 0x805
*/
.text_12 0x0101 :
{
*(.text_12)
foo12 = (. + 0x700);
}
/* 16 bit relocations:
Relative address (R_CRX_REL16) : 0x1000 + 4 = 0x1004
Absolute address (R_CRX_IMM16) : 0x01010 + 0x1000 + 4 = 0x2014
*/
.text_16 0x01010 :
{
*(.text_16)
foo16 = (. + 0x1000);
}
/* 22 bit relocations:
Absolute address (R_CRX_REGREL22) : 0x0201400 + 0x100000 + 6 = 0x301406
*/
.text_22 0x0201400 :
{
*(.text_22)
foo22 = (. + 0x100000);
}
/* 24 bit relocations:
Relative address (R_CRX_REL24) : 0xe00000 + 6 = 0xe00006
*/
.text_24 0x0f01400 :
{
*(.text_24)
foo24 = (. + 0xe00000);
}
/* 28 bit relocations:
Absolute address (R_CRX_REGREL28) : 0x06201400 + 0x3100000 + 6 = 0x9301406
*/
.text_28 0x06201400 :
{
*(.text_28)
foo28 = (. + 0x3100000);
}
/* 32 bit relocations:
Absolute address (R_CRX_ABS32, R_CRX_IMM32) : 0x11014000 + 0x11000000 + 6 = 0x22014006
Relative address (R_CRX_REL32) : 0x11000000 + 6 = 0x11000006
*/
.text_32 0x11014000 :
{
*(.text_32)
foo32 = (. + 0x11000000);
}
}

13
ld/testsuite/ld-crx/reloc-abs32.d Normal file
View File

@ -0,0 +1,13 @@
#source: reloc-abs32.s
#ld: -T $srcdir/$subdir/crx.ld
#objdump: -D
# Test absolute relocation R_CRX_ABS32
.*: file format elf32-crx
Disassembly of section .text_32:
11014000 <_start>:
11014000: 01 33 01 22 loadb 0x22014006, r1
11014004: 06 40

7
ld/testsuite/ld-crx/reloc-abs32.s Normal file
View File

@ -0,0 +1,7 @@
# Test absolute relocation R_CRX_ABS32
.section .text_32,"ax","progbits"
.global _start
_start:
loadb foo32, r1

12
ld/testsuite/ld-crx/reloc-imm16.d Normal file
View File

@ -0,0 +1,12 @@
#source: reloc-imm16.s
#ld: -T $srcdir/$subdir/crx.ld
#objdump: -D
# Test immediate relocation R_CRX_IMM16
.*: file format elf32-crx
Disassembly of section .text_16:
00001010 <_start>:
1010: ee 11 14 20 addw \$0x2014, r14

7
ld/testsuite/ld-crx/reloc-imm16.s Normal file
View File

@ -0,0 +1,7 @@
# Test immediate relocation R_CRX_IMM16
.section .text_16,"ax","progbits"
.global _start
_start:
addw $foo16 , ra

13
ld/testsuite/ld-crx/reloc-imm32.d Normal file
View File

@ -0,0 +1,13 @@
#source: reloc-imm32.s
#ld: -T $srcdir/$subdir/crx.ld
#objdump: -D
# Test immediate relocation R_CRX_IMM32
.*: file format elf32-crx
Disassembly of section .text_32:
11014000 <_start>:
11014000: f6 21 01 22 addd \$0x22014006, r6
11014004: 06 40

7
ld/testsuite/ld-crx/reloc-imm32.s Normal file
View File

@ -0,0 +1,7 @@
# Test immediate relocation R_CRX_IMM32
.section .text_32,"ax","progbits"
.global _start
_start:
addd $foo32, r6

12
ld/testsuite/ld-crx/reloc-num16.d Normal file
View File

@ -0,0 +1,12 @@
#source: reloc-num16.s
#ld: -T $srcdir/$subdir/crx.ld
#objdump: -D
# Test relocation on data R_CRX_NUM16
.*: file format elf32-crx
Disassembly of section .text:
11014000 <_start>:
11014000: 34 12 addcw \$0x3, r4

6
ld/testsuite/ld-crx/reloc-num16.s Normal file
View File

@ -0,0 +1,6 @@
# Test relocation on data R_CRX_NUM16
.text
.global _start
_start:
.word d16

13
ld/testsuite/ld-crx/reloc-num32.d Normal file
View File

@ -0,0 +1,13 @@
#source: reloc-num32.s
#ld: -T $srcdir/$subdir/crx.ld
#objdump: -D
# Test relocation on data R_CRX_NUM32
.*: file format elf32-crx
Disassembly of section .text:
11014000 <_start>:
11014000: 78 56 orw r7, r8
11014002: 34 12 addcw \$0x3, r4

6
ld/testsuite/ld-crx/reloc-num32.s Normal file
View File

@ -0,0 +1,6 @@
# Test relocation on data R_CRX_NUM32
.text
.global _start
_start:
.long d32

12
ld/testsuite/ld-crx/reloc-num8.d Normal file
View File

@ -0,0 +1,12 @@
#source: reloc-num8.s
#ld: -T $srcdir/$subdir/crx.ld
#objdump: -D
# Test relocation on data R_CRX_NUM8
.*: file format elf32-crx
Disassembly of section .text:
11014000 <_start>:
11014000: 12 00 addub \$0x1, r2

6
ld/testsuite/ld-crx/reloc-num8.s Normal file
View File

@ -0,0 +1,6 @@
# Test relocation on data R_CRX_NUM8
.text
.global _start
_start:
.byte d8

12
ld/testsuite/ld-crx/reloc-regrel12.d Normal file
View File

@ -0,0 +1,12 @@
#source: reloc-regrel12.s
#ld: -T $srcdir/$subdir/crx.ld
#objdump: -D
# Test register relative relocation R_CRX_REGREL12
.*: file format elf32-crx
Disassembly of section .text_12:
00000101 <_start>:
101: 85 32 05 78 loadb 0x805\(r7\)\+, r5

6
ld/testsuite/ld-crx/reloc-regrel12.s Normal file
View File

@ -0,0 +1,6 @@
# Test register relative relocation R_CRX_REGREL12
.section .text_12,"ax","progbits"
.global _start
_start:
loadb foo12(r7)+, r5

13
ld/testsuite/ld-crx/reloc-regrel22.d Normal file
View File

@ -0,0 +1,13 @@
#source: reloc-regrel22.s
#ld: -T $srcdir/$subdir/crx.ld
#objdump: -D
# Test register relative relocation R_CRX_REGREL22
.*: file format elf32-crx
Disassembly of section .text_22:
00201400 <_start>:
201400: cd 33 70 9c loadb 0x301406\(r9,r12,2\), r13
201404: 06 14

6
ld/testsuite/ld-crx/reloc-regrel22.s Normal file
View File

@ -0,0 +1,6 @@
# Test register relative relocation R_CRX_REGREL22
.section .text_22,"ax","progbits"
.global _start
_start:
loadb foo22(r9,r12,2), r13

13
ld/testsuite/ld-crx/reloc-regrel28.d Normal file
View File

@ -0,0 +1,13 @@
#source: reloc-regrel28.s
#ld: -T $srcdir/$subdir/crx.ld
#objdump: -D
# Test register relative relocation R_CRX_REGREL28
.*: file format elf32-crx
Disassembly of section .text_28:
06201400 <_start>:
6201400: 7f 3b 30 99 cbitd \$0x1f, 0x9301406\(r9\)
6201404: 06 14

6
ld/testsuite/ld-crx/reloc-regrel28.s Normal file
View File

@ -0,0 +1,6 @@
# Test register relative relocation R_CRX_REGREL28
.section .text_28,"ax","progbits"
.global _start
_start:
cbitd $31, foo28(r9)

13
ld/testsuite/ld-crx/reloc-regrel32.d Normal file
View File

@ -0,0 +1,13 @@
#source: reloc-regrel32.s
#ld: -T $srcdir/$subdir/crx.ld
#objdump: -D
# Test register relative relocation R_CRX_REGREL32
.*: file format elf32-crx
Disassembly of section .text_32:
11014000 <_start>:
11014000: f5 87 01 22 loadb 0x22014006\(r5\), r7
11014004: 06 40

6
ld/testsuite/ld-crx/reloc-regrel32.s Normal file
View File

@ -0,0 +1,6 @@
# Test register relative relocation R_CRX_REGREL32
.section .text_32,"ax","progbits"
.global _start
_start:
loadb foo32(r5), r7

12
ld/testsuite/ld-crx/reloc-rel16.d Normal file
View File

@ -0,0 +1,12 @@
#source: reloc-rel16.s
#ld: -T $srcdir/$subdir/crx.ld
#objdump: -D
# Test pc relative relocation R_CRX_REL16
.*: file format elf32-crx
Disassembly of section .text_16:
00001010 <_start>:
1010: 7e 30 02 08 bal r14, \*\+0x1004

8
ld/testsuite/ld-crx/reloc-rel16.s Normal file
View File

@ -0,0 +1,8 @@
# Test pc relative relocation R_CRX_REL16
.section .text_16,"ax","progbits"
.global _start
.global foo16
_start:
bal ra, foo16
foo16:

13
ld/testsuite/ld-crx/reloc-rel24.d Normal file
View File

@ -0,0 +1,13 @@
#source: reloc-rel24.s
#ld: -T $srcdir/$subdir/crx.ld
#objdump: -D
# Test pc relative relocation R_CRX_REL24
.*: file format elf32-crx
Disassembly of section .text_24:
00f01400 <_start>:
f01400: 81 31 70 20 cmpbeqb r1, r2, \*\+0xe00006
f01404: 03 00

6
ld/testsuite/ld-crx/reloc-rel24.s Normal file
View File

@ -0,0 +1,6 @@
# Test pc relative relocation R_CRX_REL24
.section .text_24,"ax","progbits"
.global _start
_start:
cmpbeqb r1, r2, foo24

13
ld/testsuite/ld-crx/reloc-rel32.d Normal file
View File

@ -0,0 +1,13 @@
#source: reloc-rel32.s
#ld: -T $srcdir/$subdir/crx.ld
#objdump: -D
# Test pc relative relocation R_CRX_REL32
.*: file format elf32-crx
Disassembly of section .text_32:
11014000 <_start>:
11014000: 7f 7e 80 08 br \*\+0x11000006
11014004: 03 00

6
ld/testsuite/ld-crx/reloc-rel32.s Normal file
View File

@ -0,0 +1,6 @@
# Test pc relative relocation R_CRX_REL32
.section .text_32,"ax","progbits"
.global _start
_start:
br foo32

12
ld/testsuite/ld-crx/reloc-rel4.d Normal file
View File

@ -0,0 +1,12 @@
#source: reloc-rel4.s
#ld: -T $srcdir/$subdir/crx.ld
#objdump: -D
# Test pc relative relocation R_CRX_REL4
.*: file format elf32-crx
Disassembly of section .text_4:
0000000a <_start>:
a: 3a b0 beq0b r10, 0x8

8
ld/testsuite/ld-crx/reloc-rel4.s Normal file
View File

@ -0,0 +1,8 @@
# Test pc relative relocation R_CRX_REL4
.section .text_4,"ax","progbits"
.global _start
.global foo4
_start:
beq0b r10 , foo4
foo4:

12
ld/testsuite/ld-crx/reloc-rel8-cmp.d Normal file
View File

@ -0,0 +1,12 @@
#source: reloc-rel8-cmp.s
#ld: -T $srcdir/$subdir/crx.ld
#objdump: -D
# Test pc relative relocation R_CRX_REL8_CMP
.*: file format elf32-crx
Disassembly of section .text_8:
000000e0 <_start>:
e0: 81 30 0a 20 cmpbeqb r1, r2, \*\+0x14

8
ld/testsuite/ld-crx/reloc-rel8-cmp.s Normal file
View File

@ -0,0 +1,8 @@
# Test pc relative relocation R_CRX_REL8_CMP
.section .text_8,"ax","progbits"
.global _start
.global foo8
_start:
cmpbeqb r1, r2, foo8
foo8:

12
ld/testsuite/ld-crx/reloc-rel8.d Normal file
View File

@ -0,0 +1,12 @@
#source: reloc-rel8.s
#ld: -T $srcdir/$subdir/crx.ld
#objdump: -D
# Test pc relative relocation R_CRX_REL8
.*: file format elf32-crx
Disassembly of section .text_8:
000000e0 <_start>:
e0: 09 70 beq \*\+0x12

8
ld/testsuite/ld-crx/reloc-rel8.s Normal file
View File

@ -0,0 +1,8 @@
# Test pc relative relocation R_CRX_REL8
.section .text_8,"ax","progbits"
.global _start
.global foo8
_start:
beq foo8
foo8:

5
opcodes/ChangeLog
View File

@ -1,3 +1,8 @@
2004-09-03 Tomer Levi <Tomer.Levi@nsc.com>
* opc-crx.c: Rename 'popma' to 'popa', remove 'pushma'.
Fix parameter to 'm[t|f]csr' insns.
2004-08-30 Nathanael Nerode <neroden@gcc.gnu.org>
* configure.in: Autoupdate to autoconf 2.59.

11
opcodes/crx-opc.c
View File

@ -472,13 +472,12 @@ const inst crx_instruction[] =
REGLIST_INST ("popret", 0x326),
REG1_INST ("popret", 0xFFD),
REGLIST_INST ("loadm", 0x324),
REGLIST_INST ("loadm", 0x324),
REGLIST_INST ("loadma", 0x325),
REGLIST_INST ("popma", 0x325),
REGLIST_INST ("popa", 0x325),
REGLIST_INST ("storm", 0x344),
REGLIST_INST ("storm", 0x344),
REGLIST_INST ("storma", 0x345),
REGLIST_INST ("pushma", 0x345),
/* Create a branch instruction. */
#define BR_INST(NAME, OPC1, OPC2, INS_TYPE) \
@ -512,9 +511,9 @@ const inst crx_instruction[] =
/* opc12 c4 opc8 copreg r */
{"mfcr", 2, 0x301031, 8, COP_REG_INS | FMT_2, {{i4,16}, {copregr,4}, {regr,0}}},
/* opc12 c4 opc8 r copsreg */
{"mtcsr", 2, 0x301032, 8, COP_REG_INS | FMT_2, {{i4,16}, {regr,4}, {copregr,0}}},
{"mtcsr", 2, 0x301032, 8, COP_REG_INS | FMT_2, {{i4,16}, {regr,4}, {copsregr,0}}},
/* opc12 c4 opc8 copsreg r */
{"mfcsr", 2, 0x301033, 8, COP_REG_INS | FMT_2, {{i4,16}, {copregr,4}, {regr,0}}},
{"mfcsr", 2, 0x301033, 8, COP_REG_INS | FMT_2, {{i4,16}, {copsregr,4}, {regr,0}}},
/* CO-processor extensions */
/* opc12 c4 opc4 i4 disps9 */