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Add load-link, store-conditional paired EVA instructions
Add paired load-link and store-conditional instructions to the
EVA ASE for MIPS32R6[1]. These instructions are optional within
the EVA ASE. Their presence is indicated by the XNP bit in the
Config5 register.
[1] "MIPS Architecture for Programmers Volume II-A: The MIPS32
Instruction Set Manual", Imagination Technologies Ltd., Document
Number: MD00086, Revision 6.06, December 15, 2016, Section 3.2
"Alphabetical List of Instructions", pp. 230-231, pp. 357-360.
gas/
* config/tc-mips.c (mips_set_ase): Handle ASE_EVA_R6.
(macro) <M_LLWPE_AB, M_SCWPE_AB>: New cases.
(mips_after_parse_args): Translate EVA to EVA_R6.
* testsuite/gas/mips/ase-errors-1.s: Add new instructions.
* testsuite/gas/mips/eva.s: Likewise.
* testsuite/gas/mips/ase-errors-1.l: Check errors for
new instructions.
* testsuite/gas/mips/mipsr6@eva.d: Check new test cases.
include/
* opcode/mips.h (ASE_EVA_R6): New macro.
(M_LLWPE_AB, M_SCWPE_AB): New enum values.
opcodes/
* mips-dis.c (mips_calculate_combination_ases): Add ISA
argument and set ASE_EVA_R6 appropriately.
(set_default_mips_dis_options): Pass ISA to above.
(parse_mips_dis_option): Likewise.
* mips-opc.c (EVAR6): New macro.
(mips_builtin_opcodes): Add llwpe, scwpe.
Derived from patch authored by Andrew Bennett <andrew.bennett@imgtec.com>
This commit is contained in:
Faraz Shahbazker
parent
be0d3bbbcd
commit
41cee0897b
@ -1,3 +1,15 @@
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2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
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Faraz Shahbazker <fshahbazker@wavecomp.com>
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* config/tc-mips.c (mips_set_ase): Handle ASE_EVA_R6.
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(macro) <M_LLWPE_AB, M_SCWPE_AB>: New cases.
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(mips_after_parse_args): Translate EVA to EVA_R6.
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* testsuite/gas/mips/ase-errors-1.s: Add new instructions.
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* testsuite/gas/mips/eva.s: Likewise.
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* testsuite/gas/mips/ase-errors-1.l: Check errors for
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new instructions.
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* testsuite/gas/mips/mipsr6@eva.d: Check new test cases.
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2019-05-06 Alan Modra <amodra@gmail.com>
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* symbols.c (symbol_relc_make_sym): Do not access sym->sy_value
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@ -2227,7 +2227,7 @@ mips_set_ase (const struct mips_ase *ase, struct mips_set_options *opts,
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/* Clear combination ASE flags, which need to be recalculated based on
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updated regular ASE settings. */
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opts->ase &= ~(ASE_MIPS16E2_MT | ASE_XPA_VIRT);
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opts->ase &= ~(ASE_MIPS16E2_MT | ASE_XPA_VIRT | ASE_EVA_R6);
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if (enabled_p)
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opts->ase |= ase->flags;
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@ -2246,6 +2246,15 @@ mips_set_ase (const struct mips_ase *ase, struct mips_set_options *opts,
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mask |= ASE_MIPS16E2_MT;
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}
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/* The EVA Extension has instructions which are only valid when the R6 ISA
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is enabled. This sets the ASE_EVA_R6 flag when both EVA and R6 ISA are
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present. */
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if (((opts->ase & ASE_EVA) != 0) && ISA_IS_R6 (opts->isa))
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{
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opts->ase |= ASE_EVA_R6;
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mask |= ASE_EVA_R6;
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}
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return mask;
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}
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@ -12017,6 +12026,7 @@ macro (struct mips_cl_insn *ip, char *str)
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goto ld;
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case M_LLDP_AB:
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case M_LLWP_AB:
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case M_LLWPE_AB:
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s = ip->insn_mo->name;
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fmt = "t,d,s";
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ll_sc_paired = 1;
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@ -12125,6 +12135,7 @@ macro (struct mips_cl_insn *ip, char *str)
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goto ld_st;
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case M_SCDP_AB:
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case M_SCWP_AB:
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case M_SCWPE_AB:
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s = ip->insn_mo->name;
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fmt = "t,d,s";
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ll_sc_paired = 1;
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@ -15246,6 +15257,12 @@ mips_after_parse_args (void)
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file_mips_opts.isa = arch_info->isa;
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file_mips_opts.init_ase = arch_info->ase;
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/* The EVA Extension has instructions which are only valid when the R6 ISA
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is enabled. This sets the ASE_EVA_R6 flag when both EVA and R6 ISA are
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present. */
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if (((file_mips_opts.ase & ASE_EVA) != 0) && ISA_IS_R6 (file_mips_opts.isa))
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file_mips_opts.ase |= ASE_EVA_R6;
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/* Set up initial mips_opts state. */
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mips_opts = file_mips_opts;
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@ -48,3 +48,7 @@
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.*:117: Warning: the `ginv' extension requires MIPS32 revision 6 or greater
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.*:120: Error: opcode not supported.* `ginvi \$a0'
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# ----------------------------------------------------------------------------
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.*:127: Error: opcode not supported .* `llwpe \$2,\$3,\$4'
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.*:128: Error: opcode not supported .* `scwpe \$2,\$3,\$4'
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.*:131: Error: opcode not supported .* `llwpe \$2,\$3,\$4'
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.*:132: Error: opcode not supported .* `scwpe \$2,\$3,\$4'
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@ -119,6 +119,18 @@
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.set noginv
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ginvi $a0 # ERROR: ginv not enabled
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.set mips32r6
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.set eva
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llwpe $2, $3, $4 # OK
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scwpe $2, $3, $4 # OK
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.set noeva
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llwpe $2, $3, $4 # ERROR: eva not enabled
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scwpe $2, $3, $4 # ERROR: eva not enabled
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.set mips32r5
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.set eva
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llwpe $2, $3, $4 # ERROR: only avaialable on R6
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scwpe $2, $3, $4 # ERROR: only avaialable on R6
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# There should be no errors after this.
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.set fp=32
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.set mips1
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@ -615,3 +615,16 @@ test_eva:
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prefe 11,($12)
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prefe 13,MYDATA
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prefe 5,%lo(foo)($6)
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.ifdef r6
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llwpe $2, $3, 0x1234
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llwpe $2, $0, 0xabcd($0)
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llwpe $0, $3, %lo(sync_mem)
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llwpe $2, $2, 0xffffffff01234567($0)
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llwpe $0, $0, sync_mem
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scwpe $2, $3, 0x1234
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scwpe $2, $0, 0xabcd($0)
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scwpe $0, $3, %lo(sync_mem)
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scwpe $2, $2, 0xffffffff01234567($0)
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scwpe $0, $0, sync_mem
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.endif
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@ -949,4 +949,36 @@ Disassembly of section \.text:
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[ 0-9a-f]+: 24c10000 addiu \$1,\$6,0
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[ 0-9a-f]+: R_MIPS_LO16 foo
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[ 0-9a-f]+: 7c250023 prefe 0x5,0\(\$1\)
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[ 0-9a-f]+: 24021234 li \$2,4660
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[ 0-9a-f]+: 7c42186e llwpe \$2,\$3,\$2
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[ 0-9a-f]+: 3c020001 lui \$2,0x1
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[ 0-9a-f]+: 2442abcd addiu \$2,\$2,-21555
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[ 0-9a-f]+: 7c42006e llwpe \$2,\$0,\$2
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[ 0-9a-f]+: 24030000 li \$3,0
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[0-9a-f]+: R_MIPS_LO16 sync_mem
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[ 0-9a-f]+: 7c60186e llwpe \$0,\$3,\$3
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[ 0-9a-f]+: 3c020123 lui \$2,0x123
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[ 0-9a-f]+: 24424567 addiu \$2,\$2,17767
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[ 0-9a-f]+: 7c42106e llwpe \$2,\$2,\$2
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[ 0-9a-f]+: 3c010000 lui \$1,0x0
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[0-9a-f]+: R_MIPS_HI16 sync_mem
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[ 0-9a-f]+: 24210000 addiu \$1,\$1,0
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[0-9a-f]+: R_MIPS_LO16 sync_mem
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[ 0-9a-f]+: 7c20006e llwpe \$0,\$0,\$1
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[ 0-9a-f]+: 24011234 li \$1,4660
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[ 0-9a-f]+: 7c22185e scwpe \$2,\$3,\$1
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[ 0-9a-f]+: 3c010001 lui \$1,0x1
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[ 0-9a-f]+: 2421abcd addiu \$1,\$1,-21555
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[ 0-9a-f]+: 7c22005e scwpe \$2,\$0,\$1
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[ 0-9a-f]+: 24010000 li \$1,0
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[0-9a-f]+: R_MIPS_LO16 sync_mem
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[ 0-9a-f]+: 7c20185e scwpe \$0,\$3,\$1
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[ 0-9a-f]+: 3c010123 lui \$1,0x123
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[ 0-9a-f]+: 24214567 addiu \$1,\$1,17767
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[ 0-9a-f]+: 7c22105e scwpe \$2,\$2,\$1
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[ 0-9a-f]+: 3c010000 lui \$1,0x0
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[0-9a-f]+: R_MIPS_HI16 sync_mem
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[ 0-9a-f]+: 24210000 addiu \$1,\$1,0
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[0-9a-f]+: R_MIPS_LO16 sync_mem
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[ 0-9a-f]+: 7c20005e scwpe \$0,\$0,\$1
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#pass
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@ -1,3 +1,9 @@
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2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
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Faraz Shahbazker <fshahbazker@wavecomp.com>
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* opcode/mips.h (ASE_EVA_R6): New macro.
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(M_LLWPE_AB, M_SCWPE_AB): New enum values.
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2019-05-01 Sudakshina Das <sudi.das@arm.com>
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* opcode/aarch64.h (AARCH64_FEATURE_TME): New.
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@ -1308,6 +1308,9 @@ static const unsigned int mips_isa_table[] = {
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#define ASE_LOONGSON_EXT 0x00800000
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/* Loongson EXTensions R2 (EXT2) instructions. */
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#define ASE_LOONGSON_EXT2 0x01000000
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/* The Enhanced VA Scheme (EVA) extension has instructions which are
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only valid for the R6 ISA. */
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#define ASE_EVA_R6 0x02000000
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/* MIPS ISA defines, use instead of hardcoding ISA level. */
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@ -1631,6 +1634,7 @@ enum
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M_LLDP_AB,
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M_LLE_AB,
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M_LLWP_AB,
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M_LLWPE_AB,
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M_LQ_AB,
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M_LW_AB,
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M_LWE_AB,
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@ -1684,6 +1688,7 @@ enum
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M_SCDP_AB,
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M_SCE_AB,
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M_SCWP_AB,
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M_SCWPE_AB,
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M_SD_AB,
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M_SDC1_AB,
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M_SDC2_AB,
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@ -1,3 +1,13 @@
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2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
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Faraz Shahbazker <fshahbazker@wavecomp.com>
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* mips-dis.c (mips_calculate_combination_ases): Add ISA
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argument and set ASE_EVA_R6 appropriately.
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(set_default_mips_dis_options): Pass ISA to above.
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(parse_mips_dis_option): Likewise.
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* mips-opc.c (EVAR6): New macro.
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(mips_builtin_opcodes): Add llwpe, scwpe.
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2019-05-01 Sudakshina Das <sudi.das@arm.com>
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* aarch64-asm-2.c: Regenerated.
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@ -829,7 +829,7 @@ mips_convert_abiflags_ases (unsigned long afl_ases)
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/* Calculate combination ASE flags from regular ASE flags. */
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static unsigned long
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mips_calculate_combination_ases (unsigned long opcode_ases)
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mips_calculate_combination_ases (int opcode_isa, unsigned long opcode_ases)
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{
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unsigned long combination_ases = 0;
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@ -837,6 +837,10 @@ mips_calculate_combination_ases (unsigned long opcode_ases)
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combination_ases |= ASE_XPA_VIRT;
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if ((opcode_ases & (ASE_MIPS16E2 | ASE_MT)) == (ASE_MIPS16E2 | ASE_MT))
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combination_ases |= ASE_MIPS16E2_MT;
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if ((opcode_ases & ASE_EVA)
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&& ((opcode_isa & INSN_ISA_MASK) == ISA_MIPS64R6
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|| (opcode_isa & INSN_ISA_MASK) == ISA_MIPS32R6))
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combination_ases |= ASE_EVA_R6;
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return combination_ases;
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}
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@ -909,7 +913,7 @@ set_default_mips_dis_options (struct disassemble_info *info)
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mips_ase |= ASE_MDMX;
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}
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#endif
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mips_ase |= mips_calculate_combination_ases (mips_ase);
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mips_ase |= mips_calculate_combination_ases (mips_isa, mips_ase);
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}
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/* Parse an ASE disassembler option and set the corresponding global
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@ -997,7 +1001,7 @@ parse_mips_dis_option (const char *option, unsigned int len)
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if (parse_mips_ase_option (option))
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{
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mips_ase |= mips_calculate_combination_ases (mips_ase);
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mips_ase |= mips_calculate_combination_ases (mips_isa, mips_ase);
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return;
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}
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@ -392,6 +392,7 @@ decode_mips_operand (const char *p)
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/* MIPS Enhanced VA Scheme. */
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#define EVA ASE_EVA
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#define EVAR6 ASE_EVA_R6
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/* TLB invalidate instruction support. */
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#define TLBINV ASE_EVA
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@ -2638,6 +2639,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
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{"lhe", "t,A(b)", 0, (int) M_LHE_AB, INSN_MACRO, 0, 0, EVA, 0 },
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{"lle", "t,+j(b)", 0x7c00002e, 0xfc00007f, WR_1|RD_3|LM, 0, 0, EVA, 0 },
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{"lle", "t,A(b)", 0, (int) M_LLE_AB, INSN_MACRO, 0, 0, EVA, 0 },
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{"llwpe", "t,d,s", 0x7c00006e, 0xfc0007ff, WR_1|WR_2|RD_3|LM, 0, 0, EVAR6, 0 },
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{"llwpe", "t,d,A(b)", 0, (int) M_LLWPE_AB, INSN_MACRO, 0, 0, EVAR6, 0 },
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{"lwe", "t,+j(b)", 0x7c00002f, 0xfc00007f, WR_1|RD_3|LM, 0, 0, EVA, 0 },
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{"lwe", "t,A(b)", 0, (int) M_LWE_AB, INSN_MACRO, 0, 0, EVA, 0 },
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{"lwle", "t,+j(b)", 0x7c000019, 0xfc00007f, WR_1|RD_3|LM, 0, 0, EVA, I37 },
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@ -2648,6 +2651,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
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{"sbe", "t,A(b)", 0, (int) M_SBE_AB, INSN_MACRO, 0, 0, EVA, 0 },
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{"sce", "t,+j(b)", 0x7c00001e, 0xfc00007f, MOD_1|RD_3|SM, 0, 0, EVA, 0 },
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{"sce", "t,A(b)", 0, (int) M_SCE_AB, INSN_MACRO, 0, 0, EVA, 0 },
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{"scwpe", "t,d,s", 0x7c00005e, 0xfc0007ff, MOD_1|RD_2|RD_3|SM, 0, 0, EVAR6, 0 },
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{"scwpe", "t,d,A(b)", 0, (int) M_SCWPE_AB, INSN_MACRO, 0, 0, EVAR6, 0 },
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{"she", "t,+j(b)", 0x7c00001d, 0xfc00007f, RD_1|RD_3|SM, 0, 0, EVA, 0 },
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{"she", "t,A(b)", 0, (int) M_SHE_AB, INSN_MACRO, 0, 0, EVA, 0 },
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{"swe", "t,+j(b)", 0x7c00001f, 0xfc00007f, RD_1|RD_3|SM, 0, 0, EVA, 0 },
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