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x86: re-do "shorthand" handling
Now that the opcode table gets preprocessed, undo parts of commit
dc821c5f9a ("x86: replace Reg8, Reg16, Reg32, and Reg64"): Have the
preprocessor handle the expansion there, while making the expansions
explicit in i386-gen and the register table.
This commit is contained in:
Jan Beulich
parent
a2cebd03fa
commit
3cc17af589
@ -1,3 +1,15 @@
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2019-10-30 Jan Beulich <jbeulich@suse.com>
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* i386-gen.c (operand_type_shorthands): Delete.
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(operand_type_init): Expand previous shorthands.
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(set_bitfield_from_shorthand): Rename back to ...
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(set_bitfield_from_cpu_flag_init): ... this. Drop processing
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of operand_type_init[].
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(set_bitfield): Adjust call to the above function.
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* i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
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RegXMM, RegYMM, RegZMM): Define.
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* i386-reg.tbl: Expand prior shorthands.
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2019-10-30 Jan Beulich <jbeulich@suse.com>
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* i386-gen.c (output_i386_opcode): Change order of fields
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@ -379,31 +379,18 @@ static initializer cpu_flag_init[] =
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"CpuAVX512_VP2INTERSECT" },
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};
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static const initializer operand_type_shorthands[] =
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{
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{ "Reg8", "Reg|Byte" },
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{ "Reg16", "Reg|Word" },
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{ "Reg32", "Reg|Dword" },
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{ "Reg64", "Reg|Qword" },
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{ "FloatAcc", "Acc|Tbyte" },
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{ "FloatReg", "Reg|Tbyte" },
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{ "RegXMM", "RegSIMD|Xmmword" },
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{ "RegYMM", "RegSIMD|Ymmword" },
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{ "RegZMM", "RegSIMD|Zmmword" },
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};
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static initializer operand_type_init[] =
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{
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{ "OPERAND_TYPE_NONE",
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"0" },
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{ "OPERAND_TYPE_REG8",
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"Reg8" },
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"Reg|Byte" },
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{ "OPERAND_TYPE_REG16",
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"Reg16" },
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"Reg|Word" },
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{ "OPERAND_TYPE_REG32",
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"Reg32" },
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"Reg|Dword" },
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{ "OPERAND_TYPE_REG64",
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"Reg64" },
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"Reg|Qword" },
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{ "OPERAND_TYPE_IMM1",
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"Imm1" },
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{ "OPERAND_TYPE_IMM8",
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@ -441,9 +428,9 @@ static initializer operand_type_init[] =
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{ "OPERAND_TYPE_DEBUG",
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"Debug" },
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{ "OPERAND_TYPE_FLOATREG",
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"FloatReg" },
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"Reg|Tbyte" },
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{ "OPERAND_TYPE_FLOATACC",
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"FloatAcc" },
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"Acc|Tbyte" },
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{ "OPERAND_TYPE_SREG",
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"SReg" },
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{ "OPERAND_TYPE_JUMPABSOLUTE",
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@ -451,11 +438,11 @@ static initializer operand_type_init[] =
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{ "OPERAND_TYPE_REGMMX",
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"RegMMX" },
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{ "OPERAND_TYPE_REGXMM",
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"RegXMM" },
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"RegSIMD|Xmmword" },
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{ "OPERAND_TYPE_REGYMM",
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"RegYMM" },
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"RegSIMD|Ymmword" },
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{ "OPERAND_TYPE_REGZMM",
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"RegZMM" },
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"RegSIMD|Zmmword" },
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{ "OPERAND_TYPE_REGMASK",
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"RegMask" },
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{ "OPERAND_TYPE_ESSEG",
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@ -830,8 +817,8 @@ next_field (char *str, char sep, char **next, char *last)
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static void set_bitfield (char *, bitfield *, int, unsigned int, int);
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static int
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set_bitfield_from_shorthand (char *f, bitfield *array, unsigned int size,
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int lineno)
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set_bitfield_from_cpu_flag_init (char *f, bitfield *array, unsigned int size,
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int lineno)
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{
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char *str, *next, *last;
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unsigned int i;
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@ -852,22 +839,6 @@ set_bitfield_from_shorthand (char *f, bitfield *array, unsigned int size,
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return 0;
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}
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for (i = 0; i < ARRAY_SIZE (operand_type_shorthands); i++)
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if (strcmp (operand_type_shorthands[i].name, f) == 0)
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{
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/* Turn on selective bits. */
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char *init = xstrdup (operand_type_shorthands[i].init);
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last = init + strlen (init);
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for (next = init; next && next < last; )
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{
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str = next_field (next, '|', &next, last);
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if (str)
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set_bitfield (str, array, 1, size, lineno);
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}
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free (init);
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return 0;
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}
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return -1;
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}
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@ -918,8 +889,8 @@ set_bitfield (char *f, bitfield *array, int value,
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}
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}
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/* Handle shorthands. */
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if (value == 1 && !set_bitfield_from_shorthand (f, array, size, lineno))
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/* Handle CPU_XXX_FLAGS. */
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if (value == 1 && !set_bitfield_from_cpu_flag_init (f, array, size, lineno))
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return;
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if (lineno != -1)
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@ -22,6 +22,18 @@
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#include "i386-opc.h"
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#undef None
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#define Reg8 Reg|Byte
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#define Reg16 Reg|Word
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#define Reg32 Reg|Dword
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#define Reg64 Reg|Qword
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#define FloatAcc Acc|Tbyte
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#define FloatReg Reg|Tbyte
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#define RegXMM RegSIMD|Xmmword
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#define RegYMM RegSIMD|Ymmword
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#define RegZMM RegSIMD|Zmmword
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#define Size16 Size=SIZE16
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#define Size32 Size=SIZE32
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#define Size64 Size=SIZE64
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@ -19,82 +19,82 @@
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// 02110-1301, USA.
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// Make %st first as we test for it.
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st, FloatReg|Acc, 0, 0, 11, 33
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st, Reg|Acc|Tbyte, 0, 0, 11, 33
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// 8 bit regs
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al, Reg8|Acc, 0, 0, Dw2Inval, Dw2Inval
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cl, Reg8|ShiftCount, 0, 1, Dw2Inval, Dw2Inval
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dl, Reg8, 0, 2, Dw2Inval, Dw2Inval
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bl, Reg8, 0, 3, Dw2Inval, Dw2Inval
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ah, Reg8, 0, 4, Dw2Inval, Dw2Inval
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ch, Reg8, 0, 5, Dw2Inval, Dw2Inval
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dh, Reg8, 0, 6, Dw2Inval, Dw2Inval
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bh, Reg8, 0, 7, Dw2Inval, Dw2Inval
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axl, Reg8, RegRex64, 0, Dw2Inval, Dw2Inval
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cxl, Reg8, RegRex64, 1, Dw2Inval, Dw2Inval
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dxl, Reg8, RegRex64, 2, Dw2Inval, Dw2Inval
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bxl, Reg8, RegRex64, 3, Dw2Inval, Dw2Inval
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spl, Reg8, RegRex64, 4, Dw2Inval, Dw2Inval
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bpl, Reg8, RegRex64, 5, Dw2Inval, Dw2Inval
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sil, Reg8, RegRex64, 6, Dw2Inval, Dw2Inval
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dil, Reg8, RegRex64, 7, Dw2Inval, Dw2Inval
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r8b, Reg8, RegRex|RegRex64, 0, Dw2Inval, Dw2Inval
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r9b, Reg8, RegRex|RegRex64, 1, Dw2Inval, Dw2Inval
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r10b, Reg8, RegRex|RegRex64, 2, Dw2Inval, Dw2Inval
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r11b, Reg8, RegRex|RegRex64, 3, Dw2Inval, Dw2Inval
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r12b, Reg8, RegRex|RegRex64, 4, Dw2Inval, Dw2Inval
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r13b, Reg8, RegRex|RegRex64, 5, Dw2Inval, Dw2Inval
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r14b, Reg8, RegRex|RegRex64, 6, Dw2Inval, Dw2Inval
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r15b, Reg8, RegRex|RegRex64, 7, Dw2Inval, Dw2Inval
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al, Reg|Acc|Byte, 0, 0, Dw2Inval, Dw2Inval
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cl, Reg|Byte|ShiftCount, 0, 1, Dw2Inval, Dw2Inval
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dl, Reg|Byte, 0, 2, Dw2Inval, Dw2Inval
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bl, Reg|Byte, 0, 3, Dw2Inval, Dw2Inval
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ah, Reg|Byte, 0, 4, Dw2Inval, Dw2Inval
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ch, Reg|Byte, 0, 5, Dw2Inval, Dw2Inval
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dh, Reg|Byte, 0, 6, Dw2Inval, Dw2Inval
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bh, Reg|Byte, 0, 7, Dw2Inval, Dw2Inval
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axl, Reg|Byte, RegRex64, 0, Dw2Inval, Dw2Inval
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cxl, Reg|Byte, RegRex64, 1, Dw2Inval, Dw2Inval
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dxl, Reg|Byte, RegRex64, 2, Dw2Inval, Dw2Inval
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bxl, Reg|Byte, RegRex64, 3, Dw2Inval, Dw2Inval
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spl, Reg|Byte, RegRex64, 4, Dw2Inval, Dw2Inval
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bpl, Reg|Byte, RegRex64, 5, Dw2Inval, Dw2Inval
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sil, Reg|Byte, RegRex64, 6, Dw2Inval, Dw2Inval
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dil, Reg|Byte, RegRex64, 7, Dw2Inval, Dw2Inval
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r8b, Reg|Byte, RegRex|RegRex64, 0, Dw2Inval, Dw2Inval
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r9b, Reg|Byte, RegRex|RegRex64, 1, Dw2Inval, Dw2Inval
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r10b, Reg|Byte, RegRex|RegRex64, 2, Dw2Inval, Dw2Inval
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r11b, Reg|Byte, RegRex|RegRex64, 3, Dw2Inval, Dw2Inval
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r12b, Reg|Byte, RegRex|RegRex64, 4, Dw2Inval, Dw2Inval
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r13b, Reg|Byte, RegRex|RegRex64, 5, Dw2Inval, Dw2Inval
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r14b, Reg|Byte, RegRex|RegRex64, 6, Dw2Inval, Dw2Inval
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r15b, Reg|Byte, RegRex|RegRex64, 7, Dw2Inval, Dw2Inval
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// 16 bit regs
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ax, Reg16|Acc, 0, 0, Dw2Inval, Dw2Inval
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cx, Reg16, 0, 1, Dw2Inval, Dw2Inval
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dx, Reg16|InOutPortReg, 0, 2, Dw2Inval, Dw2Inval
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bx, Reg16|BaseIndex, 0, 3, Dw2Inval, Dw2Inval
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sp, Reg16, 0, 4, Dw2Inval, Dw2Inval
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bp, Reg16|BaseIndex, 0, 5, Dw2Inval, Dw2Inval
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si, Reg16|BaseIndex, 0, 6, Dw2Inval, Dw2Inval
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di, Reg16|BaseIndex, 0, 7, Dw2Inval, Dw2Inval
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r8w, Reg16, RegRex, 0, Dw2Inval, Dw2Inval
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r9w, Reg16, RegRex, 1, Dw2Inval, Dw2Inval
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r10w, Reg16, RegRex, 2, Dw2Inval, Dw2Inval
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r11w, Reg16, RegRex, 3, Dw2Inval, Dw2Inval
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r12w, Reg16, RegRex, 4, Dw2Inval, Dw2Inval
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r13w, Reg16, RegRex, 5, Dw2Inval, Dw2Inval
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r14w, Reg16, RegRex, 6, Dw2Inval, Dw2Inval
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r15w, Reg16, RegRex, 7, Dw2Inval, Dw2Inval
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ax, Reg|Acc|Word, 0, 0, Dw2Inval, Dw2Inval
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cx, Reg|Word, 0, 1, Dw2Inval, Dw2Inval
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dx, Reg|Word|InOutPortReg, 0, 2, Dw2Inval, Dw2Inval
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bx, Reg|Word|BaseIndex, 0, 3, Dw2Inval, Dw2Inval
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sp, Reg|Word, 0, 4, Dw2Inval, Dw2Inval
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bp, Reg|Word|BaseIndex, 0, 5, Dw2Inval, Dw2Inval
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si, Reg|Word|BaseIndex, 0, 6, Dw2Inval, Dw2Inval
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di, Reg|Word|BaseIndex, 0, 7, Dw2Inval, Dw2Inval
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r8w, Reg|Word, RegRex, 0, Dw2Inval, Dw2Inval
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r9w, Reg|Word, RegRex, 1, Dw2Inval, Dw2Inval
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r10w, Reg|Word, RegRex, 2, Dw2Inval, Dw2Inval
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r11w, Reg|Word, RegRex, 3, Dw2Inval, Dw2Inval
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r12w, Reg|Word, RegRex, 4, Dw2Inval, Dw2Inval
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r13w, Reg|Word, RegRex, 5, Dw2Inval, Dw2Inval
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r14w, Reg|Word, RegRex, 6, Dw2Inval, Dw2Inval
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r15w, Reg|Word, RegRex, 7, Dw2Inval, Dw2Inval
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// 32 bit regs
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eax, Reg32|BaseIndex|Acc, 0, 0, 0, Dw2Inval
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ecx, Reg32|BaseIndex, 0, 1, 1, Dw2Inval
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edx, Reg32|BaseIndex, 0, 2, 2, Dw2Inval
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ebx, Reg32|BaseIndex, 0, 3, 3, Dw2Inval
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esp, Reg32, 0, 4, 4, Dw2Inval
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ebp, Reg32|BaseIndex, 0, 5, 5, Dw2Inval
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esi, Reg32|BaseIndex, 0, 6, 6, Dw2Inval
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edi, Reg32|BaseIndex, 0, 7, 7, Dw2Inval
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r8d, Reg32|BaseIndex, RegRex, 0, Dw2Inval, Dw2Inval
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r9d, Reg32|BaseIndex, RegRex, 1, Dw2Inval, Dw2Inval
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r10d, Reg32|BaseIndex, RegRex, 2, Dw2Inval, Dw2Inval
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r11d, Reg32|BaseIndex, RegRex, 3, Dw2Inval, Dw2Inval
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r12d, Reg32|BaseIndex, RegRex, 4, Dw2Inval, Dw2Inval
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r13d, Reg32|BaseIndex, RegRex, 5, Dw2Inval, Dw2Inval
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r14d, Reg32|BaseIndex, RegRex, 6, Dw2Inval, Dw2Inval
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r15d, Reg32|BaseIndex, RegRex, 7, Dw2Inval, Dw2Inval
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rax, Reg64|BaseIndex|Acc, 0, 0, Dw2Inval, 0
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rcx, Reg64|BaseIndex, 0, 1, Dw2Inval, 2
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rdx, Reg64|BaseIndex, 0, 2, Dw2Inval, 1
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rbx, Reg64|BaseIndex, 0, 3, Dw2Inval, 3
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rsp, Reg64, 0, 4, Dw2Inval, 7
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rbp, Reg64|BaseIndex, 0, 5, Dw2Inval, 6
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rsi, Reg64|BaseIndex, 0, 6, Dw2Inval, 4
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rdi, Reg64|BaseIndex, 0, 7, Dw2Inval, 5
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r8, Reg64|BaseIndex, RegRex, 0, Dw2Inval, 8
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r9, Reg64|BaseIndex, RegRex, 1, Dw2Inval, 9
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r10, Reg64|BaseIndex, RegRex, 2, Dw2Inval, 10
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r11, Reg64|BaseIndex, RegRex, 3, Dw2Inval, 11
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r12, Reg64|BaseIndex, RegRex, 4, Dw2Inval, 12
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r13, Reg64|BaseIndex, RegRex, 5, Dw2Inval, 13
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r14, Reg64|BaseIndex, RegRex, 6, Dw2Inval, 14
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r15, Reg64|BaseIndex, RegRex, 7, Dw2Inval, 15
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eax, Reg|Acc|Dword|BaseIndex, 0, 0, 0, Dw2Inval
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ecx, Reg|Dword|BaseIndex, 0, 1, 1, Dw2Inval
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edx, Reg|Dword|BaseIndex, 0, 2, 2, Dw2Inval
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ebx, Reg|Dword|BaseIndex, 0, 3, 3, Dw2Inval
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esp, Reg|Dword, 0, 4, 4, Dw2Inval
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ebp, Reg|Dword|BaseIndex, 0, 5, 5, Dw2Inval
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esi, Reg|Dword|BaseIndex, 0, 6, 6, Dw2Inval
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edi, Reg|Dword|BaseIndex, 0, 7, 7, Dw2Inval
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r8d, Reg|Dword|BaseIndex, RegRex, 0, Dw2Inval, Dw2Inval
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r9d, Reg|Dword|BaseIndex, RegRex, 1, Dw2Inval, Dw2Inval
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r10d, Reg|Dword|BaseIndex, RegRex, 2, Dw2Inval, Dw2Inval
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r11d, Reg|Dword|BaseIndex, RegRex, 3, Dw2Inval, Dw2Inval
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r12d, Reg|Dword|BaseIndex, RegRex, 4, Dw2Inval, Dw2Inval
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r13d, Reg|Dword|BaseIndex, RegRex, 5, Dw2Inval, Dw2Inval
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r14d, Reg|Dword|BaseIndex, RegRex, 6, Dw2Inval, Dw2Inval
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r15d, Reg|Dword|BaseIndex, RegRex, 7, Dw2Inval, Dw2Inval
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rax, Reg|Acc|Qword|BaseIndex, 0, 0, Dw2Inval, 0
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rcx, Reg|Qword|BaseIndex, 0, 1, Dw2Inval, 2
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rdx, Reg|Qword|BaseIndex, 0, 2, Dw2Inval, 1
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rbx, Reg|Qword|BaseIndex, 0, 3, Dw2Inval, 3
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rsp, Reg|Qword, 0, 4, Dw2Inval, 7
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rbp, Reg|Qword|BaseIndex, 0, 5, Dw2Inval, 6
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rsi, Reg|Qword|BaseIndex, 0, 6, Dw2Inval, 4
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rdi, Reg|Qword|BaseIndex, 0, 7, Dw2Inval, 5
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r8, Reg|Qword|BaseIndex, RegRex, 0, Dw2Inval, 8
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r9, Reg|Qword|BaseIndex, RegRex, 1, Dw2Inval, 9
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r10, Reg|Qword|BaseIndex, RegRex, 2, Dw2Inval, 10
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r11, Reg|Qword|BaseIndex, RegRex, 3, Dw2Inval, 11
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r12, Reg|Qword|BaseIndex, RegRex, 4, Dw2Inval, 12
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r13, Reg|Qword|BaseIndex, RegRex, 5, Dw2Inval, 13
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r14, Reg|Qword|BaseIndex, RegRex, 6, Dw2Inval, 14
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r15, Reg|Qword|BaseIndex, RegRex, 7, Dw2Inval, 15
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// Vector mask registers.
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k0, RegMask, 0, 0, 93, 118
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k1, RegMask, 0, 1, 94, 119
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@ -180,104 +180,104 @@ mm4, RegMMX, 0, 4, 33, 45
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mm5, RegMMX, 0, 5, 34, 46
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mm6, RegMMX, 0, 6, 35, 47
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mm7, RegMMX, 0, 7, 36, 48
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xmm0, RegXMM|Acc, 0, 0, 21, 17
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xmm1, RegXMM, 0, 1, 22, 18
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xmm2, RegXMM, 0, 2, 23, 19
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xmm3, RegXMM, 0, 3, 24, 20
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xmm4, RegXMM, 0, 4, 25, 21
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xmm5, RegXMM, 0, 5, 26, 22
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xmm6, RegXMM, 0, 6, 27, 23
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xmm7, RegXMM, 0, 7, 28, 24
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xmm8, RegXMM, RegRex, 0, Dw2Inval, 25
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xmm9, RegXMM, RegRex, 1, Dw2Inval, 26
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xmm10, RegXMM, RegRex, 2, Dw2Inval, 27
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xmm11, RegXMM, RegRex, 3, Dw2Inval, 28
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xmm12, RegXMM, RegRex, 4, Dw2Inval, 29
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xmm13, RegXMM, RegRex, 5, Dw2Inval, 30
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xmm14, RegXMM, RegRex, 6, Dw2Inval, 31
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xmm15, RegXMM, RegRex, 7, Dw2Inval, 32
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xmm16, RegXMM, RegVRex, 0, Dw2Inval, 67
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xmm17, RegXMM, RegVRex, 1, Dw2Inval, 68
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xmm18, RegXMM, RegVRex, 2, Dw2Inval, 69
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xmm19, RegXMM, RegVRex, 3, Dw2Inval, 70
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xmm20, RegXMM, RegVRex, 4, Dw2Inval, 71
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xmm21, RegXMM, RegVRex, 5, Dw2Inval, 72
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xmm22, RegXMM, RegVRex, 6, Dw2Inval, 73
|
||||
xmm23, RegXMM, RegVRex, 7, Dw2Inval, 74
|
||||
xmm24, RegXMM, RegVRex|RegRex, 0, Dw2Inval, 75
|
||||
xmm25, RegXMM, RegVRex|RegRex, 1, Dw2Inval, 76
|
||||
xmm26, RegXMM, RegVRex|RegRex, 2, Dw2Inval, 77
|
||||
xmm27, RegXMM, RegVRex|RegRex, 3, Dw2Inval, 78
|
||||
xmm28, RegXMM, RegVRex|RegRex, 4, Dw2Inval, 79
|
||||
xmm29, RegXMM, RegVRex|RegRex, 5, Dw2Inval, 80
|
||||
xmm30, RegXMM, RegVRex|RegRex, 6, Dw2Inval, 81
|
||||
xmm31, RegXMM, RegVRex|RegRex, 7, Dw2Inval, 82
|
||||
xmm0, RegSIMD|Acc|Xmmword, 0, 0, 21, 17
|
||||
xmm1, RegSIMD|Xmmword, 0, 1, 22, 18
|
||||
xmm2, RegSIMD|Xmmword, 0, 2, 23, 19
|
||||
xmm3, RegSIMD|Xmmword, 0, 3, 24, 20
|
||||
xmm4, RegSIMD|Xmmword, 0, 4, 25, 21
|
||||
xmm5, RegSIMD|Xmmword, 0, 5, 26, 22
|
||||
xmm6, RegSIMD|Xmmword, 0, 6, 27, 23
|
||||
xmm7, RegSIMD|Xmmword, 0, 7, 28, 24
|
||||
xmm8, RegSIMD|Xmmword, RegRex, 0, Dw2Inval, 25
|
||||
xmm9, RegSIMD|Xmmword, RegRex, 1, Dw2Inval, 26
|
||||
xmm10, RegSIMD|Xmmword, RegRex, 2, Dw2Inval, 27
|
||||
xmm11, RegSIMD|Xmmword, RegRex, 3, Dw2Inval, 28
|
||||
xmm12, RegSIMD|Xmmword, RegRex, 4, Dw2Inval, 29
|
||||
xmm13, RegSIMD|Xmmword, RegRex, 5, Dw2Inval, 30
|
||||
xmm14, RegSIMD|Xmmword, RegRex, 6, Dw2Inval, 31
|
||||
xmm15, RegSIMD|Xmmword, RegRex, 7, Dw2Inval, 32
|
||||
xmm16, RegSIMD|Xmmword, RegVRex, 0, Dw2Inval, 67
|
||||
xmm17, RegSIMD|Xmmword, RegVRex, 1, Dw2Inval, 68
|
||||
xmm18, RegSIMD|Xmmword, RegVRex, 2, Dw2Inval, 69
|
||||
xmm19, RegSIMD|Xmmword, RegVRex, 3, Dw2Inval, 70
|
||||
xmm20, RegSIMD|Xmmword, RegVRex, 4, Dw2Inval, 71
|
||||
xmm21, RegSIMD|Xmmword, RegVRex, 5, Dw2Inval, 72
|
||||
xmm22, RegSIMD|Xmmword, RegVRex, 6, Dw2Inval, 73
|
||||
xmm23, RegSIMD|Xmmword, RegVRex, 7, Dw2Inval, 74
|
||||
xmm24, RegSIMD|Xmmword, RegVRex|RegRex, 0, Dw2Inval, 75
|
||||
xmm25, RegSIMD|Xmmword, RegVRex|RegRex, 1, Dw2Inval, 76
|
||||
xmm26, RegSIMD|Xmmword, RegVRex|RegRex, 2, Dw2Inval, 77
|
||||
xmm27, RegSIMD|Xmmword, RegVRex|RegRex, 3, Dw2Inval, 78
|
||||
xmm28, RegSIMD|Xmmword, RegVRex|RegRex, 4, Dw2Inval, 79
|
||||
xmm29, RegSIMD|Xmmword, RegVRex|RegRex, 5, Dw2Inval, 80
|
||||
xmm30, RegSIMD|Xmmword, RegVRex|RegRex, 6, Dw2Inval, 81
|
||||
xmm31, RegSIMD|Xmmword, RegVRex|RegRex, 7, Dw2Inval, 82
|
||||
// AVX registers.
|
||||
ymm0, RegYMM, 0, 0, Dw2Inval, Dw2Inval
|
||||
ymm1, RegYMM, 0, 1, Dw2Inval, Dw2Inval
|
||||
ymm2, RegYMM, 0, 2, Dw2Inval, Dw2Inval
|
||||
ymm3, RegYMM, 0, 3, Dw2Inval, Dw2Inval
|
||||
ymm4, RegYMM, 0, 4, Dw2Inval, Dw2Inval
|
||||
ymm5, RegYMM, 0, 5, Dw2Inval, Dw2Inval
|
||||
ymm6, RegYMM, 0, 6, Dw2Inval, Dw2Inval
|
||||
ymm7, RegYMM, 0, 7, Dw2Inval, Dw2Inval
|
||||
ymm8, RegYMM, RegRex, 0, Dw2Inval, Dw2Inval
|
||||
ymm9, RegYMM, RegRex, 1, Dw2Inval, Dw2Inval
|
||||
ymm10, RegYMM, RegRex, 2, Dw2Inval, Dw2Inval
|
||||
ymm11, RegYMM, RegRex, 3, Dw2Inval, Dw2Inval
|
||||
ymm12, RegYMM, RegRex, 4, Dw2Inval, Dw2Inval
|
||||
ymm13, RegYMM, RegRex, 5, Dw2Inval, Dw2Inval
|
||||
ymm14, RegYMM, RegRex, 6, Dw2Inval, Dw2Inval
|
||||
ymm15, RegYMM, RegRex, 7, Dw2Inval, Dw2Inval
|
||||
ymm16, RegYMM, RegVRex, 0, Dw2Inval, Dw2Inval
|
||||
ymm17, RegYMM, RegVRex, 1, Dw2Inval, Dw2Inval
|
||||
ymm18, RegYMM, RegVRex, 2, Dw2Inval, Dw2Inval
|
||||
ymm19, RegYMM, RegVRex, 3, Dw2Inval, Dw2Inval
|
||||
ymm20, RegYMM, RegVRex, 4, Dw2Inval, Dw2Inval
|
||||
ymm21, RegYMM, RegVRex, 5, Dw2Inval, Dw2Inval
|
||||
ymm22, RegYMM, RegVRex, 6, Dw2Inval, Dw2Inval
|
||||
ymm23, RegYMM, RegVRex, 7, Dw2Inval, Dw2Inval
|
||||
ymm24, RegYMM, RegVRex|RegRex, 0, Dw2Inval, Dw2Inval
|
||||
ymm25, RegYMM, RegVRex|RegRex, 1, Dw2Inval, Dw2Inval
|
||||
ymm26, RegYMM, RegVRex|RegRex, 2, Dw2Inval, Dw2Inval
|
||||
ymm27, RegYMM, RegVRex|RegRex, 3, Dw2Inval, Dw2Inval
|
||||
ymm28, RegYMM, RegVRex|RegRex, 4, Dw2Inval, Dw2Inval
|
||||
ymm29, RegYMM, RegVRex|RegRex, 5, Dw2Inval, Dw2Inval
|
||||
ymm30, RegYMM, RegVRex|RegRex, 6, Dw2Inval, Dw2Inval
|
||||
ymm31, RegYMM, RegVRex|RegRex, 7, Dw2Inval, Dw2Inval
|
||||
ymm0, RegSIMD|Ymmword, 0, 0, Dw2Inval, Dw2Inval
|
||||
ymm1, RegSIMD|Ymmword, 0, 1, Dw2Inval, Dw2Inval
|
||||
ymm2, RegSIMD|Ymmword, 0, 2, Dw2Inval, Dw2Inval
|
||||
ymm3, RegSIMD|Ymmword, 0, 3, Dw2Inval, Dw2Inval
|
||||
ymm4, RegSIMD|Ymmword, 0, 4, Dw2Inval, Dw2Inval
|
||||
ymm5, RegSIMD|Ymmword, 0, 5, Dw2Inval, Dw2Inval
|
||||
ymm6, RegSIMD|Ymmword, 0, 6, Dw2Inval, Dw2Inval
|
||||
ymm7, RegSIMD|Ymmword, 0, 7, Dw2Inval, Dw2Inval
|
||||
ymm8, RegSIMD|Ymmword, RegRex, 0, Dw2Inval, Dw2Inval
|
||||
ymm9, RegSIMD|Ymmword, RegRex, 1, Dw2Inval, Dw2Inval
|
||||
ymm10, RegSIMD|Ymmword, RegRex, 2, Dw2Inval, Dw2Inval
|
||||
ymm11, RegSIMD|Ymmword, RegRex, 3, Dw2Inval, Dw2Inval
|
||||
ymm12, RegSIMD|Ymmword, RegRex, 4, Dw2Inval, Dw2Inval
|
||||
ymm13, RegSIMD|Ymmword, RegRex, 5, Dw2Inval, Dw2Inval
|
||||
ymm14, RegSIMD|Ymmword, RegRex, 6, Dw2Inval, Dw2Inval
|
||||
ymm15, RegSIMD|Ymmword, RegRex, 7, Dw2Inval, Dw2Inval
|
||||
ymm16, RegSIMD|Ymmword, RegVRex, 0, Dw2Inval, Dw2Inval
|
||||
ymm17, RegSIMD|Ymmword, RegVRex, 1, Dw2Inval, Dw2Inval
|
||||
ymm18, RegSIMD|Ymmword, RegVRex, 2, Dw2Inval, Dw2Inval
|
||||
ymm19, RegSIMD|Ymmword, RegVRex, 3, Dw2Inval, Dw2Inval
|
||||
ymm20, RegSIMD|Ymmword, RegVRex, 4, Dw2Inval, Dw2Inval
|
||||
ymm21, RegSIMD|Ymmword, RegVRex, 5, Dw2Inval, Dw2Inval
|
||||
ymm22, RegSIMD|Ymmword, RegVRex, 6, Dw2Inval, Dw2Inval
|
||||
ymm23, RegSIMD|Ymmword, RegVRex, 7, Dw2Inval, Dw2Inval
|
||||
ymm24, RegSIMD|Ymmword, RegVRex|RegRex, 0, Dw2Inval, Dw2Inval
|
||||
ymm25, RegSIMD|Ymmword, RegVRex|RegRex, 1, Dw2Inval, Dw2Inval
|
||||
ymm26, RegSIMD|Ymmword, RegVRex|RegRex, 2, Dw2Inval, Dw2Inval
|
||||
ymm27, RegSIMD|Ymmword, RegVRex|RegRex, 3, Dw2Inval, Dw2Inval
|
||||
ymm28, RegSIMD|Ymmword, RegVRex|RegRex, 4, Dw2Inval, Dw2Inval
|
||||
ymm29, RegSIMD|Ymmword, RegVRex|RegRex, 5, Dw2Inval, Dw2Inval
|
||||
ymm30, RegSIMD|Ymmword, RegVRex|RegRex, 6, Dw2Inval, Dw2Inval
|
||||
ymm31, RegSIMD|Ymmword, RegVRex|RegRex, 7, Dw2Inval, Dw2Inval
|
||||
// AVX512 registers.
|
||||
zmm0, RegZMM, 0, 0, Dw2Inval, Dw2Inval
|
||||
zmm1, RegZMM, 0, 1, Dw2Inval, Dw2Inval
|
||||
zmm2, RegZMM, 0, 2, Dw2Inval, Dw2Inval
|
||||
zmm3, RegZMM, 0, 3, Dw2Inval, Dw2Inval
|
||||
zmm4, RegZMM, 0, 4, Dw2Inval, Dw2Inval
|
||||
zmm5, RegZMM, 0, 5, Dw2Inval, Dw2Inval
|
||||
zmm6, RegZMM, 0, 6, Dw2Inval, Dw2Inval
|
||||
zmm7, RegZMM, 0, 7, Dw2Inval, Dw2Inval
|
||||
zmm8, RegZMM, RegRex, 0, Dw2Inval, Dw2Inval
|
||||
zmm9, RegZMM, RegRex, 1, Dw2Inval, Dw2Inval
|
||||
zmm10, RegZMM, RegRex, 2, Dw2Inval, Dw2Inval
|
||||
zmm11, RegZMM, RegRex, 3, Dw2Inval, Dw2Inval
|
||||
zmm12, RegZMM, RegRex, 4, Dw2Inval, Dw2Inval
|
||||
zmm13, RegZMM, RegRex, 5, Dw2Inval, Dw2Inval
|
||||
zmm14, RegZMM, RegRex, 6, Dw2Inval, Dw2Inval
|
||||
zmm15, RegZMM, RegRex, 7, Dw2Inval, Dw2Inval
|
||||
zmm16, RegZMM, RegVRex, 0, Dw2Inval, Dw2Inval
|
||||
zmm17, RegZMM, RegVRex, 1, Dw2Inval, Dw2Inval
|
||||
zmm18, RegZMM, RegVRex, 2, Dw2Inval, Dw2Inval
|
||||
zmm19, RegZMM, RegVRex, 3, Dw2Inval, Dw2Inval
|
||||
zmm20, RegZMM, RegVRex, 4, Dw2Inval, Dw2Inval
|
||||
zmm21, RegZMM, RegVRex, 5, Dw2Inval, Dw2Inval
|
||||
zmm22, RegZMM, RegVRex, 6, Dw2Inval, Dw2Inval
|
||||
zmm23, RegZMM, RegVRex, 7, Dw2Inval, Dw2Inval
|
||||
zmm24, RegZMM, RegVRex|RegRex, 0, Dw2Inval, Dw2Inval
|
||||
zmm25, RegZMM, RegVRex|RegRex, 1, Dw2Inval, Dw2Inval
|
||||
zmm26, RegZMM, RegVRex|RegRex, 2, Dw2Inval, Dw2Inval
|
||||
zmm27, RegZMM, RegVRex|RegRex, 3, Dw2Inval, Dw2Inval
|
||||
zmm28, RegZMM, RegVRex|RegRex, 4, Dw2Inval, Dw2Inval
|
||||
zmm29, RegZMM, RegVRex|RegRex, 5, Dw2Inval, Dw2Inval
|
||||
zmm30, RegZMM, RegVRex|RegRex, 6, Dw2Inval, Dw2Inval
|
||||
zmm31, RegZMM, RegVRex|RegRex, 7, Dw2Inval, Dw2Inval
|
||||
zmm0, RegSIMD|Zmmword, 0, 0, Dw2Inval, Dw2Inval
|
||||
zmm1, RegSIMD|Zmmword, 0, 1, Dw2Inval, Dw2Inval
|
||||
zmm2, RegSIMD|Zmmword, 0, 2, Dw2Inval, Dw2Inval
|
||||
zmm3, RegSIMD|Zmmword, 0, 3, Dw2Inval, Dw2Inval
|
||||
zmm4, RegSIMD|Zmmword, 0, 4, Dw2Inval, Dw2Inval
|
||||
zmm5, RegSIMD|Zmmword, 0, 5, Dw2Inval, Dw2Inval
|
||||
zmm6, RegSIMD|Zmmword, 0, 6, Dw2Inval, Dw2Inval
|
||||
zmm7, RegSIMD|Zmmword, 0, 7, Dw2Inval, Dw2Inval
|
||||
zmm8, RegSIMD|Zmmword, RegRex, 0, Dw2Inval, Dw2Inval
|
||||
zmm9, RegSIMD|Zmmword, RegRex, 1, Dw2Inval, Dw2Inval
|
||||
zmm10, RegSIMD|Zmmword, RegRex, 2, Dw2Inval, Dw2Inval
|
||||
zmm11, RegSIMD|Zmmword, RegRex, 3, Dw2Inval, Dw2Inval
|
||||
zmm12, RegSIMD|Zmmword, RegRex, 4, Dw2Inval, Dw2Inval
|
||||
zmm13, RegSIMD|Zmmword, RegRex, 5, Dw2Inval, Dw2Inval
|
||||
zmm14, RegSIMD|Zmmword, RegRex, 6, Dw2Inval, Dw2Inval
|
||||
zmm15, RegSIMD|Zmmword, RegRex, 7, Dw2Inval, Dw2Inval
|
||||
zmm16, RegSIMD|Zmmword, RegVRex, 0, Dw2Inval, Dw2Inval
|
||||
zmm17, RegSIMD|Zmmword, RegVRex, 1, Dw2Inval, Dw2Inval
|
||||
zmm18, RegSIMD|Zmmword, RegVRex, 2, Dw2Inval, Dw2Inval
|
||||
zmm19, RegSIMD|Zmmword, RegVRex, 3, Dw2Inval, Dw2Inval
|
||||
zmm20, RegSIMD|Zmmword, RegVRex, 4, Dw2Inval, Dw2Inval
|
||||
zmm21, RegSIMD|Zmmword, RegVRex, 5, Dw2Inval, Dw2Inval
|
||||
zmm22, RegSIMD|Zmmword, RegVRex, 6, Dw2Inval, Dw2Inval
|
||||
zmm23, RegSIMD|Zmmword, RegVRex, 7, Dw2Inval, Dw2Inval
|
||||
zmm24, RegSIMD|Zmmword, RegVRex|RegRex, 0, Dw2Inval, Dw2Inval
|
||||
zmm25, RegSIMD|Zmmword, RegVRex|RegRex, 1, Dw2Inval, Dw2Inval
|
||||
zmm26, RegSIMD|Zmmword, RegVRex|RegRex, 2, Dw2Inval, Dw2Inval
|
||||
zmm27, RegSIMD|Zmmword, RegVRex|RegRex, 3, Dw2Inval, Dw2Inval
|
||||
zmm28, RegSIMD|Zmmword, RegVRex|RegRex, 4, Dw2Inval, Dw2Inval
|
||||
zmm29, RegSIMD|Zmmword, RegVRex|RegRex, 5, Dw2Inval, Dw2Inval
|
||||
zmm30, RegSIMD|Zmmword, RegVRex|RegRex, 6, Dw2Inval, Dw2Inval
|
||||
zmm31, RegSIMD|Zmmword, RegVRex|RegRex, 7, Dw2Inval, Dw2Inval
|
||||
// Bound registers for MPX
|
||||
bnd0, RegBND, 0, 0, Dw2Inval, Dw2Inval
|
||||
bnd1, RegBND, 0, 1, Dw2Inval, Dw2Inval
|
||||
@ -292,14 +292,14 @@ eip, Dword, RegRex64, RegIP, 8, Dw2Inval
|
||||
riz, Qword|BaseIndex, RegRex64, RegIZ, Dw2Inval, Dw2Inval
|
||||
eiz, Dword|BaseIndex, 0, RegIZ, Dw2Inval, Dw2Inval
|
||||
// fp regs.
|
||||
st(0), FloatReg|Acc, 0, 0, 11, 33
|
||||
st(1), FloatReg, 0, 1, 12, 34
|
||||
st(2), FloatReg, 0, 2, 13, 35
|
||||
st(3), FloatReg, 0, 3, 14, 36
|
||||
st(4), FloatReg, 0, 4, 15, 37
|
||||
st(5), FloatReg, 0, 5, 16, 38
|
||||
st(6), FloatReg, 0, 6, 17, 39
|
||||
st(7), FloatReg, 0, 7, 18, 40
|
||||
st(0), Reg|Acc|Tbyte, 0, 0, 11, 33
|
||||
st(1), Reg|Tbyte, 0, 1, 12, 34
|
||||
st(2), Reg|Tbyte, 0, 2, 13, 35
|
||||
st(3), Reg|Tbyte, 0, 3, 14, 36
|
||||
st(4), Reg|Tbyte, 0, 4, 15, 37
|
||||
st(5), Reg|Tbyte, 0, 5, 16, 38
|
||||
st(6), Reg|Tbyte, 0, 6, 17, 39
|
||||
st(7), Reg|Tbyte, 0, 7, 18, 40
|
||||
// Pseudo-register names only used in .cfi_* directives
|
||||
eflags, 0, 0, 0, 9, 49
|
||||
rflags, 0, 0, 0, Dw2Inval, 49
|
||||
|
||||
Loading…
Reference in New Issue
Block a user