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2003-12-02 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>

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* Makefile.in : Add new machine m32r2.
        * m32r2.c : New file for m32r2.
	* mloop2.in : Ditto
	* model2.c : Ditto
	* sem2-switch.c : Ditto
        * m32r-sim.h : Add EVB register.
        * sim-if.h : Ditto
        * sim-main.h : Ditto
        * traps.c : Ditto
This commit is contained in:
Andrew Cagney 2003-12-07 02:27:45 +00:00
parent 48ecb30c92
commit 3c041444b5
7 changed files with 122 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
sim/m32r/ChangeLog
View File

@ -1,3 +1,15 @@
2003-12-02 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
* Makefile.in : Add new machine m32r2.
* m32r2.c : New file for m32r2.
* mloop2.in : Ditto
* model2.c : Ditto
* sem2-switch.c : Ditto
* m32r-sim.h : Add EVB register.
* sim-if.h : Ditto
* sim-main.h : Ditto
* traps.c : Ditto
2003-09-08 Dave Brolley <brolley@redhat.com>
On behalf of Doug Evans <dje@sebabeach.org>

39
sim/m32r/Makefile.in
View File

@ -22,6 +22,7 @@
M32R_OBJS = m32r.o cpu.o decode.o sem.o model.o mloop.o
M32RX_OBJS = m32rx.o cpux.o decodex.o modelx.o mloopx.o
M32R2_OBJS = m32r2.o cpu2.o decode2.o model2.o mloop2.o
CONFIG_DEVICES = dv-sockser.o
CONFIG_DEVICES =
@ -38,6 +39,7 @@ SIM_OBJS = \
sim-if.o arch.o \
$(M32R_OBJS) \
$(M32RX_OBJS) \
$(M32R2_OBJS) \
traps.o devices.o \
$(CONFIG_DEVICES)
@ -113,10 +115,35 @@ decodex.o: decodex.c $(M32RXF_INCLUDE_DEPS)
semx.o: semx.c $(M32RXF_INCLUDE_DEPS)
modelx.o: modelx.c $(M32RXF_INCLUDE_DEPS)
# M32R2 objs
M32R2F_INCLUDE_DEPS = \
$(CGEN_MAIN_CPU_DEPS) \
cpu2.h decode2.h eng2.h
m32r2.o: m32r2.c $(M32R2F_INCLUDE_DEPS)
# FIXME: Use of `mono' is wip.
mloop2.c eng2.h: stamp-2mloop
stamp-2mloop: $(srcdir)/../common/genmloop.sh mloop2.in Makefile
$(SHELL) $(srccom)/genmloop.sh \
-mono -no-fast -pbb -parallel-write -switch sem2-switch.c \
-cpu m32r2f -infile $(srcdir)/mloop2.in
$(SHELL) $(srcroot)/move-if-change eng.hin eng2.h
$(SHELL) $(srcroot)/move-if-change mloop.cin mloop2.c
touch stamp-2mloop
mloop2.o: mloop2.c sem2-switch.c $(M32R2F_INCLUDE_DEPS)
cpu2.o: cpu2.c $(M32R2F_INCLUDE_DEPS)
decode2.o: decode2.c $(M32R2F_INCLUDE_DEPS)
sem2.o: sem2.c $(M32R2F_INCLUDE_DEPS)
model2.o: model2.c $(M32R2F_INCLUDE_DEPS)
m32r-clean:
rm -f mloop.c eng.h stamp-mloop
rm -f mloopx.c engx.h stamp-xmloop
rm -f stamp-arch stamp-cpu stamp-xcpu
rm -f mloop2.c eng2.h stamp-2mloop
rm -f stamp-arch stamp-cpu stamp-xcpu stamp-2cpu
rm -f tmp-*
# cgen support, enable with --enable-cgen-maint
@ -148,3 +175,13 @@ stamp-xcpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(CGEN_CPU_DIR)/
EXTRAFILES="$(CGEN_CPU_SEMSW)"
touch stamp-xcpu
cpux.h semx-switch.c modelx.c decodex.c decodex.h: $(CGEN_MAINT) stamp-xcpu
stamp-2cpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(CGEN_CPU_DIR)/m32r.cpu
$(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \
cpu=m32r2f mach=m32r2 SUFFIX=2 \
archfile=$(CGEN_CPU_DIR)/m32r.cpu \
FLAGS="with-scache with-profile=fn" \
EXTRAFILES="$(CGEN_CPU_SEMSW)"
touch stamp-2cpu
cpu2.h sem2-switch.c model2.c decode2.c decode2.h: $(CGEN_MAINT) stamp-2cpu

1
sim/m32r/m32r-sim.h
View File

@ -34,6 +34,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
#define ACC1H_REGNUM 25
#define BBPSW_REGNUM 26
#define BBPC_REGNUM 27
#define EVB_REGNUM 28
extern int m32r_decode_gdb_ctrl_regnum (int);

53
sim/m32r/m32r.c
View File

@ -39,6 +39,7 @@ m32r_decode_gdb_ctrl_regnum (int gdb_regnum)
case BPC_REGNUM : return H_CR_BPC;
case BBPSW_REGNUM : return H_CR_BBPSW;
case BBPC_REGNUM : return H_CR_BBPC;
case EVB_REGNUM : return H_CR_CR5;
}
abort ();
}
@ -62,26 +63,33 @@ m32rbf_fetch_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len
case BPC_REGNUM :
case BBPSW_REGNUM :
case BBPC_REGNUM :
case EVB_REGNUM :
SETTWI (buf, a_m32r_h_cr_get (current_cpu,
m32r_decode_gdb_ctrl_regnum (rn)));
break;
case PC_REGNUM :
if (mach == MACH_M32R)
SETTWI (buf, m32rbf_h_pc_get (current_cpu));
else
else if (mach == MACH_M32RX)
SETTWI (buf, m32rxf_h_pc_get (current_cpu));
else
SETTWI (buf, m32r2f_h_pc_get (current_cpu));
break;
case ACCL_REGNUM :
if (mach == MACH_M32R)
SETTWI (buf, GETLODI (m32rbf_h_accum_get (current_cpu)));
else
else if (mach == MACH_M32RX)
SETTWI (buf, GETLODI (m32rxf_h_accum_get (current_cpu)));
else
SETTWI (buf, GETLODI (m32r2f_h_accum_get (current_cpu)));
break;
case ACCH_REGNUM :
if (mach == MACH_M32R)
SETTWI (buf, GETHIDI (m32rbf_h_accum_get (current_cpu)));
else
else if (mach == MACH_M32RX)
SETTWI (buf, GETHIDI (m32rxf_h_accum_get (current_cpu)));
else
SETTWI (buf, GETHIDI (m32r2f_h_accum_get (current_cpu)));
break;
default :
return 0;
@ -109,6 +117,7 @@ m32rbf_store_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len
case BPC_REGNUM :
case BBPSW_REGNUM :
case BBPC_REGNUM :
case EVB_REGNUM :
a_m32r_h_cr_set (current_cpu,
m32r_decode_gdb_ctrl_regnum (rn),
GETTWI (buf));
@ -116,21 +125,27 @@ m32rbf_store_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len
case PC_REGNUM :
if (mach == MACH_M32R)
m32rbf_h_pc_set (current_cpu, GETTWI (buf));
else
else if (mach == MACH_M32RX)
m32rxf_h_pc_set (current_cpu, GETTWI (buf));
else
m32r2f_h_pc_set (current_cpu, GETTWI (buf));
break;
case ACCL_REGNUM :
{
DI val;
if (mach == MACH_M32R)
val = m32rbf_h_accum_get (current_cpu);
else
else if (mach == MACH_M32RX)
val = m32rxf_h_accum_get (current_cpu);
else
val = m32r2f_h_accum_get (current_cpu);
SETLODI (val, GETTWI (buf));
if (mach == MACH_M32R)
m32rbf_h_accum_set (current_cpu, val);
else
else if (mach == MACH_M32RX)
m32rxf_h_accum_set (current_cpu, val);
else
m32r2f_h_accum_set (current_cpu, val);
break;
}
case ACCH_REGNUM :
@ -138,13 +153,17 @@ m32rbf_store_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len
DI val;
if (mach == MACH_M32R)
val = m32rbf_h_accum_get (current_cpu);
else
else if (mach == MACH_M32RX)
val = m32rxf_h_accum_get (current_cpu);
else
val = m32r2f_h_accum_get (current_cpu);
SETHIDI (val, GETTWI (buf));
if (mach == MACH_M32R)
m32rbf_h_accum_set (current_cpu, val);
else
else if (mach == MACH_M32RX)
m32rxf_h_accum_set (current_cpu, val);
else
m32r2f_h_accum_set (current_cpu, val);
break;
}
default :
@ -168,6 +187,10 @@ a_m32r_h_gr_get (SIM_CPU *current_cpu, UINT regno)
#ifdef HAVE_CPU_M32RXF
case MACH_M32RX :
return m32rxf_h_gr_get (current_cpu, regno);
#endif
#ifdef HAVE_CPU_M32R2F
case MACH_M32R2 :
return m32r2f_h_gr_get (current_cpu, regno);
#endif
default :
abort ();
@ -188,6 +211,11 @@ a_m32r_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
case MACH_M32RX :
m32rxf_h_gr_set (current_cpu, regno, newval);
break;
#endif
#ifdef HAVE_CPU_M32RXF
case MACH_M32R2 :
m32r2f_h_gr_set (current_cpu, regno, newval);
break;
#endif
default :
abort ();
@ -206,6 +234,10 @@ a_m32r_h_cr_get (SIM_CPU *current_cpu, UINT regno)
#ifdef HAVE_CPU_M32RXF
case MACH_M32RX :
return m32rxf_h_cr_get (current_cpu, regno);
#endif
#ifdef HAVE_CPU_M32R2F
case MACH_M32R2 :
return m32r2f_h_cr_get (current_cpu, regno);
#endif
default :
abort ();
@ -226,6 +258,11 @@ a_m32r_h_cr_set (SIM_CPU *current_cpu, UINT regno, USI newval)
case MACH_M32RX :
m32rxf_h_cr_set (current_cpu, regno, newval);
break;
#endif
#ifdef HAVE_CPU_M32RXF
case MACH_M32R2 :
m32r2f_h_cr_set (current_cpu, regno, newval);
break;
#endif
default :
abort ();

5
sim/m32r/sim-if.c
View File

@ -240,6 +240,11 @@ print_m32r_misc_cpu (SIM_CPU *cpu, int verbose)
PROFILE_LABEL_WIDTH, "Parallel insns:",
sim_add_commas (buf, sizeof (buf),
CPU_M32R_MISC_PROFILE (cpu)->parallel_count));
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_m32r2)
sim_io_printf (sd, " %-*s %s\n\n",
PROFILE_LABEL_WIDTH, "Parallel insns:",
sim_add_commas (buf, sizeof (buf),
CPU_M32R_MISC_PROFILE (cpu)->parallel_count));
}
}

2
sim/m32r/sim-main.h
View File

@ -60,6 +60,8 @@ struct _sim_cpu {
M32RBF_CPU_DATA cpu_data;
#elif defined (WANT_CPU_M32RXF)
M32RXF_CPU_DATA cpu_data;
#elif defined (WANT_CPU_M32R2F)
M32R2F_CPU_DATA cpu_data;
#endif
};

23
sim/m32r/traps.c
View File

@ -21,6 +21,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
#include "sim-main.h"
#include "targ-vals.h"
#define TRAP_FLUSH_CACHE 12
/* The semantic code invokes this for invalid (unrecognized) instructions.
CIA is the address with the invalid insn.
VPC is the virtual pc of the following insn. */
@ -68,12 +69,18 @@ m32r_core_signal (SIM_DESC sd, SIM_CPU *current_cpu, sim_cia cia,
/* sm not changed */
m32rbf_h_psw_set (current_cpu, m32rbf_h_psw_get (current_cpu) & 0x80);
}
else
else if (MACH_NUM (CPU_MACH (current_cpu)) == MACH_M32RX)
{
m32rxf_h_bpsw_set (current_cpu, m32rxf_h_psw_get (current_cpu));
/* sm not changed */
m32rxf_h_psw_set (current_cpu, m32rxf_h_psw_get (current_cpu) & 0x80);
}
else
{
m32r2f_h_bpsw_set (current_cpu, m32r2f_h_psw_get (current_cpu));
/* sm not changed */
m32r2f_h_psw_set (current_cpu, m32r2f_h_psw_get (current_cpu) & 0x80);
}
a_m32r_h_cr_set (current_cpu, H_CR_BPC, cia);
sim_engine_restart (CPU_STATE (current_cpu), current_cpu, NULL,
@ -131,8 +138,10 @@ m32r_trap (SIM_CPU *current_cpu, PCADDR pc, int num)
if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT)
{
/* The new pc is the trap vector entry.
We assume there's a branch there to some handler. */
USI new_pc = EIT_TRAP_BASE_ADDR + num * 4;
We assume there's a branch there to some handler.
Use cr5 as EVB (EIT Vector Base) register. */
/* USI new_pc = EIT_TRAP_BASE_ADDR + num * 4; */
USI new_pc = a_m32r_h_cr_get (current_cpu, 5) + 0x40 + num * 4;
return new_pc;
}
@ -169,9 +178,15 @@ m32r_trap (SIM_CPU *current_cpu, PCADDR pc, int num)
sim_stopped, SIM_SIGTRAP);
break;
case TRAP_FLUSH_CACHE:
/* Do nothing. */
break;
default :
{
USI new_pc = EIT_TRAP_BASE_ADDR + num * 4;
/* USI new_pc = EIT_TRAP_BASE_ADDR + num * 4; */
/* Use cr5 as EVB (EIT Vector Base) register. */
USI new_pc = a_m32r_h_cr_get (current_cpu, 5) + 0x40 + num * 4;
return new_pc;
}
}