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sim: riscv: Add support for compressed integer instructions
Added support for simulation of compressed integer instruction set ("c").
Added test file sim/testsuite/riscv/c-ext.s to test compressed instructions.
The compressed instructions are available for models implementing C extension.
Such as RV32IC, RV64IC, RV32GC, RV64GC etc.
Approved-By: Andrew Burgess <aburgess@redhat.com>
This commit is contained in:
Jaydeep Patil
Andrew Burgess
parent
4dad3c1e1c
commit
3224e32fb8
@ -3,7 +3,16 @@ M(I)
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M(IM)
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M(IMA)
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M(IA)
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M(GC)
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M(IC)
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M(IMC)
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M(IMAC)
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M(IAC)
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M(E)
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M(EM)
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M(EMA)
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M(EA)
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M(EC)
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M(EMC)
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M(EMAC)
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M(EAC)
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@ -973,6 +973,321 @@ execute_a (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
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return pc;
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}
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static sim_cia
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execute_c (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
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{
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SIM_DESC sd = CPU_STATE (cpu);
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struct riscv_sim_cpu *riscv_cpu = RISCV_SIM_CPU (cpu);
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int rd = (iw >> OP_SH_RD) & OP_MASK_RD;
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int rs1_c = ((iw >> OP_SH_CRS1S) & OP_MASK_CRS1S) + 8;
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int rs2 = (iw >> OP_SH_CRS2) & OP_MASK_CRS2;
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int rs2_c = ((iw >> OP_SH_CRS2S) & OP_MASK_CRS2S) + 8;
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const char *rd_name = riscv_gpr_names_abi[rd];
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const char *rs1_c_name = riscv_gpr_names_abi[rs1_c];
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const char *rs2_name = riscv_gpr_names_abi[rs2];
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const char *rs2_c_name = riscv_gpr_names_abi[rs2_c];
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signed_word imm;
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unsigned_word tmp;
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sim_cia pc = riscv_cpu->pc + 2;
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switch (op->match)
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{
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case MATCH_C_JR | MATCH_C_MV:
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switch (op->mask)
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{
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case MASK_C_MV:
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TRACE_INSN (cpu, "c.mv %s, %s; // %s = %s",
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rd_name, rs2_name, rd_name, rs2_name);
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store_rd (cpu, rd, riscv_cpu->regs[rs2]);
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break;
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case MASK_C_JR:
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TRACE_INSN (cpu, "c.jr %s;",
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rd_name);
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pc = riscv_cpu->regs[rd];
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TRACE_BRANCH (cpu, "to %#" PRIxTW, pc);
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break;
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}
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break;
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case MATCH_C_J:
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imm = EXTRACT_CJTYPE_IMM (iw);
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TRACE_INSN (cpu, "c.j %" PRIxTW,
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imm);
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pc = riscv_cpu->pc + imm;
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TRACE_BRANCH (cpu, "to %#" PRIxTW, pc);
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break;
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case MATCH_C_JAL | MATCH_C_ADDIW:
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/* JAL and ADDIW have the same mask but are only available on RV64 or
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RV32 respectively. */
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if (RISCV_XLEN (cpu) == 64)
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{
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imm = EXTRACT_CJTYPE_IMM (iw);
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TRACE_INSN (cpu, "c.jal %" PRIxTW,
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imm);
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store_rd (cpu, SIM_RISCV_RA_REGNUM, riscv_cpu->pc + 2);
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pc = riscv_cpu->pc + imm;
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TRACE_BRANCH (cpu, "to %#" PRIxTW, pc);
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}
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else if (RISCV_XLEN (cpu) == 32)
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{
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imm = EXTRACT_CITYPE_IMM (iw);
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TRACE_INSN (cpu, "c.addiw %s, %s, %#" PRIxTW "; // %s += %#" PRIxTW,
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rd_name, rd_name, imm, rd_name, imm);
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store_rd (cpu, rd, EXTEND32 (riscv_cpu->regs[rd] + imm));
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}
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else
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{
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TRACE_INSN (cpu, "UNHANDLED INSN: %s", op->name);
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sim_engine_halt (sd, cpu, NULL, riscv_cpu->pc, sim_signalled,
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SIM_SIGILL);
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}
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break;
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case MATCH_C_JALR | MATCH_C_ADD | MATCH_C_EBREAK:
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switch (op->mask)
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{
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case MASK_C_ADD:
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TRACE_INSN (cpu, "c.add %s, %s; // %s += %s",
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rd_name, rs2_name, rd_name, rs2_name);
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store_rd (cpu, rd, riscv_cpu->regs[rd] + riscv_cpu->regs[rs2]);
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break;
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case MASK_C_JALR:
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TRACE_INSN (cpu, "c.jalr %s, %s;",
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riscv_gpr_names_abi[SIM_RISCV_RA_REGNUM], rd_name);
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store_rd (cpu, SIM_RISCV_RA_REGNUM, riscv_cpu->pc + 2);
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pc = riscv_cpu->regs[rd];
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TRACE_BRANCH (cpu, "to %#" PRIxTW, pc);
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break;
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case MASK_C_EBREAK:
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TRACE_INSN (cpu, "ebreak");
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sim_engine_halt (sd, cpu, NULL, riscv_cpu->pc, sim_stopped,
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SIM_SIGTRAP);
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}
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break;
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case MATCH_C_BEQZ:
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imm = EXTRACT_CBTYPE_IMM (iw);
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TRACE_INSN (cpu, "c.beqz %s, %#" PRIxTW "; "
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"// if (%s == 0) goto %#" PRIxTW,
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rs1_c_name, imm, rs1_c_name, riscv_cpu->pc + imm);
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if (riscv_cpu->regs[rs1_c] == riscv_cpu->regs[0])
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{
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pc = riscv_cpu->pc + imm;
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TRACE_BRANCH (cpu, "to %#" PRIxTW, pc);
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}
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break;
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case MATCH_C_BNEZ:
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imm = EXTRACT_CBTYPE_IMM (iw);
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TRACE_INSN (cpu, "c.bnez %s, %#" PRIxTW "; "
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"// if (%s != 0) goto %#" PRIxTW,
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rs1_c_name, imm, rs1_c_name, riscv_cpu->pc + imm);
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if (riscv_cpu->regs[rs1_c] != riscv_cpu->regs[0])
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{
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pc = riscv_cpu->pc + imm;
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TRACE_BRANCH (cpu, "to %#" PRIxTW, pc);
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}
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break;
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case MATCH_C_LWSP:
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imm = EXTRACT_CITYPE_LWSP_IMM (iw);
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TRACE_INSN (cpu, "c.lwsp %s, %" PRIiTW "(sp);",
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rd_name, imm);
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store_rd (cpu, rd, EXTEND32 (
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sim_core_read_unaligned_4 (cpu, riscv_cpu->pc, read_map,
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riscv_cpu->regs[SIM_RISCV_SP_REGNUM]
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+ imm)));
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break;
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case MATCH_C_LW:
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imm = EXTRACT_CLTYPE_LW_IMM (iw);
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TRACE_INSN (cpu, "c.lw %s, %" PRIiTW "(%s);",
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rs2_c_name, imm, rs1_c_name);
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store_rd (cpu, rs2_c, EXTEND32 (
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sim_core_read_unaligned_4 (cpu, riscv_cpu->pc, read_map,
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riscv_cpu->regs[rs1_c] + imm)));
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break;
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case MATCH_C_SWSP:
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imm = EXTRACT_CSSTYPE_SWSP_IMM (iw);
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TRACE_INSN (cpu, "c.swsp %s, %" PRIiTW "(sp);",
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rs2_name, imm);
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sim_core_write_unaligned_4 (cpu, riscv_cpu->pc, write_map,
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riscv_cpu->regs[SIM_RISCV_SP_REGNUM] + imm,
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riscv_cpu->regs[rs2]);
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break;
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case MATCH_C_SW:
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imm = EXTRACT_CLTYPE_LW_IMM (iw);
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TRACE_INSN (cpu, "c.sw %s, %" PRIiTW "(%s);",
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rs2_c_name, imm, rs1_c_name);
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sim_core_write_unaligned_4 (cpu, riscv_cpu->pc, write_map,
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riscv_cpu->regs[rs1_c] + (imm),
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riscv_cpu->regs[rs2_c]);
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break;
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case MATCH_C_ADDI:
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imm = EXTRACT_CITYPE_IMM (iw);
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TRACE_INSN (cpu, "c.addi %s, %s, %#" PRIxTW "; // %s += %#" PRIxTW,
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rd_name, rd_name, imm, rd_name, imm);
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store_rd (cpu, rd, riscv_cpu->regs[rd] + imm);
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break;
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case MATCH_C_LUI:
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imm = EXTRACT_CITYPE_LUI_IMM (iw);
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TRACE_INSN (cpu, "c.lui %s, %#" PRIxTW ";",
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rd_name, imm);
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store_rd (cpu, rd, imm);
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break;
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case MATCH_C_LI:
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imm = EXTRACT_CITYPE_IMM (iw);
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TRACE_INSN (cpu, "c.li %s, %#" PRIxTW "; // %s = %#" PRIxTW,
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rd_name, imm, rd_name, imm);
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store_rd (cpu, rd, imm);
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break;
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case MATCH_C_ADDI4SPN:
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imm = EXTRACT_CIWTYPE_ADDI4SPN_IMM (iw);
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TRACE_INSN (cpu, "c.addi4spn %s, %" PRIiTW "; // %s = sp + %" PRIiTW,
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rs2_c_name, imm, rs2_c_name, imm);
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store_rd (cpu, rs2_c, riscv_cpu->regs[SIM_RISCV_SP_REGNUM] + (imm));
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break;
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case MATCH_C_ADDI16SP:
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imm = EXTRACT_CITYPE_ADDI16SP_IMM (iw);
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TRACE_INSN (cpu, "c.addi16sp %s, %" PRIiTW "; // %s = sp + %" PRIiTW,
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rd_name, imm, rd_name, imm);
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store_rd (cpu, rd, riscv_cpu->regs[SIM_RISCV_SP_REGNUM] + imm);
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break;
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case MATCH_C_SUB:
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TRACE_INSN (cpu, "c.sub %s, %s; // %s = %s - %s",
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rs1_c_name, rs2_c_name, rs1_c_name, rs1_c_name, rs2_c_name);
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store_rd (cpu, rs1_c, riscv_cpu->regs[rs1_c] - riscv_cpu->regs[rs2_c]);
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break;
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case MATCH_C_AND:
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TRACE_INSN (cpu, "c.and %s, %s; // %s = %s & %s",
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rs1_c_name, rs2_c_name, rs1_c_name, rs1_c_name, rs2_c_name);
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store_rd (cpu, rs1_c, riscv_cpu->regs[rs1_c] & riscv_cpu->regs[rs2_c]);
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break;
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case MATCH_C_OR:
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TRACE_INSN (cpu, "c.or %s, %s; // %s = %s | %s",
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rs1_c_name, rs2_c_name, rs1_c_name, rs1_c_name, rs2_c_name);
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store_rd (cpu, rs1_c, riscv_cpu->regs[rs1_c] | riscv_cpu->regs[rs2_c]);
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break;
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case MATCH_C_XOR:
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TRACE_INSN (cpu, "c.xor %s, %s; // %s = %s ^ %s",
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rs1_c_name, rs2_c_name, rs1_c_name, rs1_c_name, rs2_c_name);
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store_rd (cpu, rs1_c, riscv_cpu->regs[rs1_c] ^ riscv_cpu->regs[rs2_c]);
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break;
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case MATCH_C_SLLI | MATCH_C_SLLI64:
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if (op->mask == MASK_C_SLLI64)
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{
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/* Reserved for custom use. */
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TRACE_INSN (cpu, "UNHANDLED INSN: %s", op->name);
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sim_engine_halt (sd, cpu, NULL, riscv_cpu->pc, sim_signalled,
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SIM_SIGILL);
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break;
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}
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imm = EXTRACT_CITYPE_IMM (iw);
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TRACE_INSN (cpu, "c.slli %s, %" PRIiTW "; // %s = %s << %#" PRIxTW,
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rd_name, imm, rd_name, rd_name, imm);
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store_rd (cpu, rd, riscv_cpu->regs[rd] << imm);
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break;
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case MATCH_C_SRLI | MATCH_C_SRLI64:
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if (op->mask == MASK_C_SRLI64)
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{
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/* Reserved for custom use. */
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TRACE_INSN (cpu, "UNHANDLED INSN: %s", op->name);
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sim_engine_halt (sd, cpu, NULL, riscv_cpu->pc, sim_signalled,
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SIM_SIGILL);
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break;
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}
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imm = EXTRACT_CITYPE_IMM (iw);
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TRACE_INSN (cpu, "c.srli %s, %" PRIiTW "; // %s = %s >> %#" PRIxTW,
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rs1_c_name, imm, rs1_c_name, rs1_c_name, imm);
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if (RISCV_XLEN (cpu) == 32)
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store_rd (cpu, rs1_c,
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EXTEND32 ((uint32_t) riscv_cpu->regs[rs1_c] >> imm));
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else
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store_rd (cpu, rs1_c, riscv_cpu->regs[rs1_c] >> imm);
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break;
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case MATCH_C_SRAI | MATCH_C_SRAI64:
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if (op->mask == MASK_C_SRAI64)
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{
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/* Reserved for custom use. */
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TRACE_INSN (cpu, "UNHANDLED INSN: %s", op->name);
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sim_engine_halt (sd, cpu, NULL, riscv_cpu->pc, sim_signalled,
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SIM_SIGILL);
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break;
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}
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imm = EXTRACT_CITYPE_IMM (iw);
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TRACE_INSN (cpu, "c.srai %s, %" PRIiTW "; // %s = %s >> %#" PRIxTW,
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rs1_c_name, imm, rs1_c_name, rs1_c_name, imm);
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if (RISCV_XLEN (cpu) == 32)
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{
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if (imm > 0x1f)
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sim_engine_halt (sd, cpu, NULL, riscv_cpu->pc, sim_signalled,
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SIM_SIGILL);
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tmp = ashiftrt (riscv_cpu->regs[rs1_c], imm);
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}
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else
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tmp = ashiftrt64 (riscv_cpu->regs[rs1_c], imm);
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store_rd (cpu, rd, tmp);
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break;
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case MATCH_C_ANDI:
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imm = EXTRACT_CITYPE_IMM (iw);
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TRACE_INSN (cpu, "c.andi %s, %" PRIiTW "; // %s = %s & %#" PRIxTW,
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rs1_c_name, imm, rs1_c_name, rs1_c_name, imm);
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store_rd (cpu, rs1_c, riscv_cpu->regs[rs1_c] & imm);
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break;
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case MATCH_C_ADDW:
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TRACE_INSN (cpu, "c.addw %s, %s; // %s = %s + %s",
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rs1_c_name, rs2_c_name, rs1_c_name, rs1_c_name, rs2_c_name);
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RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
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store_rd (cpu, rs1_c,
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EXTEND32 (riscv_cpu->regs[rs1_c] + riscv_cpu->regs[rs2_c]));
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break;
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case MATCH_C_SUBW:
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TRACE_INSN (cpu, "c.subw %s, %s; // %s = %s - %s",
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rs1_c_name, rs2_c_name, rs1_c_name, rs1_c_name, rs2_c_name);
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RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
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store_rd (cpu, rs1_c,
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EXTEND32 (riscv_cpu->regs[rs1_c] - riscv_cpu->regs[rs2_c]));
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break;
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case MATCH_C_LDSP:
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imm = EXTRACT_CITYPE_LDSP_IMM (iw);
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TRACE_INSN (cpu, "c.ldsp %s, %" PRIiTW "(sp);",
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rd_name, imm);
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RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
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store_rd (cpu, rd,
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sim_core_read_unaligned_8 (cpu, riscv_cpu->pc, read_map,
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riscv_cpu->regs[SIM_RISCV_SP_REGNUM]
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+ imm));
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break;
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case MATCH_C_LD:
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imm = EXTRACT_CLTYPE_LD_IMM (iw);
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TRACE_INSN (cpu, "c.ld %s, %" PRIiTW "(%s);",
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rs1_c_name, imm, rs2_c_name);
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RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
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store_rd (cpu, rs2_c,
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sim_core_read_unaligned_8 (cpu, riscv_cpu->pc, read_map,
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riscv_cpu->regs[rs1_c] + imm));
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break;
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case MATCH_C_SDSP:
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imm = EXTRACT_CSSTYPE_SDSP_IMM (iw);
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TRACE_INSN (cpu, "c.sdsp %s, %" PRIiTW "(sp);",
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rs2_name, imm);
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RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
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sim_core_write_unaligned_8 (cpu, riscv_cpu->pc, write_map,
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riscv_cpu->regs[SIM_RISCV_SP_REGNUM] + imm,
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riscv_cpu->regs[rs2]);
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break;
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case MATCH_C_SD:
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imm = EXTRACT_CLTYPE_LD_IMM (iw);
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TRACE_INSN (cpu, "c.sd %s, %" PRIiTW "(%s);",
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rs2_c_name, imm, rs1_c_name);
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RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
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sim_core_write_unaligned_8 (cpu, riscv_cpu->pc, write_map,
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riscv_cpu->regs[rs1_c] + imm,
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riscv_cpu->regs[rs2_c]);
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break;
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default:
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TRACE_INSN (cpu, "UNHANDLED INSN: %s", op->name);
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sim_engine_halt (sd, cpu, NULL, riscv_cpu->pc, sim_signalled,
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SIM_SIGILL);
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}
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return pc;
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}
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static sim_cia
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execute_one (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
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{
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@ -988,6 +1303,16 @@ execute_one (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
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{
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case INSN_CLASS_A:
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return execute_a (cpu, iw, op);
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case INSN_CLASS_C:
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/* Check whether model with C extension is selected. */
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if (riscv_cpu->csr.misa & 4)
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return execute_c (cpu, iw, op);
|
||||
else
|
||||
{
|
||||
TRACE_INSN (cpu, "UNHANDLED EXTENSION: %d", op->insn_class);
|
||||
sim_engine_halt (sd, cpu, NULL, riscv_cpu->pc, sim_signalled,
|
||||
SIM_SIGILL);
|
||||
}
|
||||
case INSN_CLASS_I:
|
||||
return execute_i (cpu, iw, op);
|
||||
case INSN_CLASS_M:
|
||||
@ -1018,17 +1343,17 @@ void step_once (SIM_CPU *cpu)
|
||||
|
||||
iw = sim_core_read_aligned_2 (cpu, pc, exec_map, pc);
|
||||
|
||||
/* Reject non-32-bit opcodes first. */
|
||||
len = riscv_insn_length (iw);
|
||||
if (len != 4)
|
||||
if (len != 4 && len != 2)
|
||||
{
|
||||
sim_io_printf (sd, "sim: bad insn len %#x @ %#" PRIxTA ": %#" PRIxTW "\n",
|
||||
len, pc, iw);
|
||||
sim_engine_halt (sd, cpu, NULL, pc, sim_signalled, SIM_SIGILL);
|
||||
}
|
||||
|
||||
iw |= ((unsigned_word) sim_core_read_aligned_2 (
|
||||
cpu, pc, exec_map, pc + 2) << 16);
|
||||
if (len == 4)
|
||||
iw |= ((unsigned_word) sim_core_read_aligned_2
|
||||
(cpu, pc, exec_map, pc + 2) << 16);
|
||||
|
||||
TRACE_CORE (cpu, "0x%08" PRIxTW, iw);
|
||||
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
sim_init
|
||||
|
||||
# all machines
|
||||
set all_machs "riscv"
|
||||
set all_machs "riscv32 riscv64"
|
||||
|
||||
foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.s]] {
|
||||
# If we're only testing specific files and this isn't one of them, skip it.
|
||||
|
||||
95
sim/testsuite/riscv/c-ext.s
Normal file
95
sim/testsuite/riscv/c-ext.s
Normal file
@ -0,0 +1,95 @@
|
||||
# Basic Tests for C extension.
|
||||
# mach: riscv32 riscv64
|
||||
# sim(riscv32): --model RV32IC
|
||||
# sim(riscv64): --model RV64IC
|
||||
# ld(riscv32): -m elf32lriscv
|
||||
# ld(riscv64): -m elf64lriscv
|
||||
# as(riscv32): -march=rv32ic
|
||||
# as(riscv64): -march=rv64ic
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
.data
|
||||
.align 4
|
||||
_data:
|
||||
.word 1234
|
||||
.word 0
|
||||
|
||||
start
|
||||
la a0, _data
|
||||
|
||||
# Test load-store instructions.
|
||||
c.lw a1,0(a0)
|
||||
c.sw a1,4(a0)
|
||||
c.lw a2,4(a0)
|
||||
|
||||
li a5,1234
|
||||
bne a1,a5,test_fail
|
||||
bne a2,a5,test_fail
|
||||
|
||||
# Test basic arithmetic.
|
||||
c.li a0,0
|
||||
c.li a1,1
|
||||
c.addi a0,1
|
||||
c.addi a0,-1
|
||||
c.add a0,a1
|
||||
c.sub a0,a1
|
||||
|
||||
li a5,1
|
||||
bne a0,x0,test_fail
|
||||
bne a1,a5,test_fail
|
||||
|
||||
# Test logical operations.
|
||||
c.li a0,7
|
||||
c.li a1,7
|
||||
c.li a2,4
|
||||
c.li a3,3
|
||||
c.li a4,3
|
||||
c.andi a0,3
|
||||
c.and a1,a0
|
||||
c.or a2,a3
|
||||
c.xor a4,a4
|
||||
|
||||
li a5,3
|
||||
bne a0,a5,test_fail
|
||||
bne a1,a5,test_fail
|
||||
bne a4,x0,test_fail
|
||||
li a5,7
|
||||
bne a2,a5,test_fail
|
||||
|
||||
# Test shift operations.
|
||||
c.li a0,4
|
||||
c.li a1,4
|
||||
c.slli a0,1
|
||||
c.srli a1,1
|
||||
|
||||
li a5,8
|
||||
bne a0,a5,test_fail
|
||||
li a5,2
|
||||
bne a1,a5,test_fail
|
||||
|
||||
# Test jump instruction.
|
||||
c.j 1f
|
||||
|
||||
j test_fail
|
||||
1:
|
||||
la a0,2f
|
||||
|
||||
# Test jump register instruction.
|
||||
c.jr a0
|
||||
|
||||
j test_fail
|
||||
|
||||
2:
|
||||
# Test branch instruction.
|
||||
c.li a0,1
|
||||
c.beqz a0,test_fail
|
||||
c.li a0,0
|
||||
c.bnez a0,test_fail
|
||||
|
||||
test_pass:
|
||||
pass
|
||||
fail
|
||||
|
||||
test_fail:
|
||||
fail
|
||||
@ -1,5 +1,5 @@
|
||||
# Basic jalr tests.
|
||||
# mach: riscv
|
||||
# mach: riscv32 riscv64
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
# Check that the RV32M instructions run without any faults.
|
||||
# mach: riscv
|
||||
# mach: riscv32 riscv64
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
# check that the sim doesn't die immediately.
|
||||
# mach: riscv
|
||||
# mach: riscv32 riscv64
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user