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x86: drop some stray/bogus DefaultSize
Insns permitting only GPR operands (and hence implicit sizing when there's no suffix) don't ever have their DefaultSize attribute inspected, so it shouldn't be there in the first place. Additionally XBEGIN is like JMP, not CALL, and hence shouldn't be converted to 32-bit operand size in .code16gcc mode. While the same is true for SYSRET, it permitting more than one suffix makes it FLDENV- like, and hence rather than dropping the attribute, for now add it to the exclusion list to avoid it getting an operand size prefix emitted in .code16gcc mode. (This will be dealt with later, perhaps together with FLDENV and friends.)
This commit is contained in:
Jan Beulich
parent
5085593976
commit
3036c89919
@ -1,3 +1,10 @@
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2019-12-04 Jan Beulich <jbeulich@suse.com>
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* config/tc-i386.c (process_suffix): Exclude SYSRET alongside
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FLDENV et al.
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* testsuite/gas/i386/general.s: Expand .code16gcc set of insns.
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* testsuite/gas/i386/general.l: Adjust expectations.
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2019-11-22 Andrew Burgess <andrew.burgess@embecosm.com>
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* as.c (flag_dwarf_cie_version): Change initial value to -1, and
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@ -6311,7 +6311,9 @@ process_suffix (void)
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else if (i.tm.opcode_modifier.defaultsize
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&& !i.suffix
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/* exclude fldenv/frstor/fsave/fstenv */
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&& i.tm.opcode_modifier.no_ssuf)
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&& i.tm.opcode_modifier.no_ssuf
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/* exclude sysret */
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&& i.tm.base_opcode != 0x0f07)
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{
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if (stackop_size == LONG_MNEM_SUFFIX
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&& i.tm.base_opcode == 0xcf)
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@ -31,6 +31,7 @@
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.*:143: Warning:.*
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.*:144: Warning:.*
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.*:178: Warning:.*
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.*:224: Warning:.*
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1 .psize 0
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2 .text
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3 #test jumps and calls
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@ -283,11 +284,49 @@
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217 022a 0FB6C8 movzb %al,%ecx
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218
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219 .code16gcc
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220 # Use 16-bit layout by default for fldenv.
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221 022d 67D920 fldenv \(%eax\)
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222 0230 67D920 fldenvs \(%eax\)
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223 0233 6766D920 fldenvl \(%eax\)
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224
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225 # Force a good alignment.
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226 0237 00000000 00000000 .p2align 4,0
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226 00
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[ ]*[1-9][0-9]*[ ]*# Except for IRET use 32-bit implicit stack accesses by default.
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[ ]*[1-9][0-9]*[ ]+[0-9a-f]*[ ]+66E8FAFF FFFF[ ]+call \.
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[ ]*[1-9][0-9]*[ ]+[0-9a-f]*[ ]+66FF17[ ]+call \*\(%bx\)
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[ ]*[1-9][0-9]*[ ]+[0-9a-f]*[ ]+66C80000 00[ ]+enter \$0,\$0
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[ ]*[1-9][0-9]*[ ]+[0-9a-f]*[ ]+CF[ ]+iret
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.*Warning:.*16-bit.*iret.*
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[ ]*[1-9][0-9]*[ ]+[0-9a-f]*[ ]+66FF1F[ ]+lcall \*\(%bx\)
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[ ]*[1-9][0-9]*[ ]+[0-9a-f]*[ ]+669A0000 00000000[ ]+lcall \$0,\$0
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[ ]*[1-9][0-9]*[ ]+[0-9a-f]*[ ]+66C9[ ]+leave
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[ ]*[1-9][0-9]*[ ]+[0-9a-f]*[ ]+66CB[ ]+lret
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[ ]*[1-9][0-9]*[ ]+[0-9a-f]*[ ]+66CA0000[ ]+lret \$0
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[ ]*[1-9][0-9]*[ ]+[0-9a-f]*[ ]+666A00[ ]+push \$0
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[ ]*[1-9][0-9]*[ ]+[0-9a-f]*[ ]+66683412 0000[ ]+push \$0x1234
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[ ]*[1-9][0-9]*[ ]+[0-9a-f]*[ ]+66FF37[ ]+push \(%bx\)
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[ ]*[1-9][0-9]*[ ]+[0-9a-f]*[ ]+6660[ ]+pusha
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[ ]*[1-9][0-9]*[ ]+[0-9a-f]*[ ]+669C[ ]+pushf
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[ ]*[1-9][0-9]*[ ]+[0-9a-f]*[ ]+668F07[ ]+pop \(%bx\)
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[ ]*[1-9][0-9]*[ ]+[0-9a-f]*[ ]+6661[ ]+popa
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[ ]*[1-9][0-9]*[ ]+[0-9a-f]*[ ]+669D[ ]+popf
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[ ]*[1-9][0-9]*[ ]+[0-9a-f]*[ ]+66C3[ ]+ret
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[ ]*[1-9][0-9]*[ ]+[0-9a-f]*[ ]+66C20000[ ]+ret \$0
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[ ]*[1-9][0-9]*[ ]*
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[ ]*[1-9][0-9]*[ ]*# However use 16-bit branches not accessing the stack by default.
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[ ]*[1-9][0-9]*[ ]+[0-9a-f]*[ ]+77FE[ ]+ja \.
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[ ]*[1-9][0-9]*[ ]+[0-9a-f]*[ ]+0F873012[ ]+ja \.\+0x1234
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[ ]*[1-9][0-9]*[ ]+[0-9a-f]*[ ]+E3FE[ ]+jcxz \.
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[ ]*[1-9][0-9]*[ ]+[0-9a-f]*[ ]+EBFE[ ]+jmp \.
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[ ]*[1-9][0-9]*[ ]+[0-9a-f]*[ ]+E93112[ ]+jmp \.\+0x1234
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[ ]*[1-9][0-9]*[ ]+[0-9a-f]*[ ]+FF27[ ]+jmp \*\(%bx\)
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[ ]*[1-9][0-9]*[ ]+[0-9a-f]*[ ]+FF2F[ ]+ljmp \*\(%bx\)
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[ ]*[1-9][0-9]*[ ]+[0-9a-f]*[ ]+EA000000 00[ ]+ljmp \$0,\$0
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[ ]*[1-9][0-9]*[ ]+[0-9a-f]*[ ]+E2FE[ ]+loop \.
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[ ]*[1-9][0-9]*[ ]+[0-9a-f]*[ ]+0F05[ ]+syscall
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[ ]*[1-9][0-9]*[ ]+[0-9a-f]*[ ]+0F34[ ]+sysenter
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[ ]*[1-9][0-9]*[ ]+[0-9a-f]*[ ]+0F35[ ]+sysexit
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[ ]*[1-9][0-9]*[ ]+[0-9a-f]*[ ]+0F07[ ]+sysret
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[ ]*[1-9][0-9]*[ ]+[0-9a-f]*[ ]+C7F8FCFF[ ]+xbegin \.
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[ ]*[1-9][0-9]*[ ]*
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[ ]*[1-9][0-9]*[ ]*# Use 16-bit layout by default for fldenv.
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[ ]*[1-9][0-9]*[ ]+[0-9a-f]*[ ]+67D920[ ]+fldenv \(%eax\)
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[ ]*[1-9][0-9]*[ ]+[0-9a-f]*[ ]+67D920[ ]+fldenvs \(%eax\)
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[ ]*[1-9][0-9]*[ ]+[0-9a-f]*[ ]+6766D920[ ]+fldenvl \(%eax\)
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[ ]*[1-9][0-9]*[ ]*
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[ ]*[1-9][0-9]*[ ]*# Force a good alignment.
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[ ]*[1-9][0-9]*[ ]+[0-9a-f ]+\.p2align 4,0
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#pass
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@ -217,6 +217,43 @@
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movzb %al,%ecx
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.code16gcc
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# Except for IRET use 32-bit implicit stack accesses by default.
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call .
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call *(%bx)
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enter $0,$0
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iret
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lcall *(%bx)
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lcall $0,$0
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leave
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lret
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lret $0
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push $0
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push $0x1234
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push (%bx)
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pusha
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pushf
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pop (%bx)
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popa
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popf
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ret
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ret $0
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# However use 16-bit branches not accessing the stack by default.
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ja .
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ja .+0x1234
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jcxz .
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jmp .
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jmp .+0x1234
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jmp *(%bx)
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ljmp *(%bx)
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ljmp $0,$0
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loop .
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syscall
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sysenter
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sysexit
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sysret
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xbegin .
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# Use 16-bit layout by default for fldenv.
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fldenv (%eax)
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fldenvs (%eax)
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@ -1,3 +1,10 @@
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2019-12-04 Jan Beulich <jbeulich@suse.com>
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* i386-opc.tbl (push, pop): Drop DefaultSize from GPR-only
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forms.
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(xbegin): Drop DefaultSize.
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* i386-tbl.h: Re-generate.
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2019-11-22 Mihail Ionescu <mihail.ionescu@arm.com>
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* opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes):
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@ -151,13 +151,13 @@ movzx, 2, 0xfb6, None, 2, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf
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movzx, 2, 0xfb7, None, 2, Cpu386, Modrm|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { Reg16|Word|BaseIndex, Reg32|Reg64 }
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// Push instructions.
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push, 1, 0x50, None, 1, CpuNo64, ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32 }
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push, 1, 0x50, None, 1, CpuNo64, ShortForm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32 }
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push, 1, 0xff, 0x6, 1, CpuNo64, Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Word|Dword|Unspecified|BaseIndex }
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push, 1, 0x6a, None, 1, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8S }
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push, 1, 0x68, None, 1, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm16|Imm32 }
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push, 1, 0x6, None, 1, CpuNo64, ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { SReg }
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// In 64bit mode, the operand size is implicitly 64bit.
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push, 1, 0x50, None, 1, Cpu64, ShortForm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Reg16|Reg64 }
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push, 1, 0x50, None, 1, Cpu64, ShortForm|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Reg16|Reg64 }
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push, 1, 0xff, 0x6, 1, Cpu64, Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Reg16|Reg64|Word|Qword|Unspecified|BaseIndex }
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push, 1, 0x6a, None, 1, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Imm8S }
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push, 1, 0x68, None, 1, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Imm16|Imm32S }
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@ -166,11 +166,11 @@ push, 1, 0xfa0, None, 2, Cpu64, ShortForm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No
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pusha, 0, 0x60, None, 1, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
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// Pop instructions.
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pop, 1, 0x58, None, 1, CpuNo64, ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32 }
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pop, 1, 0x58, None, 1, CpuNo64, ShortForm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32 }
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pop, 1, 0x8f, 0x0, 1, CpuNo64, Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Word|Dword|Unspecified|BaseIndex }
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pop, 1, 0x7, None, 1, CpuNo64, ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { SReg }
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// In 64bit mode, the operand size is implicitly 64bit.
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pop, 1, 0x58, None, 1, Cpu64, ShortForm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Reg16|Reg64 }
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pop, 1, 0x58, None, 1, Cpu64, ShortForm|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Reg16|Reg64 }
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pop, 1, 0x8f, 0x0, 1, Cpu64, Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Reg16|Reg64|Word|Qword|Unspecified|BaseIndex }
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pop, 1, 0xfa1, None, 2, Cpu64, ShortForm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { SReg }
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@ -2550,7 +2550,7 @@ xrelease, 0, 0xf3, None, 1, CpuHLE, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_l
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// RTM instructions
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xabort, 1, 0xc6f8, None, 2, CpuRTM, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8 }
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xbegin, 1, 0xc7f8, None, 2, CpuRTM, JumpDword|DefaultSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Disp16|Disp32 }
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xbegin, 1, 0xc7f8, None, 2, CpuRTM, JumpDword|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Disp16|Disp32 }
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xend, 0, 0xf01d5, None, 3, CpuRTM, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
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xtest, 0, 0xf01d6, None, 3, CpuHLE|CpuRTM, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
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@ -547,7 +547,7 @@ const insn_template i386_optab[] =
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } },
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{ 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 1, 1, 1, 0,
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{ 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
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{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0,
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@ -607,7 +607,7 @@ const insn_template i386_optab[] =
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } },
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{ 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 1, 0, 1, 0,
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{ 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 1, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
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{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1,
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@ -679,7 +679,7 @@ const insn_template i386_optab[] =
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } },
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{ 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 1, 1, 1, 0,
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{ 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
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{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0,
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@ -715,7 +715,7 @@ const insn_template i386_optab[] =
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } },
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{ 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 1, 0, 1, 0,
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{ 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 1, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
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{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1,
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@ -42835,7 +42835,7 @@ const insn_template i386_optab[] =
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0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
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{ 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0,
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{ 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
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{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0,
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