mirror of
https://sourceware.org/git/binutils-gdb.git
synced 2025-01-18 12:24:38 +08:00
gas: further adjust file/line handling for .irp and alike
Commit 7992631e8c ("gas/Dwarf: improve debug info generation from .irp
and alike blocks"), while dealing okay with actual assembly source files
not using .file/.line and alike outside but not inside of .irp et al,
has undue effects when the logical file/line pair was already
overridden: Line numbers would continuously increment upon every
iteration, thus potentially getting far off. Furthermore it left it to
the user to actually insert .file/.line inside such constructs. Note
though that before aforementioned change things weren't pretty either:
Diagnostics (and debug info) would be associated with the directive
terminating the iteration construct, rather than with the actual lines.
Handle this automatically by simply latching the present line and then
re-instating coordinates first thing on every iteration; note that the
file can't change from what was previously pushed on the scrubber's
state stack, and hence can be taken from there by using a new flavor of
.linefile (which is far better memory-footprint-wise than recording the
full path in the inserted directive). (This then leaves undisturbed any
file/line control occurring in the body of the construct, as these will
only be seen and processed afterwards.)
This commit is contained in:
Jan Beulich
parent
1a42a9fe4e
commit
2ee1792bec
@ -440,7 +440,8 @@ bump_line_counters (void)
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number. If it is -2, we decrement the logical line number (this is
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to support the .appfile pseudo-op inserted into the stream by
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do_scrub_chars).
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If the fname is NULL, we don't change the current logical file name.
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If fname is NULL, we don't change the current logical file name, unless
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bit 3 of flags is set.
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Returns nonzero if the filename actually changes. */
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int
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@ -460,6 +461,14 @@ new_logical_line_flags (const char *fname, /* DON'T destroy it! We point to it!
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case 1 << 2:
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/* FIXME: we could check that include nesting is correct. */
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break;
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case 1 << 3:
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if (line_number < 0 || fname != NULL || next_saved_file == NULL)
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abort ();
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if (next_saved_file->logical_input_file)
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fname = next_saved_file->logical_input_file;
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else
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fname = next_saved_file->physical_input_file;
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break;
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default:
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abort ();
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}
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15
gas/macro.c
15
gas/macro.c
@ -126,6 +126,21 @@ buffer_and_nest (const char *from, const char *to, sb *ptr,
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else
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from_len = strlen (from);
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/* Except for macros record the present source position, such that
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diagnostics and debug info will be properly associated with the
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respective original lines, rather than with the line of the ending
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directive (TO). */
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if (from == NULL || strcasecmp (from, "MACRO") != 0)
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{
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unsigned int line;
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char *linefile;
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as_where (&line);
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linefile = xasprintf ("\t.linefile %u .\n", line);
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sb_add_buffer (ptr, linefile, strlen (linefile));
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xfree (linefile);
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}
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while (more)
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{
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/* Try to find the first pseudo op on the line. */
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13
gas/read.c
13
gas/read.c
@ -2067,7 +2067,7 @@ void
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s_app_line (int appline)
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{
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char *file = NULL;
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int linenum;
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int linenum, flags = 0;
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/* The given number is that of the next line. */
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if (appline)
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@ -2092,7 +2092,6 @@ s_app_line (int appline)
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linenum);
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else
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{
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int flags = 0;
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int length = 0;
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if (!appline)
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@ -2101,6 +2100,12 @@ s_app_line (int appline)
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if (*input_line_pointer == '"')
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file = demand_copy_string (&length);
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else if (*input_line_pointer == '.')
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{
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/* buffer_and_nest() may insert this form. */
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++input_line_pointer;
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flags = 1 << 3;
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}
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if (file)
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{
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@ -2147,7 +2152,7 @@ s_app_line (int appline)
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}
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}
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if (appline || file)
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if (appline || file || flags)
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{
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linenum--;
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new_logical_line_flags (file, linenum, flags);
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@ -2157,7 +2162,7 @@ s_app_line (int appline)
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#endif
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}
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}
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if (appline || file)
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if (appline || file || flags)
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demand_empty_rest_of_line ();
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else
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ignore_rest_of_line ();
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@ -2,15 +2,15 @@
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[^:]+:18: Error: operand mismatch -- `ldaprb x0,\[x1\]'
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[^:]+:19: Error: operand mismatch -- `ldaprh x0,\[x1\]'
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[^:]+:20: Error: the optional immediate offset can only be 0 at operand 2 -- `ldapr x0,\[x1,#8\]'
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[^:]+:24: Error: 64-bit integer or SP register expected at operand 2 -- `ldaprb w1,\[xz\]'
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[^:]+:24: Error: the optional immediate offset can only be 0 at operand 2 -- `ldaprb w1,\[x7,#8\]'
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[^:]+:24: Error: invalid addressing mode at operand 2 -- `ldaprb w1,\[x7,#8\]!'
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[^:]+:24: Error: invalid addressing mode at operand 2 -- `ldaprb w1,\[x7\],#8'
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[^:]+:24: Error: 64-bit integer or SP register expected at operand 2 -- `ldaprh w1,\[xz\]'
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[^:]+:24: Error: the optional immediate offset can only be 0 at operand 2 -- `ldaprh w1,\[x7,#8\]'
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[^:]+:24: Error: invalid addressing mode at operand 2 -- `ldaprh w1,\[x7,#8\]!'
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[^:]+:24: Error: invalid addressing mode at operand 2 -- `ldaprh w1,\[x7\],#8'
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[^:]+:24: Error: 64-bit integer or SP register expected at operand 2 -- `ldapr w1,\[xz\]'
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[^:]+:24: Error: the optional immediate offset can only be 0 at operand 2 -- `ldapr w1,\[x7,#8\]'
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[^:]+:24: Error: invalid addressing mode at operand 2 -- `ldapr w1,\[x7,#8\]!'
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[^:]+:24: Error: invalid addressing mode at operand 2 -- `ldapr w1,\[x7\],#8'
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[^:]+:23: Error: 64-bit integer or SP register expected at operand 2 -- `ldaprb w1,\[xz\]'
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[^:]+:23: Error: the optional immediate offset can only be 0 at operand 2 -- `ldaprb w1,\[x7,#8\]'
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[^:]+:23: Error: invalid addressing mode at operand 2 -- `ldaprb w1,\[x7,#8\]!'
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[^:]+:23: Error: invalid addressing mode at operand 2 -- `ldaprb w1,\[x7\],#8'
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[^:]+:23: Error: 64-bit integer or SP register expected at operand 2 -- `ldaprh w1,\[xz\]'
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[^:]+:23: Error: the optional immediate offset can only be 0 at operand 2 -- `ldaprh w1,\[x7,#8\]'
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[^:]+:23: Error: invalid addressing mode at operand 2 -- `ldaprh w1,\[x7,#8\]!'
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[^:]+:23: Error: invalid addressing mode at operand 2 -- `ldaprh w1,\[x7\],#8'
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[^:]+:23: Error: 64-bit integer or SP register expected at operand 2 -- `ldapr w1,\[xz\]'
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[^:]+:23: Error: the optional immediate offset can only be 0 at operand 2 -- `ldapr w1,\[x7,#8\]'
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[^:]+:23: Error: invalid addressing mode at operand 2 -- `ldapr w1,\[x7,#8\]!'
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[^:]+:23: Error: invalid addressing mode at operand 2 -- `ldapr w1,\[x7\],#8'
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@ -167,118 +167,118 @@
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[^:]*:235: Error: .*`msr SPSel,#2'
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[^:]*:237: Error: .*`tbl v0.16b,{v1.16b,v3.16b,v5.16b},v2.16b'
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[^:]*:238: Error: .*`tbx v0.8b,{v1.16b,v3.16b,v5.16b,v7.16b},v2.8b'
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[^:]*:264: Error: .*`ld2 {v0.8b,v2.8b},\[x0\],#16'
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[^:]*:264: Error: .*`ld2 {v0.8b,v1.8b,v2.8b,v3.8b},\[x0\],#32'
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[^:]*:264: Error: .*`ld2 {v0.8b,v2.8b},\[x0\],x7'
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[^:]*:264: Error: .*`ld2 {v0.8b,v1.8b,v2.8b,v3.8b},\[x0\],x7'
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[^:]*:264: Error: .*`ld2 {v0.4h,v2.4h},\[x0\],#16'
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[^:]*:264: Error: .*`ld2 {v0.4h,v1.4h,v2.4h,v3.4h},\[x0\],#32'
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[^:]*:264: Error: .*`ld2 {v0.4h,v2.4h},\[x0\],x7'
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[^:]*:264: Error: .*`ld2 {v0.4h,v1.4h,v2.4h,v3.4h},\[x0\],x7'
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[^:]*:264: Error: .*`ld2 {v0.2s,v2.2s},\[x0\],#16'
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[^:]*:264: Error: .*`ld2 {v0.2s,v1.2s,v2.2s,v3.2s},\[x0\],#32'
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[^:]*:264: Error: .*`ld2 {v0.2s,v2.2s},\[x0\],x7'
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[^:]*:264: Error: .*`ld2 {v0.2s,v1.2s,v2.2s,v3.2s},\[x0\],x7'
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[^:]*:264: Error: .*`st2 {v0.8b,v2.8b},\[x0\],#16'
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[^:]*:264: Error: .*`st2 {v0.8b,v1.8b,v2.8b,v3.8b},\[x0\],#32'
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[^:]*:264: Error: .*`st2 {v0.8b,v2.8b},\[x0\],x7'
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[^:]*:264: Error: .*`st2 {v0.8b,v1.8b,v2.8b,v3.8b},\[x0\],x7'
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[^:]*:264: Error: .*`st2 {v0.4h,v2.4h},\[x0\],#16'
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[^:]*:264: Error: .*`st2 {v0.4h,v1.4h,v2.4h,v3.4h},\[x0\],#32'
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[^:]*:264: Error: .*`st2 {v0.4h,v2.4h},\[x0\],x7'
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[^:]*:264: Error: .*`st2 {v0.4h,v1.4h,v2.4h,v3.4h},\[x0\],x7'
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[^:]*:264: Error: .*`st2 {v0.2s,v2.2s},\[x0\],#16'
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[^:]*:264: Error: .*`st2 {v0.2s,v1.2s,v2.2s,v3.2s},\[x0\],#32'
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[^:]*:264: Error: .*`st2 {v0.2s,v2.2s},\[x0\],x7'
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[^:]*:264: Error: .*`st2 {v0.2s,v1.2s,v2.2s,v3.2s},\[x0\],x7'
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[^:]*:270: Error: .*`ld2 {v0.16b,v2.16b},\[x0\],#32'
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[^:]*:270: Error: .*`ld2 {v0.16b,v1.16b,v2.16b,v3.16b},\[x0\],#64'
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[^:]*:270: Error: .*`ld2 {v0.16b,v2.16b},\[x0\],x7'
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[^:]*:270: Error: .*`ld2 {v0.16b,v1.16b,v2.16b,v3.16b},\[x0\],x7'
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[^:]*:270: Error: .*`ld2 {v0.8h,v2.8h},\[x0\],#32'
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[^:]*:270: Error: .*`ld2 {v0.8h,v1.8h,v2.8h,v3.8h},\[x0\],#64'
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[^:]*:270: Error: .*`ld2 {v0.8h,v2.8h},\[x0\],x7'
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[^:]*:270: Error: .*`ld2 {v0.8h,v1.8h,v2.8h,v3.8h},\[x0\],x7'
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[^:]*:270: Error: .*`ld2 {v0.4s,v2.4s},\[x0\],#32'
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[^:]*:270: Error: .*`ld2 {v0.4s,v1.4s,v2.4s,v3.4s},\[x0\],#64'
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[^:]*:270: Error: .*`ld2 {v0.4s,v2.4s},\[x0\],x7'
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[^:]*:270: Error: .*`ld2 {v0.4s,v1.4s,v2.4s,v3.4s},\[x0\],x7'
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[^:]*:270: Error: .*`ld2 {v0.2d,v2.2d},\[x0\],#32'
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[^:]*:270: Error: .*`ld2 {v0.2d,v1.2d,v2.2d,v3.2d},\[x0\],#64'
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[^:]*:270: Error: .*`ld2 {v0.2d,v2.2d},\[x0\],x7'
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[^:]*:270: Error: .*`ld2 {v0.2d,v1.2d,v2.2d,v3.2d},\[x0\],x7'
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[^:]*:270: Error: .*`st2 {v0.16b,v2.16b},\[x0\],#32'
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[^:]*:270: Error: .*`st2 {v0.16b,v1.16b,v2.16b,v3.16b},\[x0\],#64'
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[^:]*:270: Error: .*`st2 {v0.16b,v2.16b},\[x0\],x7'
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[^:]*:270: Error: .*`st2 {v0.16b,v1.16b,v2.16b,v3.16b},\[x0\],x7'
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[^:]*:270: Error: .*`st2 {v0.8h,v2.8h},\[x0\],#32'
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[^:]*:270: Error: .*`st2 {v0.8h,v1.8h,v2.8h,v3.8h},\[x0\],#64'
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[^:]*:270: Error: .*`st2 {v0.8h,v2.8h},\[x0\],x7'
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[^:]*:270: Error: .*`st2 {v0.8h,v1.8h,v2.8h,v3.8h},\[x0\],x7'
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[^:]*:270: Error: .*`st2 {v0.4s,v2.4s},\[x0\],#32'
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[^:]*:270: Error: .*`st2 {v0.4s,v1.4s,v2.4s,v3.4s},\[x0\],#64'
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[^:]*:270: Error: .*`st2 {v0.4s,v2.4s},\[x0\],x7'
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[^:]*:270: Error: .*`st2 {v0.4s,v1.4s,v2.4s,v3.4s},\[x0\],x7'
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[^:]*:270: Error: .*`st2 {v0.2d,v2.2d},\[x0\],#32'
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[^:]*:270: Error: .*`st2 {v0.2d,v1.2d,v2.2d,v3.2d},\[x0\],#64'
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[^:]*:270: Error: .*`st2 {v0.2d,v2.2d},\[x0\],x7'
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[^:]*:270: Error: .*`st2 {v0.2d,v1.2d,v2.2d,v3.2d},\[x0\],x7'
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[^:]*:290: Error: .*`ld3 {v0.8b,v2.8b,v4.8b},\[x0\],#24'
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[^:]*:290: Error: .*`ld4 {v0.8b,v2.8b,v4.8b,v6.8b},\[x0\],#32'
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[^:]*:290: Error: .*`ld3 {v0.8b,v2.8b,v4.8b},\[x0\],x7'
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[^:]*:290: Error: .*`ld4 {v0.8b,v2.8b,v4.8b,v6.8b},\[x0\],x7'
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[^:]*:290: Error: .*`ld3 {v0.4h,v2.4h,v4.4h},\[x0\],#24'
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[^:]*:290: Error: .*`ld4 {v0.4h,v2.4h,v4.4h,v6.4h},\[x0\],#32'
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[^:]*:290: Error: .*`ld3 {v0.4h,v2.4h,v4.4h},\[x0\],x7'
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[^:]*:290: Error: .*`ld4 {v0.4h,v2.4h,v4.4h,v6.4h},\[x0\],x7'
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[^:]*:290: Error: .*`ld3 {v0.2s,v2.2s,v4.2s},\[x0\],#24'
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[^:]*:290: Error: .*`ld4 {v0.2s,v2.2s,v4.2s,v6.2s},\[x0\],#32'
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[^:]*:290: Error: .*`ld3 {v0.2s,v2.2s,v4.2s},\[x0\],x7'
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[^:]*:290: Error: .*`ld4 {v0.2s,v2.2s,v4.2s,v6.2s},\[x0\],x7'
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[^:]*:290: Error: .*`st3 {v0.8b,v2.8b,v4.8b},\[x0\],#24'
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[^:]*:290: Error: .*`st4 {v0.8b,v2.8b,v4.8b,v6.8b},\[x0\],#32'
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[^:]*:290: Error: .*`st3 {v0.8b,v2.8b,v4.8b},\[x0\],x7'
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[^:]*:290: Error: .*`st4 {v0.8b,v2.8b,v4.8b,v6.8b},\[x0\],x7'
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[^:]*:290: Error: .*`st3 {v0.4h,v2.4h,v4.4h},\[x0\],#24'
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[^:]*:290: Error: .*`st4 {v0.4h,v2.4h,v4.4h,v6.4h},\[x0\],#32'
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[^:]*:290: Error: .*`st3 {v0.4h,v2.4h,v4.4h},\[x0\],x7'
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[^:]*:290: Error: .*`st4 {v0.4h,v2.4h,v4.4h,v6.4h},\[x0\],x7'
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[^:]*:290: Error: .*`st3 {v0.2s,v2.2s,v4.2s},\[x0\],#24'
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[^:]*:290: Error: .*`st4 {v0.2s,v2.2s,v4.2s,v6.2s},\[x0\],#32'
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[^:]*:290: Error: .*`st3 {v0.2s,v2.2s,v4.2s},\[x0\],x7'
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[^:]*:290: Error: .*`st4 {v0.2s,v2.2s,v4.2s,v6.2s},\[x0\],x7'
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[^:]*:296: Error: .*`ld3 {v0.16b,v2.16b,v4.16b},\[x0\],#48'
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[^:]*:296: Error: .*`ld4 {v0.16b,v2.16b,v4.16b,v6.16b},\[x0\],#64'
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[^:]*:296: Error: .*`ld3 {v0.16b,v2.16b,v4.16b},\[x0\],x7'
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[^:]*:296: Error: .*`ld4 {v0.16b,v2.16b,v4.16b,v6.16b},\[x0\],x7'
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[^:]*:296: Error: .*`ld3 {v0.8h,v2.8h,v4.8h},\[x0\],#48'
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[^:]*:296: Error: .*`ld4 {v0.8h,v2.8h,v4.8h,v6.8h},\[x0\],#64'
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[^:]*:296: Error: .*`ld3 {v0.8h,v2.8h,v4.8h},\[x0\],x7'
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[^:]*:296: Error: .*`ld4 {v0.8h,v2.8h,v4.8h,v6.8h},\[x0\],x7'
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[^:]*:296: Error: .*`ld3 {v0.4s,v2.4s,v4.4s},\[x0\],#48'
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[^:]*:296: Error: .*`ld4 {v0.4s,v2.4s,v4.4s,v6.4s},\[x0\],#64'
|
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[^:]*:296: Error: .*`ld3 {v0.4s,v2.4s,v4.4s},\[x0\],x7'
|
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[^:]*:296: Error: .*`ld4 {v0.4s,v2.4s,v4.4s,v6.4s},\[x0\],x7'
|
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[^:]*:296: Error: .*`ld3 {v0.2d,v2.2d,v4.2d},\[x0\],#48'
|
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[^:]*:296: Error: .*`ld4 {v0.2d,v2.2d,v4.2d,v6.2d},\[x0\],#64'
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[^:]*:296: Error: .*`ld3 {v0.2d,v2.2d,v4.2d},\[x0\],x7'
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[^:]*:296: Error: .*`ld4 {v0.2d,v2.2d,v4.2d,v6.2d},\[x0\],x7'
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[^:]*:296: Error: .*`st3 {v0.16b,v2.16b,v4.16b},\[x0\],#48'
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[^:]*:296: Error: .*`st4 {v0.16b,v2.16b,v4.16b,v6.16b},\[x0\],#64'
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[^:]*:296: Error: .*`st3 {v0.16b,v2.16b,v4.16b},\[x0\],x7'
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[^:]*:296: Error: .*`st4 {v0.16b,v2.16b,v4.16b,v6.16b},\[x0\],x7'
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[^:]*:296: Error: .*`st3 {v0.8h,v2.8h,v4.8h},\[x0\],#48'
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[^:]*:296: Error: .*`st4 {v0.8h,v2.8h,v4.8h,v6.8h},\[x0\],#64'
|
||||
[^:]*:296: Error: .*`st3 {v0.8h,v2.8h,v4.8h},\[x0\],x7'
|
||||
[^:]*:296: Error: .*`st4 {v0.8h,v2.8h,v4.8h,v6.8h},\[x0\],x7'
|
||||
[^:]*:296: Error: .*`st3 {v0.4s,v2.4s,v4.4s},\[x0\],#48'
|
||||
[^:]*:296: Error: .*`st4 {v0.4s,v2.4s,v4.4s,v6.4s},\[x0\],#64'
|
||||
[^:]*:296: Error: .*`st3 {v0.4s,v2.4s,v4.4s},\[x0\],x7'
|
||||
[^:]*:296: Error: .*`st4 {v0.4s,v2.4s,v4.4s,v6.4s},\[x0\],x7'
|
||||
[^:]*:296: Error: .*`st3 {v0.2d,v2.2d,v4.2d},\[x0\],#48'
|
||||
[^:]*:296: Error: .*`st4 {v0.2d,v2.2d,v4.2d,v6.2d},\[x0\],#64'
|
||||
[^:]*:296: Error: .*`st3 {v0.2d,v2.2d,v4.2d},\[x0\],x7'
|
||||
[^:]*:296: Error: .*`st4 {v0.2d,v2.2d,v4.2d,v6.2d},\[x0\],x7'
|
||||
[^:]*:262: Error: .*`ld2 {v0.8b,v2.8b},\[x0\],#16'
|
||||
[^:]*:262: Error: .*`ld2 {v0.8b,v1.8b,v2.8b,v3.8b},\[x0\],#32'
|
||||
[^:]*:262: Error: .*`ld2 {v0.8b,v2.8b},\[x0\],x7'
|
||||
[^:]*:262: Error: .*`ld2 {v0.8b,v1.8b,v2.8b,v3.8b},\[x0\],x7'
|
||||
[^:]*:262: Error: .*`ld2 {v0.4h,v2.4h},\[x0\],#16'
|
||||
[^:]*:262: Error: .*`ld2 {v0.4h,v1.4h,v2.4h,v3.4h},\[x0\],#32'
|
||||
[^:]*:262: Error: .*`ld2 {v0.4h,v2.4h},\[x0\],x7'
|
||||
[^:]*:262: Error: .*`ld2 {v0.4h,v1.4h,v2.4h,v3.4h},\[x0\],x7'
|
||||
[^:]*:262: Error: .*`ld2 {v0.2s,v2.2s},\[x0\],#16'
|
||||
[^:]*:262: Error: .*`ld2 {v0.2s,v1.2s,v2.2s,v3.2s},\[x0\],#32'
|
||||
[^:]*:262: Error: .*`ld2 {v0.2s,v2.2s},\[x0\],x7'
|
||||
[^:]*:262: Error: .*`ld2 {v0.2s,v1.2s,v2.2s,v3.2s},\[x0\],x7'
|
||||
[^:]*:262: Error: .*`st2 {v0.8b,v2.8b},\[x0\],#16'
|
||||
[^:]*:262: Error: .*`st2 {v0.8b,v1.8b,v2.8b,v3.8b},\[x0\],#32'
|
||||
[^:]*:262: Error: .*`st2 {v0.8b,v2.8b},\[x0\],x7'
|
||||
[^:]*:262: Error: .*`st2 {v0.8b,v1.8b,v2.8b,v3.8b},\[x0\],x7'
|
||||
[^:]*:262: Error: .*`st2 {v0.4h,v2.4h},\[x0\],#16'
|
||||
[^:]*:262: Error: .*`st2 {v0.4h,v1.4h,v2.4h,v3.4h},\[x0\],#32'
|
||||
[^:]*:262: Error: .*`st2 {v0.4h,v2.4h},\[x0\],x7'
|
||||
[^:]*:262: Error: .*`st2 {v0.4h,v1.4h,v2.4h,v3.4h},\[x0\],x7'
|
||||
[^:]*:262: Error: .*`st2 {v0.2s,v2.2s},\[x0\],#16'
|
||||
[^:]*:262: Error: .*`st2 {v0.2s,v1.2s,v2.2s,v3.2s},\[x0\],#32'
|
||||
[^:]*:262: Error: .*`st2 {v0.2s,v2.2s},\[x0\],x7'
|
||||
[^:]*:262: Error: .*`st2 {v0.2s,v1.2s,v2.2s,v3.2s},\[x0\],x7'
|
||||
[^:]*:268: Error: .*`ld2 {v0.16b,v2.16b},\[x0\],#32'
|
||||
[^:]*:268: Error: .*`ld2 {v0.16b,v1.16b,v2.16b,v3.16b},\[x0\],#64'
|
||||
[^:]*:268: Error: .*`ld2 {v0.16b,v2.16b},\[x0\],x7'
|
||||
[^:]*:268: Error: .*`ld2 {v0.16b,v1.16b,v2.16b,v3.16b},\[x0\],x7'
|
||||
[^:]*:268: Error: .*`ld2 {v0.8h,v2.8h},\[x0\],#32'
|
||||
[^:]*:268: Error: .*`ld2 {v0.8h,v1.8h,v2.8h,v3.8h},\[x0\],#64'
|
||||
[^:]*:268: Error: .*`ld2 {v0.8h,v2.8h},\[x0\],x7'
|
||||
[^:]*:268: Error: .*`ld2 {v0.8h,v1.8h,v2.8h,v3.8h},\[x0\],x7'
|
||||
[^:]*:268: Error: .*`ld2 {v0.4s,v2.4s},\[x0\],#32'
|
||||
[^:]*:268: Error: .*`ld2 {v0.4s,v1.4s,v2.4s,v3.4s},\[x0\],#64'
|
||||
[^:]*:268: Error: .*`ld2 {v0.4s,v2.4s},\[x0\],x7'
|
||||
[^:]*:268: Error: .*`ld2 {v0.4s,v1.4s,v2.4s,v3.4s},\[x0\],x7'
|
||||
[^:]*:268: Error: .*`ld2 {v0.2d,v2.2d},\[x0\],#32'
|
||||
[^:]*:268: Error: .*`ld2 {v0.2d,v1.2d,v2.2d,v3.2d},\[x0\],#64'
|
||||
[^:]*:268: Error: .*`ld2 {v0.2d,v2.2d},\[x0\],x7'
|
||||
[^:]*:268: Error: .*`ld2 {v0.2d,v1.2d,v2.2d,v3.2d},\[x0\],x7'
|
||||
[^:]*:268: Error: .*`st2 {v0.16b,v2.16b},\[x0\],#32'
|
||||
[^:]*:268: Error: .*`st2 {v0.16b,v1.16b,v2.16b,v3.16b},\[x0\],#64'
|
||||
[^:]*:268: Error: .*`st2 {v0.16b,v2.16b},\[x0\],x7'
|
||||
[^:]*:268: Error: .*`st2 {v0.16b,v1.16b,v2.16b,v3.16b},\[x0\],x7'
|
||||
[^:]*:268: Error: .*`st2 {v0.8h,v2.8h},\[x0\],#32'
|
||||
[^:]*:268: Error: .*`st2 {v0.8h,v1.8h,v2.8h,v3.8h},\[x0\],#64'
|
||||
[^:]*:268: Error: .*`st2 {v0.8h,v2.8h},\[x0\],x7'
|
||||
[^:]*:268: Error: .*`st2 {v0.8h,v1.8h,v2.8h,v3.8h},\[x0\],x7'
|
||||
[^:]*:268: Error: .*`st2 {v0.4s,v2.4s},\[x0\],#32'
|
||||
[^:]*:268: Error: .*`st2 {v0.4s,v1.4s,v2.4s,v3.4s},\[x0\],#64'
|
||||
[^:]*:268: Error: .*`st2 {v0.4s,v2.4s},\[x0\],x7'
|
||||
[^:]*:268: Error: .*`st2 {v0.4s,v1.4s,v2.4s,v3.4s},\[x0\],x7'
|
||||
[^:]*:268: Error: .*`st2 {v0.2d,v2.2d},\[x0\],#32'
|
||||
[^:]*:268: Error: .*`st2 {v0.2d,v1.2d,v2.2d,v3.2d},\[x0\],#64'
|
||||
[^:]*:268: Error: .*`st2 {v0.2d,v2.2d},\[x0\],x7'
|
||||
[^:]*:268: Error: .*`st2 {v0.2d,v1.2d,v2.2d,v3.2d},\[x0\],x7'
|
||||
[^:]*:288: Error: .*`ld3 {v0.8b,v2.8b,v4.8b},\[x0\],#24'
|
||||
[^:]*:288: Error: .*`ld4 {v0.8b,v2.8b,v4.8b,v6.8b},\[x0\],#32'
|
||||
[^:]*:288: Error: .*`ld3 {v0.8b,v2.8b,v4.8b},\[x0\],x7'
|
||||
[^:]*:288: Error: .*`ld4 {v0.8b,v2.8b,v4.8b,v6.8b},\[x0\],x7'
|
||||
[^:]*:288: Error: .*`ld3 {v0.4h,v2.4h,v4.4h},\[x0\],#24'
|
||||
[^:]*:288: Error: .*`ld4 {v0.4h,v2.4h,v4.4h,v6.4h},\[x0\],#32'
|
||||
[^:]*:288: Error: .*`ld3 {v0.4h,v2.4h,v4.4h},\[x0\],x7'
|
||||
[^:]*:288: Error: .*`ld4 {v0.4h,v2.4h,v4.4h,v6.4h},\[x0\],x7'
|
||||
[^:]*:288: Error: .*`ld3 {v0.2s,v2.2s,v4.2s},\[x0\],#24'
|
||||
[^:]*:288: Error: .*`ld4 {v0.2s,v2.2s,v4.2s,v6.2s},\[x0\],#32'
|
||||
[^:]*:288: Error: .*`ld3 {v0.2s,v2.2s,v4.2s},\[x0\],x7'
|
||||
[^:]*:288: Error: .*`ld4 {v0.2s,v2.2s,v4.2s,v6.2s},\[x0\],x7'
|
||||
[^:]*:288: Error: .*`st3 {v0.8b,v2.8b,v4.8b},\[x0\],#24'
|
||||
[^:]*:288: Error: .*`st4 {v0.8b,v2.8b,v4.8b,v6.8b},\[x0\],#32'
|
||||
[^:]*:288: Error: .*`st3 {v0.8b,v2.8b,v4.8b},\[x0\],x7'
|
||||
[^:]*:288: Error: .*`st4 {v0.8b,v2.8b,v4.8b,v6.8b},\[x0\],x7'
|
||||
[^:]*:288: Error: .*`st3 {v0.4h,v2.4h,v4.4h},\[x0\],#24'
|
||||
[^:]*:288: Error: .*`st4 {v0.4h,v2.4h,v4.4h,v6.4h},\[x0\],#32'
|
||||
[^:]*:288: Error: .*`st3 {v0.4h,v2.4h,v4.4h},\[x0\],x7'
|
||||
[^:]*:288: Error: .*`st4 {v0.4h,v2.4h,v4.4h,v6.4h},\[x0\],x7'
|
||||
[^:]*:288: Error: .*`st3 {v0.2s,v2.2s,v4.2s},\[x0\],#24'
|
||||
[^:]*:288: Error: .*`st4 {v0.2s,v2.2s,v4.2s,v6.2s},\[x0\],#32'
|
||||
[^:]*:288: Error: .*`st3 {v0.2s,v2.2s,v4.2s},\[x0\],x7'
|
||||
[^:]*:288: Error: .*`st4 {v0.2s,v2.2s,v4.2s,v6.2s},\[x0\],x7'
|
||||
[^:]*:294: Error: .*`ld3 {v0.16b,v2.16b,v4.16b},\[x0\],#48'
|
||||
[^:]*:294: Error: .*`ld4 {v0.16b,v2.16b,v4.16b,v6.16b},\[x0\],#64'
|
||||
[^:]*:294: Error: .*`ld3 {v0.16b,v2.16b,v4.16b},\[x0\],x7'
|
||||
[^:]*:294: Error: .*`ld4 {v0.16b,v2.16b,v4.16b,v6.16b},\[x0\],x7'
|
||||
[^:]*:294: Error: .*`ld3 {v0.8h,v2.8h,v4.8h},\[x0\],#48'
|
||||
[^:]*:294: Error: .*`ld4 {v0.8h,v2.8h,v4.8h,v6.8h},\[x0\],#64'
|
||||
[^:]*:294: Error: .*`ld3 {v0.8h,v2.8h,v4.8h},\[x0\],x7'
|
||||
[^:]*:294: Error: .*`ld4 {v0.8h,v2.8h,v4.8h,v6.8h},\[x0\],x7'
|
||||
[^:]*:294: Error: .*`ld3 {v0.4s,v2.4s,v4.4s},\[x0\],#48'
|
||||
[^:]*:294: Error: .*`ld4 {v0.4s,v2.4s,v4.4s,v6.4s},\[x0\],#64'
|
||||
[^:]*:294: Error: .*`ld3 {v0.4s,v2.4s,v4.4s},\[x0\],x7'
|
||||
[^:]*:294: Error: .*`ld4 {v0.4s,v2.4s,v4.4s,v6.4s},\[x0\],x7'
|
||||
[^:]*:294: Error: .*`ld3 {v0.2d,v2.2d,v4.2d},\[x0\],#48'
|
||||
[^:]*:294: Error: .*`ld4 {v0.2d,v2.2d,v4.2d,v6.2d},\[x0\],#64'
|
||||
[^:]*:294: Error: .*`ld3 {v0.2d,v2.2d,v4.2d},\[x0\],x7'
|
||||
[^:]*:294: Error: .*`ld4 {v0.2d,v2.2d,v4.2d,v6.2d},\[x0\],x7'
|
||||
[^:]*:294: Error: .*`st3 {v0.16b,v2.16b,v4.16b},\[x0\],#48'
|
||||
[^:]*:294: Error: .*`st4 {v0.16b,v2.16b,v4.16b,v6.16b},\[x0\],#64'
|
||||
[^:]*:294: Error: .*`st3 {v0.16b,v2.16b,v4.16b},\[x0\],x7'
|
||||
[^:]*:294: Error: .*`st4 {v0.16b,v2.16b,v4.16b,v6.16b},\[x0\],x7'
|
||||
[^:]*:294: Error: .*`st3 {v0.8h,v2.8h,v4.8h},\[x0\],#48'
|
||||
[^:]*:294: Error: .*`st4 {v0.8h,v2.8h,v4.8h,v6.8h},\[x0\],#64'
|
||||
[^:]*:294: Error: .*`st3 {v0.8h,v2.8h,v4.8h},\[x0\],x7'
|
||||
[^:]*:294: Error: .*`st4 {v0.8h,v2.8h,v4.8h,v6.8h},\[x0\],x7'
|
||||
[^:]*:294: Error: .*`st3 {v0.4s,v2.4s,v4.4s},\[x0\],#48'
|
||||
[^:]*:294: Error: .*`st4 {v0.4s,v2.4s,v4.4s,v6.4s},\[x0\],#64'
|
||||
[^:]*:294: Error: .*`st3 {v0.4s,v2.4s,v4.4s},\[x0\],x7'
|
||||
[^:]*:294: Error: .*`st4 {v0.4s,v2.4s,v4.4s,v6.4s},\[x0\],x7'
|
||||
[^:]*:294: Error: .*`st3 {v0.2d,v2.2d,v4.2d},\[x0\],#48'
|
||||
[^:]*:294: Error: .*`st4 {v0.2d,v2.2d,v4.2d,v6.2d},\[x0\],#64'
|
||||
[^:]*:294: Error: .*`st3 {v0.2d,v2.2d,v4.2d},\[x0\],x7'
|
||||
[^:]*:294: Error: .*`st4 {v0.2d,v2.2d,v4.2d,v6.2d},\[x0\],x7'
|
||||
[^:]*:300: Error: .*`ld1r {v0.8b,v1.8b},\[x0\],#1'
|
||||
[^:]*:301: Error: .*`ld1r {v0.16b,v1.16b},\[x0\],#1'
|
||||
[^:]*:302: Error: .*`ld1r {v0.4h,v1.4h},\[x0\],#2'
|
||||
@ -287,98 +287,98 @@
|
||||
[^:]*:305: Error: .*`ld1r {v0.4s,v1.4s},\[x0\],#4'
|
||||
[^:]*:306: Error: .*`ld1r {v0.1d,v1.1d},\[x0\],#8'
|
||||
[^:]*:307: Error: .*`ld1r {v0.2d,v1.2d},\[x0\],#8'
|
||||
[^:]*:322: Error: .*`ld2 {v0.h,v2.h}\[1\],\[x0\],#4'
|
||||
[^:]*:322: Error: .*`ld3 {v0.h,v2.h,v4.h}\[1\],\[x0\],#6'
|
||||
[^:]*:322: Error: .*`ld4 {v0.h,v2.h,v4.h,v6.h}\[1\],\[x0\],#8'
|
||||
[^:]*:322: Error: .*`ld2r {v0.4h,v2.4h},\[x0\],#4'
|
||||
[^:]*:322: Error: .*`ld3r {v0.4h,v2.4h,v4.4h},\[x0\],#6'
|
||||
[^:]*:322: Error: .*`ld4r {v0.4h,v2.4h,v4.4h,v6.4h},\[x0\],#8'
|
||||
[^:]*:322: Error: .*`ld2r {v0.8h,v2.8h},\[x0\],#4'
|
||||
[^:]*:322: Error: .*`ld3r {v0.8h,v2.8h,v4.8h},\[x0\],#6'
|
||||
[^:]*:322: Error: .*`ld4r {v0.8h,v2.8h,v4.8h,v6.8h},\[x0\],#8'
|
||||
[^:]*:322: Error: .*`st2 {v0.h,v2.h}\[1\],\[x0\],#4'
|
||||
[^:]*:322: Error: .*`st3 {v0.h,v2.h,v4.h}\[1\],\[x0\],#6'
|
||||
[^:]*:322: Error: .*`st4 {v0.h,v2.h,v4.h,v6.h}\[1\],\[x0\],#8'
|
||||
[^:]*:337: Error: .*`ld2 {v0.s,v2.s}\[1\],\[x0\],#8'
|
||||
[^:]*:337: Error: .*`ld3 {v0.s,v2.s,v4.s}\[1\],\[x0\],#12'
|
||||
[^:]*:337: Error: .*`ld4 {v0.s,v2.s,v4.s,v6.s}\[1\],\[x0\],#16'
|
||||
[^:]*:337: Error: .*`ld2r {v0.2s,v2.2s},\[x0\],#8'
|
||||
[^:]*:337: Error: .*`ld3r {v0.2s,v2.2s,v4.2s},\[x0\],#12'
|
||||
[^:]*:337: Error: .*`ld4r {v0.2s,v2.2s,v4.2s,v6.2s},\[x0\],#16'
|
||||
[^:]*:337: Error: .*`ld2r {v0.4s,v2.4s},\[x0\],#8'
|
||||
[^:]*:337: Error: .*`ld3r {v0.4s,v2.4s,v4.4s},\[x0\],#12'
|
||||
[^:]*:337: Error: .*`ld4r {v0.4s,v2.4s,v4.4s,v6.4s},\[x0\],#16'
|
||||
[^:]*:337: Error: .*`st2 {v0.s,v2.s}\[1\],\[x0\],#8'
|
||||
[^:]*:337: Error: .*`st3 {v0.s,v2.s,v4.s}\[1\],\[x0\],#12'
|
||||
[^:]*:337: Error: .*`st4 {v0.s,v2.s,v4.s,v6.s}\[1\],\[x0\],#16'
|
||||
[^:]*:352: Error: .*`ld2 {v0.d,v2.d}\[1\],\[x0\],#16'
|
||||
[^:]*:352: Error: .*`ld3 {v0.d,v2.d,v4.d}\[1\],\[x0\],#24'
|
||||
[^:]*:352: Error: .*`ld4 {v0.d,v2.d,v4.d,v6.d}\[1\],\[x0\],#32'
|
||||
[^:]*:352: Error: .*`ld2r {v0.1d,v2.1d},\[x0\],#16'
|
||||
[^:]*:352: Error: .*`ld3r {v0.1d,v2.1d,v4.1d},\[x0\],#24'
|
||||
[^:]*:352: Error: .*`ld4r {v0.1d,v2.1d,v4.1d,v6.1d},\[x0\],#32'
|
||||
[^:]*:352: Error: .*`ld2r {v0.2d,v2.2d},\[x0\],#16'
|
||||
[^:]*:352: Error: .*`ld3r {v0.2d,v2.2d,v4.2d},\[x0\],#24'
|
||||
[^:]*:352: Error: .*`ld4r {v0.2d,v2.2d,v4.2d,v6.2d},\[x0\],#32'
|
||||
[^:]*:352: Error: .*`st2 {v0.d,v2.d}\[1\],\[x0\],#16'
|
||||
[^:]*:352: Error: .*`st3 {v0.d,v2.d,v4.d}\[1\],\[x0\],#24'
|
||||
[^:]*:352: Error: .*`st4 {v0.d,v2.d,v4.d,v6.d}\[1\],\[x0\],#32'
|
||||
[^:]*:356: Error: .*`ld1r {v0.8b,v1.8b},\[x0\],x7'
|
||||
[^:]*:356: Error: .*`ld1r {v0.16b,v1.16b},\[x0\],x7'
|
||||
[^:]*:356: Error: .*`ld1r {v0.4h,v1.4h},\[x0\],x7'
|
||||
[^:]*:356: Error: .*`ld1r {v0.8h,v1.8h},\[x0\],x7'
|
||||
[^:]*:356: Error: .*`ld1r {v0.2s,v1.2s},\[x0\],x7'
|
||||
[^:]*:356: Error: .*`ld1r {v0.4s,v1.4s},\[x0\],x7'
|
||||
[^:]*:356: Error: .*`ld1r {v0.1d,v1.1d},\[x0\],x7'
|
||||
[^:]*:356: Error: .*`ld1r {v0.2d,v1.2d},\[x0\],x7'
|
||||
[^:]*:373: Error: .*`ld2 {v0.b,v2.b}\[1\],\[x0\],x7'
|
||||
[^:]*:373: Error: .*`ld3 {v0.b,v2.b,v4.b}\[1\],\[x0\],x7'
|
||||
[^:]*:373: Error: .*`ld4 {v0.b,v2.b,v4.b,v6.b}\[1\],\[x0\],x7'
|
||||
[^:]*:373: Error: .*`ld2 {v0.h,v2.h}\[1\],\[x0\],x7'
|
||||
[^:]*:373: Error: .*`ld3 {v0.h,v2.h,v4.h}\[1\],\[x0\],x7'
|
||||
[^:]*:373: Error: .*`ld4 {v0.h,v2.h,v4.h,v6.h}\[1\],\[x0\],x7'
|
||||
[^:]*:373: Error: .*`ld2 {v0.s,v2.s}\[1\],\[x0\],x7'
|
||||
[^:]*:373: Error: .*`ld3 {v0.s,v2.s,v4.s}\[1\],\[x0\],x7'
|
||||
[^:]*:373: Error: .*`ld4 {v0.s,v2.s,v4.s,v6.s}\[1\],\[x0\],x7'
|
||||
[^:]*:373: Error: .*`ld2 {v0.d,v2.d}\[1\],\[x0\],x7'
|
||||
[^:]*:373: Error: .*`ld3 {v0.d,v2.d,v4.d}\[1\],\[x0\],x7'
|
||||
[^:]*:373: Error: .*`ld4 {v0.d,v2.d,v4.d,v6.d}\[1\],\[x0\],x7'
|
||||
[^:]*:373: Error: .*`ld2r {v0.8b,v2.8b},\[x0\],x7'
|
||||
[^:]*:373: Error: .*`ld3r {v0.8b,v2.8b,v4.8b},\[x0\],x7'
|
||||
[^:]*:373: Error: .*`ld4r {v0.8b,v2.8b,v4.8b,v6.8b},\[x0\],x7'
|
||||
[^:]*:373: Error: .*`ld2r {v0.16b,v2.16b},\[x0\],x7'
|
||||
[^:]*:373: Error: .*`ld3r {v0.16b,v2.16b,v4.16b},\[x0\],x7'
|
||||
[^:]*:373: Error: .*`ld4r {v0.16b,v2.16b,v4.16b,v6.16b},\[x0\],x7'
|
||||
[^:]*:373: Error: .*`ld2r {v0.4h,v2.4h},\[x0\],x7'
|
||||
[^:]*:373: Error: .*`ld3r {v0.4h,v2.4h,v4.4h},\[x0\],x7'
|
||||
[^:]*:373: Error: .*`ld4r {v0.4h,v2.4h,v4.4h,v6.4h},\[x0\],x7'
|
||||
[^:]*:373: Error: .*`ld2r {v0.8h,v2.8h},\[x0\],x7'
|
||||
[^:]*:373: Error: .*`ld3r {v0.8h,v2.8h,v4.8h},\[x0\],x7'
|
||||
[^:]*:373: Error: .*`ld4r {v0.8h,v2.8h,v4.8h,v6.8h},\[x0\],x7'
|
||||
[^:]*:373: Error: .*`ld2r {v0.2s,v2.2s},\[x0\],x7'
|
||||
[^:]*:373: Error: .*`ld3r {v0.2s,v2.2s,v4.2s},\[x0\],x7'
|
||||
[^:]*:373: Error: .*`ld4r {v0.2s,v2.2s,v4.2s,v6.2s},\[x0\],x7'
|
||||
[^:]*:373: Error: .*`ld2r {v0.4s,v2.4s},\[x0\],x7'
|
||||
[^:]*:373: Error: .*`ld3r {v0.4s,v2.4s,v4.4s},\[x0\],x7'
|
||||
[^:]*:373: Error: .*`ld4r {v0.4s,v2.4s,v4.4s,v6.4s},\[x0\],x7'
|
||||
[^:]*:373: Error: .*`ld2r {v0.1d,v2.1d},\[x0\],x7'
|
||||
[^:]*:373: Error: .*`ld3r {v0.1d,v2.1d,v4.1d},\[x0\],x7'
|
||||
[^:]*:373: Error: .*`ld4r {v0.1d,v2.1d,v4.1d,v6.1d},\[x0\],x7'
|
||||
[^:]*:373: Error: .*`ld2r {v0.2d,v2.2d},\[x0\],x7'
|
||||
[^:]*:373: Error: .*`ld3r {v0.2d,v2.2d,v4.2d},\[x0\],x7'
|
||||
[^:]*:373: Error: .*`ld4r {v0.2d,v2.2d,v4.2d,v6.2d},\[x0\],x7'
|
||||
[^:]*:373: Error: .*`st2 {v0.b,v2.b}\[1\],\[x0\],x7'
|
||||
[^:]*:373: Error: .*`st3 {v0.b,v2.b,v4.b}\[1\],\[x0\],x7'
|
||||
[^:]*:373: Error: .*`st4 {v0.b,v2.b,v4.b,v6.b}\[1\],\[x0\],x7'
|
||||
[^:]*:373: Error: .*`st2 {v0.h,v2.h}\[1\],\[x0\],x7'
|
||||
[^:]*:373: Error: .*`st3 {v0.h,v2.h,v4.h}\[1\],\[x0\],x7'
|
||||
[^:]*:373: Error: .*`st4 {v0.h,v2.h,v4.h,v6.h}\[1\],\[x0\],x7'
|
||||
[^:]*:373: Error: .*`st2 {v0.s,v2.s}\[1\],\[x0\],x7'
|
||||
[^:]*:373: Error: .*`st3 {v0.s,v2.s,v4.s}\[1\],\[x0\],x7'
|
||||
[^:]*:373: Error: .*`st4 {v0.s,v2.s,v4.s,v6.s}\[1\],\[x0\],x7'
|
||||
[^:]*:373: Error: .*`st2 {v0.d,v2.d}\[1\],\[x0\],x7'
|
||||
[^:]*:373: Error: .*`st3 {v0.d,v2.d,v4.d}\[1\],\[x0\],x7'
|
||||
[^:]*:373: Error: .*`st4 {v0.d,v2.d,v4.d,v6.d}\[1\],\[x0\],x7'
|
||||
[^:]*:316: Error: .*`ld2 {v0.h,v2.h}\[1\],\[x0\],#4'
|
||||
[^:]*:316: Error: .*`ld3 {v0.h,v2.h,v4.h}\[1\],\[x0\],#6'
|
||||
[^:]*:316: Error: .*`ld4 {v0.h,v2.h,v4.h,v6.h}\[1\],\[x0\],#8'
|
||||
[^:]*:319: Error: .*`ld2r {v0.4h,v2.4h},\[x0\],#4'
|
||||
[^:]*:319: Error: .*`ld3r {v0.4h,v2.4h,v4.4h},\[x0\],#6'
|
||||
[^:]*:319: Error: .*`ld4r {v0.4h,v2.4h,v4.4h,v6.4h},\[x0\],#8'
|
||||
[^:]*:319: Error: .*`ld2r {v0.8h,v2.8h},\[x0\],#4'
|
||||
[^:]*:319: Error: .*`ld3r {v0.8h,v2.8h,v4.8h},\[x0\],#6'
|
||||
[^:]*:319: Error: .*`ld4r {v0.8h,v2.8h,v4.8h,v6.8h},\[x0\],#8'
|
||||
[^:]*:316: Error: .*`st2 {v0.h,v2.h}\[1\],\[x0\],#4'
|
||||
[^:]*:316: Error: .*`st3 {v0.h,v2.h,v4.h}\[1\],\[x0\],#6'
|
||||
[^:]*:316: Error: .*`st4 {v0.h,v2.h,v4.h,v6.h}\[1\],\[x0\],#8'
|
||||
[^:]*:331: Error: .*`ld2 {v0.s,v2.s}\[1\],\[x0\],#8'
|
||||
[^:]*:331: Error: .*`ld3 {v0.s,v2.s,v4.s}\[1\],\[x0\],#12'
|
||||
[^:]*:331: Error: .*`ld4 {v0.s,v2.s,v4.s,v6.s}\[1\],\[x0\],#16'
|
||||
[^:]*:334: Error: .*`ld2r {v0.2s,v2.2s},\[x0\],#8'
|
||||
[^:]*:334: Error: .*`ld3r {v0.2s,v2.2s,v4.2s},\[x0\],#12'
|
||||
[^:]*:334: Error: .*`ld4r {v0.2s,v2.2s,v4.2s,v6.2s},\[x0\],#16'
|
||||
[^:]*:334: Error: .*`ld2r {v0.4s,v2.4s},\[x0\],#8'
|
||||
[^:]*:334: Error: .*`ld3r {v0.4s,v2.4s,v4.4s},\[x0\],#12'
|
||||
[^:]*:334: Error: .*`ld4r {v0.4s,v2.4s,v4.4s,v6.4s},\[x0\],#16'
|
||||
[^:]*:331: Error: .*`st2 {v0.s,v2.s}\[1\],\[x0\],#8'
|
||||
[^:]*:331: Error: .*`st3 {v0.s,v2.s,v4.s}\[1\],\[x0\],#12'
|
||||
[^:]*:331: Error: .*`st4 {v0.s,v2.s,v4.s,v6.s}\[1\],\[x0\],#16'
|
||||
[^:]*:346: Error: .*`ld2 {v0.d,v2.d}\[1\],\[x0\],#16'
|
||||
[^:]*:346: Error: .*`ld3 {v0.d,v2.d,v4.d}\[1\],\[x0\],#24'
|
||||
[^:]*:346: Error: .*`ld4 {v0.d,v2.d,v4.d,v6.d}\[1\],\[x0\],#32'
|
||||
[^:]*:349: Error: .*`ld2r {v0.1d,v2.1d},\[x0\],#16'
|
||||
[^:]*:349: Error: .*`ld3r {v0.1d,v2.1d,v4.1d},\[x0\],#24'
|
||||
[^:]*:349: Error: .*`ld4r {v0.1d,v2.1d,v4.1d,v6.1d},\[x0\],#32'
|
||||
[^:]*:349: Error: .*`ld2r {v0.2d,v2.2d},\[x0\],#16'
|
||||
[^:]*:349: Error: .*`ld3r {v0.2d,v2.2d,v4.2d},\[x0\],#24'
|
||||
[^:]*:349: Error: .*`ld4r {v0.2d,v2.2d,v4.2d,v6.2d},\[x0\],#32'
|
||||
[^:]*:346: Error: .*`st2 {v0.d,v2.d}\[1\],\[x0\],#16'
|
||||
[^:]*:346: Error: .*`st3 {v0.d,v2.d,v4.d}\[1\],\[x0\],#24'
|
||||
[^:]*:346: Error: .*`st4 {v0.d,v2.d,v4.d,v6.d}\[1\],\[x0\],#32'
|
||||
[^:]*:355: Error: .*`ld1r {v0.8b,v1.8b},\[x0\],x7'
|
||||
[^:]*:355: Error: .*`ld1r {v0.16b,v1.16b},\[x0\],x7'
|
||||
[^:]*:355: Error: .*`ld1r {v0.4h,v1.4h},\[x0\],x7'
|
||||
[^:]*:355: Error: .*`ld1r {v0.8h,v1.8h},\[x0\],x7'
|
||||
[^:]*:355: Error: .*`ld1r {v0.2s,v1.2s},\[x0\],x7'
|
||||
[^:]*:355: Error: .*`ld1r {v0.4s,v1.4s},\[x0\],x7'
|
||||
[^:]*:355: Error: .*`ld1r {v0.1d,v1.1d},\[x0\],x7'
|
||||
[^:]*:355: Error: .*`ld1r {v0.2d,v1.2d},\[x0\],x7'
|
||||
[^:]*:366: Error: .*`ld2 {v0.b,v2.b}\[1\],\[x0\],x7'
|
||||
[^:]*:366: Error: .*`ld3 {v0.b,v2.b,v4.b}\[1\],\[x0\],x7'
|
||||
[^:]*:366: Error: .*`ld4 {v0.b,v2.b,v4.b,v6.b}\[1\],\[x0\],x7'
|
||||
[^:]*:366: Error: .*`ld2 {v0.h,v2.h}\[1\],\[x0\],x7'
|
||||
[^:]*:366: Error: .*`ld3 {v0.h,v2.h,v4.h}\[1\],\[x0\],x7'
|
||||
[^:]*:366: Error: .*`ld4 {v0.h,v2.h,v4.h,v6.h}\[1\],\[x0\],x7'
|
||||
[^:]*:366: Error: .*`ld2 {v0.s,v2.s}\[1\],\[x0\],x7'
|
||||
[^:]*:366: Error: .*`ld3 {v0.s,v2.s,v4.s}\[1\],\[x0\],x7'
|
||||
[^:]*:366: Error: .*`ld4 {v0.s,v2.s,v4.s,v6.s}\[1\],\[x0\],x7'
|
||||
[^:]*:366: Error: .*`ld2 {v0.d,v2.d}\[1\],\[x0\],x7'
|
||||
[^:]*:366: Error: .*`ld3 {v0.d,v2.d,v4.d}\[1\],\[x0\],x7'
|
||||
[^:]*:366: Error: .*`ld4 {v0.d,v2.d,v4.d,v6.d}\[1\],\[x0\],x7'
|
||||
[^:]*:370: Error: .*`ld2r {v0.8b,v2.8b},\[x0\],x7'
|
||||
[^:]*:370: Error: .*`ld3r {v0.8b,v2.8b,v4.8b},\[x0\],x7'
|
||||
[^:]*:370: Error: .*`ld4r {v0.8b,v2.8b,v4.8b,v6.8b},\[x0\],x7'
|
||||
[^:]*:370: Error: .*`ld2r {v0.16b,v2.16b},\[x0\],x7'
|
||||
[^:]*:370: Error: .*`ld3r {v0.16b,v2.16b,v4.16b},\[x0\],x7'
|
||||
[^:]*:370: Error: .*`ld4r {v0.16b,v2.16b,v4.16b,v6.16b},\[x0\],x7'
|
||||
[^:]*:370: Error: .*`ld2r {v0.4h,v2.4h},\[x0\],x7'
|
||||
[^:]*:370: Error: .*`ld3r {v0.4h,v2.4h,v4.4h},\[x0\],x7'
|
||||
[^:]*:370: Error: .*`ld4r {v0.4h,v2.4h,v4.4h,v6.4h},\[x0\],x7'
|
||||
[^:]*:370: Error: .*`ld2r {v0.8h,v2.8h},\[x0\],x7'
|
||||
[^:]*:370: Error: .*`ld3r {v0.8h,v2.8h,v4.8h},\[x0\],x7'
|
||||
[^:]*:370: Error: .*`ld4r {v0.8h,v2.8h,v4.8h,v6.8h},\[x0\],x7'
|
||||
[^:]*:370: Error: .*`ld2r {v0.2s,v2.2s},\[x0\],x7'
|
||||
[^:]*:370: Error: .*`ld3r {v0.2s,v2.2s,v4.2s},\[x0\],x7'
|
||||
[^:]*:370: Error: .*`ld4r {v0.2s,v2.2s,v4.2s,v6.2s},\[x0\],x7'
|
||||
[^:]*:370: Error: .*`ld2r {v0.4s,v2.4s},\[x0\],x7'
|
||||
[^:]*:370: Error: .*`ld3r {v0.4s,v2.4s,v4.4s},\[x0\],x7'
|
||||
[^:]*:370: Error: .*`ld4r {v0.4s,v2.4s,v4.4s,v6.4s},\[x0\],x7'
|
||||
[^:]*:370: Error: .*`ld2r {v0.1d,v2.1d},\[x0\],x7'
|
||||
[^:]*:370: Error: .*`ld3r {v0.1d,v2.1d,v4.1d},\[x0\],x7'
|
||||
[^:]*:370: Error: .*`ld4r {v0.1d,v2.1d,v4.1d,v6.1d},\[x0\],x7'
|
||||
[^:]*:370: Error: .*`ld2r {v0.2d,v2.2d},\[x0\],x7'
|
||||
[^:]*:370: Error: .*`ld3r {v0.2d,v2.2d,v4.2d},\[x0\],x7'
|
||||
[^:]*:370: Error: .*`ld4r {v0.2d,v2.2d,v4.2d,v6.2d},\[x0\],x7'
|
||||
[^:]*:366: Error: .*`st2 {v0.b,v2.b}\[1\],\[x0\],x7'
|
||||
[^:]*:366: Error: .*`st3 {v0.b,v2.b,v4.b}\[1\],\[x0\],x7'
|
||||
[^:]*:366: Error: .*`st4 {v0.b,v2.b,v4.b,v6.b}\[1\],\[x0\],x7'
|
||||
[^:]*:366: Error: .*`st2 {v0.h,v2.h}\[1\],\[x0\],x7'
|
||||
[^:]*:366: Error: .*`st3 {v0.h,v2.h,v4.h}\[1\],\[x0\],x7'
|
||||
[^:]*:366: Error: .*`st4 {v0.h,v2.h,v4.h,v6.h}\[1\],\[x0\],x7'
|
||||
[^:]*:366: Error: .*`st2 {v0.s,v2.s}\[1\],\[x0\],x7'
|
||||
[^:]*:366: Error: .*`st3 {v0.s,v2.s,v4.s}\[1\],\[x0\],x7'
|
||||
[^:]*:366: Error: .*`st4 {v0.s,v2.s,v4.s,v6.s}\[1\],\[x0\],x7'
|
||||
[^:]*:366: Error: .*`st2 {v0.d,v2.d}\[1\],\[x0\],x7'
|
||||
[^:]*:366: Error: .*`st3 {v0.d,v2.d,v4.d}\[1\],\[x0\],x7'
|
||||
[^:]*:366: Error: .*`st4 {v0.d,v2.d,v4.d,v6.d}\[1\],\[x0\],x7'
|
||||
[^:]*:396: Error: .*`ld2 {v0.8B,v2.8B},\[x0\]'
|
||||
[^:]*:396: Error: .*`ld3 {v0.8B,v2.8B,v4.8B},\[x0\]'
|
||||
[^:]*:396: Error: .*`ld4 {v0.8B,v2.8B,v4.8B,v6.8B},\[x0\]'
|
||||
@ -485,22 +485,22 @@
|
||||
[^:]*:452: Error: .*`ld4r {v0.2D,v2.2D,v4.2D,v6.2D},\[x0\]'
|
||||
[^:]*:454: Error: .*`pmull v0.1q,v1.1d,v2.1d'
|
||||
[^:]*:455: Error: .*`pmull2 v0.1q,v1.2d,v2.2d'
|
||||
[^:]*:463: Error: .*`scvtf d0,w1,33'
|
||||
[^:]*:463: Error: .*`scvtf s0,w0,33'
|
||||
[^:]*:463: Error: .*`scvtf d0,x1,65'
|
||||
[^:]*:463: Error: .*`scvtf s0,x1,65'
|
||||
[^:]*:463: Error: .*`ucvtf d0,w1,33'
|
||||
[^:]*:463: Error: .*`ucvtf s0,w0,33'
|
||||
[^:]*:463: Error: .*`ucvtf d0,x1,65'
|
||||
[^:]*:463: Error: .*`ucvtf s0,x1,65'
|
||||
[^:]*:469: Error: .*`fcvtzs w1,d0,33'
|
||||
[^:]*:469: Error: .*`fcvtzs w0,s0,33'
|
||||
[^:]*:469: Error: .*`fcvtzs x1,d0,65'
|
||||
[^:]*:469: Error: .*`fcvtzs x1,s0,65'
|
||||
[^:]*:469: Error: .*`fcvtzu w1,d0,33'
|
||||
[^:]*:469: Error: .*`fcvtzu w0,s0,33'
|
||||
[^:]*:469: Error: .*`fcvtzu x1,d0,65'
|
||||
[^:]*:469: Error: .*`fcvtzu x1,s0,65'
|
||||
[^:]*:459: Error: .*`scvtf d0,w1,33'
|
||||
[^:]*:460: Error: .*`scvtf s0,w0,33'
|
||||
[^:]*:461: Error: .*`scvtf d0,x1,65'
|
||||
[^:]*:462: Error: .*`scvtf s0,x1,65'
|
||||
[^:]*:459: Error: .*`ucvtf d0,w1,33'
|
||||
[^:]*:460: Error: .*`ucvtf s0,w0,33'
|
||||
[^:]*:461: Error: .*`ucvtf d0,x1,65'
|
||||
[^:]*:462: Error: .*`ucvtf s0,x1,65'
|
||||
[^:]*:465: Error: .*`fcvtzs w1,d0,33'
|
||||
[^:]*:466: Error: .*`fcvtzs w0,s0,33'
|
||||
[^:]*:467: Error: .*`fcvtzs x1,d0,65'
|
||||
[^:]*:468: Error: .*`fcvtzs x1,s0,65'
|
||||
[^:]*:465: Error: .*`fcvtzu w1,d0,33'
|
||||
[^:]*:466: Error: .*`fcvtzu w0,s0,33'
|
||||
[^:]*:467: Error: .*`fcvtzu x1,d0,65'
|
||||
[^:]*:468: Error: .*`fcvtzu x1,s0,65'
|
||||
[^:]*:472: Error: .*
|
||||
[^:]*:475: Error: .*`ldrh w0,\[x1,x2,lsr#1\]'
|
||||
[^:]*:477: Error: .*`add w0,w1,w2,ror#1'
|
||||
|
||||
@ -1,36 +1,36 @@
|
||||
[^:]*: Assembler messages:
|
||||
[^:]*:8: Error: Type is not allowed for this instruction -- `vctp.s8 r13'
|
||||
[^:]*:8: Error: Type is not allowed for this instruction -- `vctp.u16 r13'
|
||||
[^:]*:8: Error: Type is not allowed for this instruction -- `vctp.f32 r13'
|
||||
[^:]*:8: Error: r15 not allowed here -- `vctp.8 r15'
|
||||
[^:]*:8: Error: r15 not allowed here -- `vctp.16 r15'
|
||||
[^:]*:8: Error: r15 not allowed here -- `vctp.32 r15'
|
||||
[^:]*:8: Error: r15 not allowed here -- `vctp.64 r15'
|
||||
[^:]*:8: Error: r15 not allowed here -- `vctp.s8 r15'
|
||||
[^:]*:8: Error: r15 not allowed here -- `vctp.u16 r15'
|
||||
[^:]*:8: Error: r15 not allowed here -- `vctp.f32 r15'
|
||||
[^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.8 r0'
|
||||
[^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.16 r0'
|
||||
[^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.32 r0'
|
||||
[^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.64 r0'
|
||||
[^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.f32 r0'
|
||||
[^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.8 r1'
|
||||
[^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.16 r1'
|
||||
[^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.32 r1'
|
||||
[^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.64 r1'
|
||||
[^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.f32 r1'
|
||||
[^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.8 r2'
|
||||
[^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.16 r2'
|
||||
[^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.32 r2'
|
||||
[^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.64 r2'
|
||||
[^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.f32 r2'
|
||||
[^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.8 r4'
|
||||
[^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.16 r4'
|
||||
[^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.32 r4'
|
||||
[^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.64 r4'
|
||||
[^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.f32 r4'
|
||||
[^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.8 r8'
|
||||
[^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.16 r8'
|
||||
[^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.32 r8'
|
||||
[^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.64 r8'
|
||||
[^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.f32 r8'
|
||||
[^:]*:6: Error: Type is not allowed for this instruction -- `vctp.s8 r13'
|
||||
[^:]*:6: Error: Type is not allowed for this instruction -- `vctp.u16 r13'
|
||||
[^:]*:6: Error: Type is not allowed for this instruction -- `vctp.f32 r13'
|
||||
[^:]*:6: Error: r15 not allowed here -- `vctp.8 r15'
|
||||
[^:]*:6: Error: r15 not allowed here -- `vctp.16 r15'
|
||||
[^:]*:6: Error: r15 not allowed here -- `vctp.32 r15'
|
||||
[^:]*:6: Error: r15 not allowed here -- `vctp.64 r15'
|
||||
[^:]*:6: Error: r15 not allowed here -- `vctp.s8 r15'
|
||||
[^:]*:6: Error: r15 not allowed here -- `vctp.u16 r15'
|
||||
[^:]*:6: Error: r15 not allowed here -- `vctp.f32 r15'
|
||||
[^:]*:12: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.8 r0'
|
||||
[^:]*:12: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.16 r0'
|
||||
[^:]*:12: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.32 r0'
|
||||
[^:]*:12: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.64 r0'
|
||||
[^:]*:12: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.f32 r0'
|
||||
[^:]*:12: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.8 r1'
|
||||
[^:]*:12: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.16 r1'
|
||||
[^:]*:12: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.32 r1'
|
||||
[^:]*:12: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.64 r1'
|
||||
[^:]*:12: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.f32 r1'
|
||||
[^:]*:12: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.8 r2'
|
||||
[^:]*:12: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.16 r2'
|
||||
[^:]*:12: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.32 r2'
|
||||
[^:]*:12: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.64 r2'
|
||||
[^:]*:12: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.f32 r2'
|
||||
[^:]*:12: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.8 r4'
|
||||
[^:]*:12: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.16 r4'
|
||||
[^:]*:12: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.32 r4'
|
||||
[^:]*:12: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.64 r4'
|
||||
[^:]*:12: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.f32 r4'
|
||||
[^:]*:12: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.8 r8'
|
||||
[^:]*:12: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.16 r8'
|
||||
[^:]*:12: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.32 r8'
|
||||
[^:]*:12: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.64 r8'
|
||||
[^:]*:12: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.f32 r8'
|
||||
|
||||
@ -133,37 +133,37 @@
|
||||
[^:]*:134: Error: syntax error -- `vldrweq.32 q0,\[r0\]'
|
||||
[^:]*:135: Error: vector predicated instruction should be in VPT/VPST block -- `vldrwt.32 q0,\[r0\]'
|
||||
[^:]*:137: Error: instruction missing MVE vector predication code -- `vldrw.32 q0,\[r0\]'
|
||||
[^:]*:140: Error: bad element type for instruction -- `vldrb.16 q0,\[r2,q3\]'
|
||||
[^:]*:140: Error: bad element type for instruction -- `vldrb.32 q0,\[r2,q3\]'
|
||||
[^:]*:140: Error: bad element type for instruction -- `vldrb.64 q0,\[r2,q3\]'
|
||||
[^:]*:140: Error: bad element type for instruction -- `vldrb.f16 q0,\[r2,q3\]'
|
||||
[^:]*:140: Error: bad element type for instruction -- `vldrb.f32 q0,\[r2,q3\]'
|
||||
[^:]*:140: Error: bad element type for instruction -- `vldrb.f64 q0,\[r2,q3\]'
|
||||
[^:]*:140: Error: bad element type for instruction -- `vldrb.p16 q0,\[r2,q3\]'
|
||||
[^:]*:140: Error: bad element type for instruction -- `vldrb.p32 q0,\[r2,q3\]'
|
||||
[^:]*:140: Error: bad element type for instruction -- `vldrb.p64 q0,\[r2,q3\]'
|
||||
[^:]*:140: Error: bad element type for instruction -- `vldrb.s8 q0,\[r2,q3\]'
|
||||
[^:]*:143: Error: bad element type for instruction -- `vldrh.8 q0,\[r2,q3,uxtw#1\]'
|
||||
[^:]*:143: Error: bad element type for instruction -- `vldrh.32 q0,\[r2,q3,uxtw#1\]'
|
||||
[^:]*:143: Error: bad element type for instruction -- `vldrh.64 q0,\[r2,q3,uxtw#1\]'
|
||||
[^:]*:143: Error: bad element type for instruction -- `vldrh.f32 q0,\[r2,q3,uxtw#1\]'
|
||||
[^:]*:143: Error: bad element type for instruction -- `vldrh.f64 q0,\[r2,q3,uxtw#1\]'
|
||||
[^:]*:143: Error: bad element type for instruction -- `vldrh.p32 q0,\[r2,q3,uxtw#1\]'
|
||||
[^:]*:143: Error: bad element type for instruction -- `vldrh.p64 q0,\[r2,q3,uxtw#1\]'
|
||||
[^:]*:143: Error: bad element type for instruction -- `vldrh.s16 q0,\[r2,q3,uxtw#1\]'
|
||||
[^:]*:146: Error: bad element type for instruction -- `vldrw.8 q0,\[r2,q3,uxtw#2\]'
|
||||
[^:]*:146: Error: bad element type for instruction -- `vldrw.16 q0,\[r2,q3,uxtw#2\]'
|
||||
[^:]*:146: Error: bad element type for instruction -- `vldrw.64 q0,\[r2,q3,uxtw#2\]'
|
||||
[^:]*:146: Error: bad element type for instruction -- `vldrw.f16 q0,\[r2,q3,uxtw#2\]'
|
||||
[^:]*:146: Error: bad element type for instruction -- `vldrw.f64 q0,\[r2,q3,uxtw#2\]'
|
||||
[^:]*:146: Error: bad element type for instruction -- `vldrw.p16 q0,\[r2,q3,uxtw#2\]'
|
||||
[^:]*:146: Error: bad element type for instruction -- `vldrw.p64 q0,\[r2,q3,uxtw#2\]'
|
||||
[^:]*:146: Error: bad element type for instruction -- `vldrw.s32 q0,\[r2,q3,uxtw#2\]'
|
||||
[^:]*:149: Error: bad element type for instruction -- `vldrd.8 q0,\[r2,q3,uxtw#3\]'
|
||||
[^:]*:149: Error: bad element type for instruction -- `vldrd.16 q0,\[r2,q3,uxtw#3\]'
|
||||
[^:]*:149: Error: bad element type for instruction -- `vldrd.32 q0,\[r2,q3,uxtw#3\]'
|
||||
[^:]*:149: Error: bad element type for instruction -- `vldrd.f16 q0,\[r2,q3,uxtw#3\]'
|
||||
[^:]*:149: Error: bad element type for instruction -- `vldrd.f32 q0,\[r2,q3,uxtw#3\]'
|
||||
[^:]*:149: Error: bad element type for instruction -- `vldrd.p16 q0,\[r2,q3,uxtw#3\]'
|
||||
[^:]*:149: Error: bad element type for instruction -- `vldrd.p32 q0,\[r2,q3,uxtw#3\]'
|
||||
[^:]*:149: Error: bad element type for instruction -- `vldrd.s64 q0,\[r2,q3,uxtw#3\]'
|
||||
[^:]*:139: Error: bad element type for instruction -- `vldrb.16 q0,\[r2,q3\]'
|
||||
[^:]*:139: Error: bad element type for instruction -- `vldrb.32 q0,\[r2,q3\]'
|
||||
[^:]*:139: Error: bad element type for instruction -- `vldrb.64 q0,\[r2,q3\]'
|
||||
[^:]*:139: Error: bad element type for instruction -- `vldrb.f16 q0,\[r2,q3\]'
|
||||
[^:]*:139: Error: bad element type for instruction -- `vldrb.f32 q0,\[r2,q3\]'
|
||||
[^:]*:139: Error: bad element type for instruction -- `vldrb.f64 q0,\[r2,q3\]'
|
||||
[^:]*:139: Error: bad element type for instruction -- `vldrb.p16 q0,\[r2,q3\]'
|
||||
[^:]*:139: Error: bad element type for instruction -- `vldrb.p32 q0,\[r2,q3\]'
|
||||
[^:]*:139: Error: bad element type for instruction -- `vldrb.p64 q0,\[r2,q3\]'
|
||||
[^:]*:139: Error: bad element type for instruction -- `vldrb.s8 q0,\[r2,q3\]'
|
||||
[^:]*:142: Error: bad element type for instruction -- `vldrh.8 q0,\[r2,q3,uxtw#1\]'
|
||||
[^:]*:142: Error: bad element type for instruction -- `vldrh.32 q0,\[r2,q3,uxtw#1\]'
|
||||
[^:]*:142: Error: bad element type for instruction -- `vldrh.64 q0,\[r2,q3,uxtw#1\]'
|
||||
[^:]*:142: Error: bad element type for instruction -- `vldrh.f32 q0,\[r2,q3,uxtw#1\]'
|
||||
[^:]*:142: Error: bad element type for instruction -- `vldrh.f64 q0,\[r2,q3,uxtw#1\]'
|
||||
[^:]*:142: Error: bad element type for instruction -- `vldrh.p32 q0,\[r2,q3,uxtw#1\]'
|
||||
[^:]*:142: Error: bad element type for instruction -- `vldrh.p64 q0,\[r2,q3,uxtw#1\]'
|
||||
[^:]*:142: Error: bad element type for instruction -- `vldrh.s16 q0,\[r2,q3,uxtw#1\]'
|
||||
[^:]*:145: Error: bad element type for instruction -- `vldrw.8 q0,\[r2,q3,uxtw#2\]'
|
||||
[^:]*:145: Error: bad element type for instruction -- `vldrw.16 q0,\[r2,q3,uxtw#2\]'
|
||||
[^:]*:145: Error: bad element type for instruction -- `vldrw.64 q0,\[r2,q3,uxtw#2\]'
|
||||
[^:]*:145: Error: bad element type for instruction -- `vldrw.f16 q0,\[r2,q3,uxtw#2\]'
|
||||
[^:]*:145: Error: bad element type for instruction -- `vldrw.f64 q0,\[r2,q3,uxtw#2\]'
|
||||
[^:]*:145: Error: bad element type for instruction -- `vldrw.p16 q0,\[r2,q3,uxtw#2\]'
|
||||
[^:]*:145: Error: bad element type for instruction -- `vldrw.p64 q0,\[r2,q3,uxtw#2\]'
|
||||
[^:]*:145: Error: bad element type for instruction -- `vldrw.s32 q0,\[r2,q3,uxtw#2\]'
|
||||
[^:]*:148: Error: bad element type for instruction -- `vldrd.8 q0,\[r2,q3,uxtw#3\]'
|
||||
[^:]*:148: Error: bad element type for instruction -- `vldrd.16 q0,\[r2,q3,uxtw#3\]'
|
||||
[^:]*:148: Error: bad element type for instruction -- `vldrd.32 q0,\[r2,q3,uxtw#3\]'
|
||||
[^:]*:148: Error: bad element type for instruction -- `vldrd.f16 q0,\[r2,q3,uxtw#3\]'
|
||||
[^:]*:148: Error: bad element type for instruction -- `vldrd.f32 q0,\[r2,q3,uxtw#3\]'
|
||||
[^:]*:148: Error: bad element type for instruction -- `vldrd.p16 q0,\[r2,q3,uxtw#3\]'
|
||||
[^:]*:148: Error: bad element type for instruction -- `vldrd.p32 q0,\[r2,q3,uxtw#3\]'
|
||||
[^:]*:148: Error: bad element type for instruction -- `vldrd.s64 q0,\[r2,q3,uxtw#3\]'
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,7 +1,7 @@
|
||||
[^:]*: Assembler messages:
|
||||
[^:]*:4: Error: bad type in SIMD instruction -- `vqdmlah.u8 q1,q2,r0'
|
||||
[^:]*:4: Error: bad type in SIMD instruction -- `vqrdmlah.u8 q3,q4,r5'
|
||||
[^:]*:4: Error: bad type in SIMD instruction -- `vqdmlah.u16 q1,q2,r0'
|
||||
[^:]*:4: Error: bad type in SIMD instruction -- `vqrdmlah.u16 q3,q4,r5'
|
||||
[^:]*:4: Error: bad type in SIMD instruction -- `vqdmlah.u32 q1,q2,r0'
|
||||
[^:]*:4: Error: bad type in SIMD instruction -- `vqrdmlah.u32 q3,q4,r5'
|
||||
[^:]*:2: Error: bad type in SIMD instruction -- `vqdmlah.u8 q1,q2,r0'
|
||||
[^:]*:3: Error: bad type in SIMD instruction -- `vqrdmlah.u8 q3,q4,r5'
|
||||
[^:]*:2: Error: bad type in SIMD instruction -- `vqdmlah.u16 q1,q2,r0'
|
||||
[^:]*:3: Error: bad type in SIMD instruction -- `vqrdmlah.u16 q3,q4,r5'
|
||||
[^:]*:2: Error: bad type in SIMD instruction -- `vqdmlah.u32 q1,q2,r0'
|
||||
[^:]*:3: Error: bad type in SIMD instruction -- `vqrdmlah.u32 q3,q4,r5'
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
[^:]*: Assembler messages:
|
||||
[^:]*:4: Error: bad type in SIMD instruction -- `vqdmlash.u8 q0,q2,r0'
|
||||
[^:]*:4: Error: bad type in SIMD instruction -- `vqrdmlash.u8 q1,q3,r1'
|
||||
[^:]*:4: Error: bad type in SIMD instruction -- `vqdmlash.u16 q0,q2,r0'
|
||||
[^:]*:4: Error: bad type in SIMD instruction -- `vqrdmlash.u16 q1,q3,r1'
|
||||
[^:]*:4: Error: bad type in SIMD instruction -- `vqdmlash.u32 q0,q2,r0'
|
||||
[^:]*:4: Error: bad type in SIMD instruction -- `vqrdmlash.u32 q1,q3,r1'
|
||||
[^:]*:2: Error: bad type in SIMD instruction -- `vqdmlash.u8 q0,q2,r0'
|
||||
[^:]*:3: Error: bad type in SIMD instruction -- `vqrdmlash.u8 q1,q3,r1'
|
||||
[^:]*:2: Error: bad type in SIMD instruction -- `vqdmlash.u16 q0,q2,r0'
|
||||
[^:]*:3: Error: bad type in SIMD instruction -- `vqrdmlash.u16 q1,q3,r1'
|
||||
[^:]*:2: Error: bad type in SIMD instruction -- `vqdmlash.u32 q0,q2,r0'
|
||||
[^:]*:3: Error: bad type in SIMD instruction -- `vqrdmlash.u32 q1,q3,r1'
|
||||
|
||||
@ -1,80 +1,80 @@
|
||||
[^:]*: Assembler messages:
|
||||
[^:]*:13: Error: bad type in SIMD instruction -- `vrintn.i16 q0,q1'
|
||||
[^:]*:13: Error: bad type in SIMD instruction -- `vrintn.f64 q0,q1'
|
||||
[^:]*:13: Error: bad type in SIMD instruction -- `vrintx.i16 q0,q1'
|
||||
[^:]*:13: Error: bad type in SIMD instruction -- `vrintx.f64 q0,q1'
|
||||
[^:]*:13: Error: bad type in SIMD instruction -- `vrinta.i16 q0,q1'
|
||||
[^:]*:13: Error: bad type in SIMD instruction -- `vrinta.f64 q0,q1'
|
||||
[^:]*:13: Error: bad type in SIMD instruction -- `vrintz.i16 q0,q1'
|
||||
[^:]*:13: Error: bad type in SIMD instruction -- `vrintz.f64 q0,q1'
|
||||
[^:]*:13: Error: bad type in SIMD instruction -- `vrintm.i16 q0,q1'
|
||||
[^:]*:13: Error: bad type in SIMD instruction -- `vrintm.f64 q0,q1'
|
||||
[^:]*:13: Error: bad type in SIMD instruction -- `vrintp.i16 q0,q1'
|
||||
[^:]*:13: Error: bad type in SIMD instruction -- `vrintp.f64 q0,q1'
|
||||
[^:]*:11: Error: bad type in SIMD instruction -- `vrintn.i16 q0,q1'
|
||||
[^:]*:12: Error: bad type in SIMD instruction -- `vrintn.f64 q0,q1'
|
||||
[^:]*:11: Error: bad type in SIMD instruction -- `vrintx.i16 q0,q1'
|
||||
[^:]*:12: Error: bad type in SIMD instruction -- `vrintx.f64 q0,q1'
|
||||
[^:]*:11: Error: bad type in SIMD instruction -- `vrinta.i16 q0,q1'
|
||||
[^:]*:12: Error: bad type in SIMD instruction -- `vrinta.f64 q0,q1'
|
||||
[^:]*:11: Error: bad type in SIMD instruction -- `vrintz.i16 q0,q1'
|
||||
[^:]*:12: Error: bad type in SIMD instruction -- `vrintz.f64 q0,q1'
|
||||
[^:]*:11: Error: bad type in SIMD instruction -- `vrintm.i16 q0,q1'
|
||||
[^:]*:12: Error: bad type in SIMD instruction -- `vrintm.f64 q0,q1'
|
||||
[^:]*:11: Error: bad type in SIMD instruction -- `vrintp.i16 q0,q1'
|
||||
[^:]*:12: Error: bad type in SIMD instruction -- `vrintp.f64 q0,q1'
|
||||
[^:]*:14: Error: VFP single, double or Neon quad precision register expected -- `vrintr.f16 q0,q1'
|
||||
[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:25: Error: syntax error -- `vrintneq.f16 q0,q1'
|
||||
[^:]*:25: Error: syntax error -- `vrintneq.f16 q0,q1'
|
||||
[^:]*:25: Error: syntax error -- `vrintneq.f16 q0,q1'
|
||||
[^:]*:25: Error: vector predicated instruction should be in VPT/VPST block -- `vrintnt.f16 q0,q1'
|
||||
[^:]*:25: Error: instruction missing MVE vector predication code -- `vrintn.f16 q0,q1'
|
||||
[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:25: Error: syntax error -- `vrintxeq.f16 q0,q1'
|
||||
[^:]*:25: Error: syntax error -- `vrintxeq.f16 q0,q1'
|
||||
[^:]*:25: Error: syntax error -- `vrintxeq.f16 q0,q1'
|
||||
[^:]*:25: Error: vector predicated instruction should be in VPT/VPST block -- `vrintxt.f16 q0,q1'
|
||||
[^:]*:25: Error: instruction missing MVE vector predication code -- `vrintx.f16 q0,q1'
|
||||
[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:25: Error: syntax error -- `vrintaeq.f16 q0,q1'
|
||||
[^:]*:25: Error: syntax error -- `vrintaeq.f16 q0,q1'
|
||||
[^:]*:25: Error: syntax error -- `vrintaeq.f16 q0,q1'
|
||||
[^:]*:25: Error: vector predicated instruction should be in VPT/VPST block -- `vrintat.f16 q0,q1'
|
||||
[^:]*:25: Error: instruction missing MVE vector predication code -- `vrinta.f16 q0,q1'
|
||||
[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:25: Error: syntax error -- `vrintzeq.f16 q0,q1'
|
||||
[^:]*:25: Error: syntax error -- `vrintzeq.f16 q0,q1'
|
||||
[^:]*:25: Error: syntax error -- `vrintzeq.f16 q0,q1'
|
||||
[^:]*:25: Error: vector predicated instruction should be in VPT/VPST block -- `vrintzt.f16 q0,q1'
|
||||
[^:]*:25: Error: instruction missing MVE vector predication code -- `vrintz.f16 q0,q1'
|
||||
[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:25: Error: syntax error -- `vrintmeq.f16 q0,q1'
|
||||
[^:]*:25: Error: syntax error -- `vrintmeq.f16 q0,q1'
|
||||
[^:]*:25: Error: syntax error -- `vrintmeq.f16 q0,q1'
|
||||
[^:]*:25: Error: vector predicated instruction should be in VPT/VPST block -- `vrintmt.f16 q0,q1'
|
||||
[^:]*:25: Error: instruction missing MVE vector predication code -- `vrintm.f16 q0,q1'
|
||||
[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:25: Error: syntax error -- `vrintpeq.f16 q0,q1'
|
||||
[^:]*:25: Error: syntax error -- `vrintpeq.f16 q0,q1'
|
||||
[^:]*:25: Error: syntax error -- `vrintpeq.f16 q0,q1'
|
||||
[^:]*:25: Error: vector predicated instruction should be in VPT/VPST block -- `vrintpt.f16 q0,q1'
|
||||
[^:]*:25: Error: instruction missing MVE vector predication code -- `vrintp.f16 q0,q1'
|
||||
[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:18: Error: syntax error -- `vrintneq.f16 q0,q1'
|
||||
[^:]*:19: Error: syntax error -- `vrintneq.f16 q0,q1'
|
||||
[^:]*:21: Error: syntax error -- `vrintneq.f16 q0,q1'
|
||||
[^:]*:22: Error: vector predicated instruction should be in VPT/VPST block -- `vrintnt.f16 q0,q1'
|
||||
[^:]*:24: Error: instruction missing MVE vector predication code -- `vrintn.f16 q0,q1'
|
||||
[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:18: Error: syntax error -- `vrintxeq.f16 q0,q1'
|
||||
[^:]*:19: Error: syntax error -- `vrintxeq.f16 q0,q1'
|
||||
[^:]*:21: Error: syntax error -- `vrintxeq.f16 q0,q1'
|
||||
[^:]*:22: Error: vector predicated instruction should be in VPT/VPST block -- `vrintxt.f16 q0,q1'
|
||||
[^:]*:24: Error: instruction missing MVE vector predication code -- `vrintx.f16 q0,q1'
|
||||
[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:18: Error: syntax error -- `vrintaeq.f16 q0,q1'
|
||||
[^:]*:19: Error: syntax error -- `vrintaeq.f16 q0,q1'
|
||||
[^:]*:21: Error: syntax error -- `vrintaeq.f16 q0,q1'
|
||||
[^:]*:22: Error: vector predicated instruction should be in VPT/VPST block -- `vrintat.f16 q0,q1'
|
||||
[^:]*:24: Error: instruction missing MVE vector predication code -- `vrinta.f16 q0,q1'
|
||||
[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:18: Error: syntax error -- `vrintzeq.f16 q0,q1'
|
||||
[^:]*:19: Error: syntax error -- `vrintzeq.f16 q0,q1'
|
||||
[^:]*:21: Error: syntax error -- `vrintzeq.f16 q0,q1'
|
||||
[^:]*:22: Error: vector predicated instruction should be in VPT/VPST block -- `vrintzt.f16 q0,q1'
|
||||
[^:]*:24: Error: instruction missing MVE vector predication code -- `vrintz.f16 q0,q1'
|
||||
[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:18: Error: syntax error -- `vrintmeq.f16 q0,q1'
|
||||
[^:]*:19: Error: syntax error -- `vrintmeq.f16 q0,q1'
|
||||
[^:]*:21: Error: syntax error -- `vrintmeq.f16 q0,q1'
|
||||
[^:]*:22: Error: vector predicated instruction should be in VPT/VPST block -- `vrintmt.f16 q0,q1'
|
||||
[^:]*:24: Error: instruction missing MVE vector predication code -- `vrintm.f16 q0,q1'
|
||||
[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:18: Error: syntax error -- `vrintpeq.f16 q0,q1'
|
||||
[^:]*:19: Error: syntax error -- `vrintpeq.f16 q0,q1'
|
||||
[^:]*:21: Error: syntax error -- `vrintpeq.f16 q0,q1'
|
||||
[^:]*:22: Error: vector predicated instruction should be in VPT/VPST block -- `vrintpt.f16 q0,q1'
|
||||
[^:]*:24: Error: instruction missing MVE vector predication code -- `vrintp.f16 q0,q1'
|
||||
|
||||
@ -68,6 +68,20 @@ Raw dump of debug contents .*
|
||||
.*Advance PC by .*
|
||||
.*Extended opcode 1: End of Sequence
|
||||
|
||||
.*Extended opcode 2: .*
|
||||
.*Advance Line by 41 to 42
|
||||
.*Copy
|
||||
.*Special opcode .* and Line by 1 to 43
|
||||
.*Advance PC by .*
|
||||
.*Extended opcode 1: End of Sequence
|
||||
|
||||
.*Extended opcode 2: .*
|
||||
.*Advance Line by 41 to 42
|
||||
.*Copy
|
||||
.*Special opcode .* and Line by 1 to 43
|
||||
.*Advance PC by .*
|
||||
.*Extended opcode 1: End of Sequence
|
||||
|
||||
|
||||
Contents of the \.debug_aranges section:
|
||||
|
||||
@ -84,6 +98,8 @@ Contents of the \.debug_aranges section:
|
||||
0+ [0-9a-f]+ ?
|
||||
0+ [0-9a-f]+ ?
|
||||
0+ [0-9a-f]+ ?
|
||||
0+ [0-9a-f]+ ?
|
||||
0+ [0-9a-f]+ ?
|
||||
0+ 0+ ?
|
||||
|
||||
Contents of the \.debug_rnglists section:
|
||||
@ -95,6 +111,8 @@ Contents of the \.debug_rnglists section:
|
||||
[0-9a-f]+ 0+ [0-9a-f]+ ?
|
||||
[0-9a-f]+ 0+ [0-9a-f]+ ?
|
||||
[0-9a-f]+ 0+ [0-9a-f]+ ?
|
||||
[0-9a-f]+ 0+ [0-9a-f]+ ?
|
||||
[0-9a-f]+ 0+ [0-9a-f]+ ?
|
||||
[0-9a-f]+ <End of list>
|
||||
|
||||
#pass
|
||||
|
||||
@ -36,3 +36,9 @@ _start:
|
||||
.nop
|
||||
.nop
|
||||
.endr
|
||||
|
||||
.irp n, ef, kl
|
||||
.section .text.\n, "ax"
|
||||
.nop
|
||||
.nop
|
||||
.endr
|
||||
|
||||
@ -312,6 +312,16 @@ if { [is_elf_format] } then {
|
||||
run_dump_test "dwarf-5-func" $dump_opts
|
||||
run_dump_test "dwarf-5-func-global" $dump_opts
|
||||
run_dump_test "dwarf-5-func-local" $dump_opts
|
||||
|
||||
# Exclude targets defining ONLY_STANDARD_ESCAPES. It's not clear how these
|
||||
# are supposed to reference macro arguments in double-quoted strings.
|
||||
if { ![istarget "avr-*-*"]
|
||||
&& ![istarget "cris*-*-*"]
|
||||
&& ![istarget "msp430-*-*"]
|
||||
&& ![istarget "z80-*-*"] } then {
|
||||
run_list_test line
|
||||
}
|
||||
|
||||
run_dump_test "pr25917"
|
||||
run_dump_test "bss"
|
||||
run_dump_test "bad-bss"
|
||||
|
||||
30
gas/testsuite/gas/elf/line.l
Normal file
30
gas/testsuite/gas/elf/line.l
Normal file
@ -0,0 +1,30 @@
|
||||
# This should match the warnings when assembling line.s.
|
||||
|
||||
.*: Assembler messages:
|
||||
line\.s:[0-9]*18: Warning: \.warning .*
|
||||
line\.s:[0-9]*: Warning: m1/1: 123
|
||||
line\.s:[0-9]*: Warning: m1/2: 123
|
||||
line\.s:[0-9]*: Warning: m1/1: abc
|
||||
line\.s:[0-9]*: Warning: m1/2: abc
|
||||
line\.s:[0-9]*: Warning: m1/1: XYZ
|
||||
line\.s:[0-9]*: Warning: m1/2: XYZ
|
||||
line\.s:[0-9]*24: Warning: \.warning .*
|
||||
Line\.s:10: Warning: m2/1: 987
|
||||
Line\.s:12: Warning: m2/2: 987
|
||||
Line\.s:10: Warning: m2/1: zyx
|
||||
Line\.s:12: Warning: m2/2: zyx
|
||||
Line\.s:10: Warning: m2/1: CBA
|
||||
Line\.s:12: Warning: m2/2: CBA
|
||||
line\.s:[0-9]*29: Warning: \.warning .*
|
||||
line\.s:[0-9]*35: Warning: irp/1: 123
|
||||
line\.s:[0-9]*37: Warning: irp/2: 123
|
||||
line\.s:[0-9]*35: Warning: irp/1: 456
|
||||
line\.s:[0-9]*37: Warning: irp/2: 456
|
||||
line\.s:[0-9]*39: Warning: \.warning .*
|
||||
line\.s:[0-9]*45: Warning: rept/1
|
||||
line\.s:[0-9]*47: Warning: rept/2
|
||||
line\.s:[0-9]*45: Warning: rept/1
|
||||
line\.s:[0-9]*47: Warning: rept/2
|
||||
line\.s:[0-9]*45: Warning: rept/1
|
||||
line\.s:[0-9]*47: Warning: rept/2
|
||||
line\.s:[0-9]*49: Warning: \.warning .*
|
||||
49
gas/testsuite/gas/elf/line.s
Normal file
49
gas/testsuite/gas/elf/line.s
Normal file
@ -0,0 +1,49 @@
|
||||
.macro m1 args:vararg
|
||||
.warning "m1/1: \args"
|
||||
.nop
|
||||
.warning "m1/2: \args"
|
||||
.endm
|
||||
|
||||
.macro m2 args:vararg
|
||||
.file "Line.s"
|
||||
.line 9
|
||||
.warning "m2/1: \args"
|
||||
.nop
|
||||
.warning "m2/2: \args"
|
||||
.endm
|
||||
|
||||
.text
|
||||
|
||||
# 10018 "line.s"
|
||||
.warning
|
||||
|
||||
macro:
|
||||
m1 123
|
||||
m1 abc
|
||||
m1 XYZ
|
||||
.warning
|
||||
|
||||
m2 987
|
||||
m2 zyx
|
||||
m2 CBA
|
||||
.warning
|
||||
|
||||
# 20032 "line.s"
|
||||
|
||||
irp:
|
||||
.irp arg, 123, 456
|
||||
.warning "irp/1: \arg"
|
||||
.nop
|
||||
.warning "irp/2: \arg"
|
||||
.endr
|
||||
.warning
|
||||
|
||||
# 30042 "line.s"
|
||||
|
||||
rept:
|
||||
.rept 3
|
||||
.warning "rept/1"
|
||||
.nop
|
||||
.warning "rept/2"
|
||||
.endr
|
||||
.warning
|
||||
@ -6,5 +6,5 @@
|
||||
|
||||
Main SWYM 0
|
||||
.rept 223
|
||||
GREG
|
||||
.endr % { dg-error "too many GREG registers allocated" "" }
|
||||
GREG % { dg-error "too many GREG registers allocated" "" }
|
||||
.endr
|
||||
|
||||
Loading…
Reference in New Issue
Block a user