gas: bpf: fix tests for pseudo-c syntax

This patch fixes the GAS BPF testsuite so the tests for pseudo-c
syntax are actually executed.

2023-04-27  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* testsuite/gas/bpf/mem.dump: New file.
	* testsuite/gas/bpf/mem-pseudoc.d: Likewise.
	* testsuite/gas/bpf/mem.d: #dump mem.dump.
	* testsuite/gas/bpf/lddw.dump: New file.
	* testsuite/gas/bpf/lddw-pseudoc.d: Likewise.
	* testsuite/gas/bpf/lddw.d: #dump lddw.dump.
	* testsuite/gas/bpf/jump.dump: New file.
	* testsuite/gas/bpf/jump-pseudoc.d: Likewise
	* testsuite/gas/bpf/jump.d: #dump jump.dump.
	* testsuite/gas/bpf/jump32.dump: New file.
	* testsuite/gas/bpf/jump32-pseudoc.d: Likewise.
	* testsuite/gas/bpf/jump32.d: #dump jump32.dump.
	* testsuite/gas/bpf/lddw-be.dump: New file.
	* testsuite/gas/bpf/lddw-be-pseudoc.d: Likewise.
	* testsuite/gas/bpf/lddw-be.d: #dump lddw-be.dump.
	* testsuite/gas/bpf/indcall-1.dump: New file.
	* testsuite/gas/bpf/indcall-1-pseudoc.d: Likewise.
	* testsuite/gas/bpf/indcall-1.d: #dump indcall-1.dump.
	* testsuite/gas/bpf/indcall-1-pseudoc.s (main): Fix lddw
	instruction.
	* testsuite/gas/bpf/atomic.dump: New file.
	* testsuite/gas/bpf/atomic-pseudoc.d: Likewise.
	* testsuite/gas/bpf/atomic.d: #dump atomic.dump.
	* testsuite/gas/bpf/alu32.dump: New file.
	* testsuite/gas/bpf/alu32-pseudoc.d: Likewise.
	* testsuite/gas/bpf/alu32.d: #dump alu32.dump.
	* testsuite/gas/bpf/alu.dump: New file.
	* testsuite/gas/bpf/alu-pseudoc.d: Likewise.
	* testsuite/gas/bpf/alu.d: #dump alu.dump.

	* testsuite/gas/bpf/alu-be.dump: New file.
	* testsuite/gas/bpf/alu-be-pseudoc.d: Likewise.
	* testsuite/gas/bpf/alu-be.d: #dump alu-be.dump.
	* testsuite/gas/bpf/alu32-be-pseudoc.d: New file.
	* testsuite/gas/bpf/alu32-be-dump: Likewise.
	* testsuite/gas/bpf/alu32-be.d: #dump alu32-be-dump.
	* testsuite/gas/bpf/bpf.exp: Run *-pseudoc tests.
This commit is contained in:
Jose E. Marchesi 2023-04-27 20:05:19 +02:00
parent e29ff7211b
commit 2b8c7766ea
36 changed files with 489 additions and 392 deletions

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@ -1,3 +1,43 @@
2023-04-27 Jose E. Marchesi <jose.marchesi@oracle.com>
* testsuite/gas/bpf/mem.dump: New file.
* testsuite/gas/bpf/mem-pseudoc.d: Likewise.
* testsuite/gas/bpf/mem.d: #dump mem.dump.
* testsuite/gas/bpf/lddw.dump: New file.
* testsuite/gas/bpf/lddw-pseudoc.d: Likewise.
* testsuite/gas/bpf/lddw.d: #dump lddw.dump.
* testsuite/gas/bpf/jump.dump: New file.
* testsuite/gas/bpf/jump-pseudoc.d: Likewise
* testsuite/gas/bpf/jump.d: #dump jump.dump.
* testsuite/gas/bpf/jump32.dump: New file.
* testsuite/gas/bpf/jump32-pseudoc.d: Likewise.
* testsuite/gas/bpf/jump32.d: #dump jump32.dump.
* testsuite/gas/bpf/lddw-be.dump: New file.
* testsuite/gas/bpf/lddw-be-pseudoc.d: Likewise.
* testsuite/gas/bpf/lddw-be.d: #dump lddw-be.dump.
* testsuite/gas/bpf/indcall-1.dump: New file.
* testsuite/gas/bpf/indcall-1-pseudoc.d: Likewise.
* testsuite/gas/bpf/indcall-1.d: #dump indcall-1.dump.
* testsuite/gas/bpf/indcall-1-pseudoc.s (main): Fix lddw
instruction.
* testsuite/gas/bpf/atomic.dump: New file.
* testsuite/gas/bpf/atomic-pseudoc.d: Likewise.
* testsuite/gas/bpf/atomic.d: #dump atomic.dump.
* testsuite/gas/bpf/alu32.dump: New file.
* testsuite/gas/bpf/alu32-pseudoc.d: Likewise.
* testsuite/gas/bpf/alu32.d: #dump alu32.dump.
* testsuite/gas/bpf/alu.dump: New file.
* testsuite/gas/bpf/alu-pseudoc.d: Likewise.
* testsuite/gas/bpf/alu.d: #dump alu.dump.
* testsuite/gas/bpf/alu-be.dump: New file.
* testsuite/gas/bpf/alu-be-pseudoc.d: Likewise.
* testsuite/gas/bpf/alu-be.d: #dump alu-be.dump.
* testsuite/gas/bpf/alu32-be-pseudoc.d: New file.
* testsuite/gas/bpf/alu32-be-dump: Likewise.
* testsuite/gas/bpf/alu32-be.d: #dump alu32-be-dump.
* testsuite/gas/bpf/bpf.exp: Run *-pseudoc tests.
2023-04-19 Jose E. Marchesi <jose.marchesi@oracle.com>
PR gas/29757

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#as: --EB
#source: alu-pseudoc.s
#objdump: -dr
#dump: alu-be.dump
#name: eBPF ALU64 instructions, big endian, pseudoc syntax

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@ -1,60 +1,5 @@
#as: --EB
#source: alu.s
#source: alu-pseudoc.s
#objdump: -dr
#name: eBPF ALU64 instructions, big endian
.*: +file format .*bpf.*
Disassembly of section .text:
0+ <.text>:
0: 07 20 00 00 00 00 02 9a add %r2,0x29a
8: 07 30 00 00 ff ff fd 66 add %r3,-666
10: 07 40 00 00 7e ad be ef add %r4,0x7eadbeef
18: 0f 56 00 00 00 00 00 00 add %r5,%r6
20: 17 20 00 00 00 00 02 9a sub %r2,0x29a
28: 17 30 00 00 ff ff fd 66 sub %r3,-666
30: 17 40 00 00 7e ad be ef sub %r4,0x7eadbeef
38: 1f 56 00 00 00 00 00 00 sub %r5,%r6
40: 27 20 00 00 00 00 02 9a mul %r2,0x29a
48: 27 30 00 00 ff ff fd 66 mul %r3,-666
50: 27 40 00 00 7e ad be ef mul %r4,0x7eadbeef
58: 2f 56 00 00 00 00 00 00 mul %r5,%r6
60: 37 20 00 00 00 00 02 9a div %r2,0x29a
68: 37 30 00 00 ff ff fd 66 div %r3,-666
70: 37 40 00 00 7e ad be ef div %r4,0x7eadbeef
78: 3f 56 00 00 00 00 00 00 div %r5,%r6
80: 47 20 00 00 00 00 02 9a or %r2,0x29a
88: 47 30 00 00 ff ff fd 66 or %r3,-666
90: 47 40 00 00 7e ad be ef or %r4,0x7eadbeef
98: 4f 56 00 00 00 00 00 00 or %r5,%r6
a0: 57 20 00 00 00 00 02 9a and %r2,0x29a
a8: 57 30 00 00 ff ff fd 66 and %r3,-666
b0: 57 40 00 00 7e ad be ef and %r4,0x7eadbeef
b8: 5f 56 00 00 00 00 00 00 and %r5,%r6
c0: 67 20 00 00 00 00 02 9a lsh %r2,0x29a
c8: 67 30 00 00 ff ff fd 66 lsh %r3,-666
d0: 67 40 00 00 7e ad be ef lsh %r4,0x7eadbeef
d8: 6f 56 00 00 00 00 00 00 lsh %r5,%r6
e0: 77 20 00 00 00 00 02 9a rsh %r2,0x29a
e8: 77 30 00 00 ff ff fd 66 rsh %r3,-666
f0: 77 40 00 00 7e ad be ef rsh %r4,0x7eadbeef
f8: 7f 56 00 00 00 00 00 00 rsh %r5,%r6
100: 97 20 00 00 00 00 02 9a mod %r2,0x29a
108: 97 30 00 00 ff ff fd 66 mod %r3,-666
110: 97 40 00 00 7e ad be ef mod %r4,0x7eadbeef
118: 9f 56 00 00 00 00 00 00 mod %r5,%r6
120: a7 20 00 00 00 00 02 9a xor %r2,0x29a
128: a7 30 00 00 ff ff fd 66 xor %r3,-666
130: a7 40 00 00 7e ad be ef xor %r4,0x7eadbeef
138: af 56 00 00 00 00 00 00 xor %r5,%r6
140: b7 20 00 00 00 00 02 9a mov %r2,0x29a
148: b7 30 00 00 ff ff fd 66 mov %r3,-666
150: b7 40 00 00 7e ad be ef mov %r4,0x7eadbeef
158: bf 56 00 00 00 00 00 00 mov %r5,%r6
160: c7 20 00 00 00 00 02 9a arsh %r2,0x29a
168: c7 30 00 00 ff ff fd 66 arsh %r3,-666
170: c7 40 00 00 7e ad be ef arsh %r4,0x7eadbeef
178: cf 56 00 00 00 00 00 00 arsh %r5,%r6
180: 87 20 00 00 00 00 00 00 neg %r2
#dump: alu-be.dump
#name: eBPF ALU64 instructions, big endian, normal syntax

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.*: +file format .*bpf.*
Disassembly of section .text:
0+ <.text>:
0: 07 20 00 00 00 00 02 9a add %r2,0x29a
8: 07 30 00 00 ff ff fd 66 add %r3,-666
10: 07 40 00 00 7e ad be ef add %r4,0x7eadbeef
18: 0f 56 00 00 00 00 00 00 add %r5,%r6
20: 17 20 00 00 00 00 02 9a sub %r2,0x29a
28: 17 30 00 00 ff ff fd 66 sub %r3,-666
30: 17 40 00 00 7e ad be ef sub %r4,0x7eadbeef
38: 1f 56 00 00 00 00 00 00 sub %r5,%r6
40: 27 20 00 00 00 00 02 9a mul %r2,0x29a
48: 27 30 00 00 ff ff fd 66 mul %r3,-666
50: 27 40 00 00 7e ad be ef mul %r4,0x7eadbeef
58: 2f 56 00 00 00 00 00 00 mul %r5,%r6
60: 37 20 00 00 00 00 02 9a div %r2,0x29a
68: 37 30 00 00 ff ff fd 66 div %r3,-666
70: 37 40 00 00 7e ad be ef div %r4,0x7eadbeef
78: 3f 56 00 00 00 00 00 00 div %r5,%r6
80: 47 20 00 00 00 00 02 9a or %r2,0x29a
88: 47 30 00 00 ff ff fd 66 or %r3,-666
90: 47 40 00 00 7e ad be ef or %r4,0x7eadbeef
98: 4f 56 00 00 00 00 00 00 or %r5,%r6
a0: 57 20 00 00 00 00 02 9a and %r2,0x29a
a8: 57 30 00 00 ff ff fd 66 and %r3,-666
b0: 57 40 00 00 7e ad be ef and %r4,0x7eadbeef
b8: 5f 56 00 00 00 00 00 00 and %r5,%r6
c0: 67 20 00 00 00 00 02 9a lsh %r2,0x29a
c8: 67 30 00 00 ff ff fd 66 lsh %r3,-666
d0: 67 40 00 00 7e ad be ef lsh %r4,0x7eadbeef
d8: 6f 56 00 00 00 00 00 00 lsh %r5,%r6
e0: 77 20 00 00 00 00 02 9a rsh %r2,0x29a
e8: 77 30 00 00 ff ff fd 66 rsh %r3,-666
f0: 77 40 00 00 7e ad be ef rsh %r4,0x7eadbeef
f8: 7f 56 00 00 00 00 00 00 rsh %r5,%r6
100: 97 20 00 00 00 00 02 9a mod %r2,0x29a
108: 97 30 00 00 ff ff fd 66 mod %r3,-666
110: 97 40 00 00 7e ad be ef mod %r4,0x7eadbeef
118: 9f 56 00 00 00 00 00 00 mod %r5,%r6
120: a7 20 00 00 00 00 02 9a xor %r2,0x29a
128: a7 30 00 00 ff ff fd 66 xor %r3,-666
130: a7 40 00 00 7e ad be ef xor %r4,0x7eadbeef
138: af 56 00 00 00 00 00 00 xor %r5,%r6
140: b7 20 00 00 00 00 02 9a mov %r2,0x29a
148: b7 30 00 00 ff ff fd 66 mov %r3,-666
150: b7 40 00 00 7e ad be ef mov %r4,0x7eadbeef
158: bf 56 00 00 00 00 00 00 mov %r5,%r6
160: c7 20 00 00 00 00 02 9a arsh %r2,0x29a
168: c7 30 00 00 ff ff fd 66 arsh %r3,-666
170: c7 40 00 00 7e ad be ef arsh %r4,0x7eadbeef
178: cf 56 00 00 00 00 00 00 arsh %r5,%r6
180: 87 20 00 00 00 00 00 00 neg %r2

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#as: --EL
#objdump: -dr
#source: alu-pseudoc.s
#dump: alu.dump
#name: eBPF ALU64 instructions, pseudo-c syntax

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@ -1,58 +1,5 @@
#as: --EL
#objdump: -dr
#name: eBPF ALU64 instructions
.*: +file format .*bpf.*
Disassembly of section .text:
0+ <.text>:
0: 07 02 00 00 9a 02 00 00 add %r2,0x29a
8: 07 03 00 00 66 fd ff ff add %r3,-666
10: 07 04 00 00 ef be ad 7e add %r4,0x7eadbeef
18: 0f 65 00 00 00 00 00 00 add %r5,%r6
20: 17 02 00 00 9a 02 00 00 sub %r2,0x29a
28: 17 03 00 00 66 fd ff ff sub %r3,-666
30: 17 04 00 00 ef be ad 7e sub %r4,0x7eadbeef
38: 1f 65 00 00 00 00 00 00 sub %r5,%r6
40: 27 02 00 00 9a 02 00 00 mul %r2,0x29a
48: 27 03 00 00 66 fd ff ff mul %r3,-666
50: 27 04 00 00 ef be ad 7e mul %r4,0x7eadbeef
58: 2f 65 00 00 00 00 00 00 mul %r5,%r6
60: 37 02 00 00 9a 02 00 00 div %r2,0x29a
68: 37 03 00 00 66 fd ff ff div %r3,-666
70: 37 04 00 00 ef be ad 7e div %r4,0x7eadbeef
78: 3f 65 00 00 00 00 00 00 div %r5,%r6
80: 47 02 00 00 9a 02 00 00 or %r2,0x29a
88: 47 03 00 00 66 fd ff ff or %r3,-666
90: 47 04 00 00 ef be ad 7e or %r4,0x7eadbeef
98: 4f 65 00 00 00 00 00 00 or %r5,%r6
a0: 57 02 00 00 9a 02 00 00 and %r2,0x29a
a8: 57 03 00 00 66 fd ff ff and %r3,-666
b0: 57 04 00 00 ef be ad 7e and %r4,0x7eadbeef
b8: 5f 65 00 00 00 00 00 00 and %r5,%r6
c0: 67 02 00 00 9a 02 00 00 lsh %r2,0x29a
c8: 67 03 00 00 66 fd ff ff lsh %r3,-666
d0: 67 04 00 00 ef be ad 7e lsh %r4,0x7eadbeef
d8: 6f 65 00 00 00 00 00 00 lsh %r5,%r6
e0: 77 02 00 00 9a 02 00 00 rsh %r2,0x29a
e8: 77 03 00 00 66 fd ff ff rsh %r3,-666
f0: 77 04 00 00 ef be ad 7e rsh %r4,0x7eadbeef
f8: 7f 65 00 00 00 00 00 00 rsh %r5,%r6
100: 97 02 00 00 9a 02 00 00 mod %r2,0x29a
108: 97 03 00 00 66 fd ff ff mod %r3,-666
110: 97 04 00 00 ef be ad 7e mod %r4,0x7eadbeef
118: 9f 65 00 00 00 00 00 00 mod %r5,%r6
120: a7 02 00 00 9a 02 00 00 xor %r2,0x29a
128: a7 03 00 00 66 fd ff ff xor %r3,-666
130: a7 04 00 00 ef be ad 7e xor %r4,0x7eadbeef
138: af 65 00 00 00 00 00 00 xor %r5,%r6
140: b7 02 00 00 9a 02 00 00 mov %r2,0x29a
148: b7 03 00 00 66 fd ff ff mov %r3,-666
150: b7 04 00 00 ef be ad 7e mov %r4,0x7eadbeef
158: bf 65 00 00 00 00 00 00 mov %r5,%r6
160: c7 02 00 00 9a 02 00 00 arsh %r2,0x29a
168: c7 03 00 00 66 fd ff ff arsh %r3,-666
170: c7 04 00 00 ef be ad 7e arsh %r4,0x7eadbeef
178: cf 65 00 00 00 00 00 00 arsh %r5,%r6
180: 87 02 00 00 00 00 00 00 neg %r2
#source: alu.s
#dump: alu.dump
#name: eBPF ALU64 instructions, normal syntax

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.*: +file format .*bpf.*
Disassembly of section .text:
0+ <.text>:
0: 07 02 00 00 9a 02 00 00 add %r2,0x29a
8: 07 03 00 00 66 fd ff ff add %r3,-666
10: 07 04 00 00 ef be ad 7e add %r4,0x7eadbeef
18: 0f 65 00 00 00 00 00 00 add %r5,%r6
20: 17 02 00 00 9a 02 00 00 sub %r2,0x29a
28: 17 03 00 00 66 fd ff ff sub %r3,-666
30: 17 04 00 00 ef be ad 7e sub %r4,0x7eadbeef
38: 1f 65 00 00 00 00 00 00 sub %r5,%r6
40: 27 02 00 00 9a 02 00 00 mul %r2,0x29a
48: 27 03 00 00 66 fd ff ff mul %r3,-666
50: 27 04 00 00 ef be ad 7e mul %r4,0x7eadbeef
58: 2f 65 00 00 00 00 00 00 mul %r5,%r6
60: 37 02 00 00 9a 02 00 00 div %r2,0x29a
68: 37 03 00 00 66 fd ff ff div %r3,-666
70: 37 04 00 00 ef be ad 7e div %r4,0x7eadbeef
78: 3f 65 00 00 00 00 00 00 div %r5,%r6
80: 47 02 00 00 9a 02 00 00 or %r2,0x29a
88: 47 03 00 00 66 fd ff ff or %r3,-666
90: 47 04 00 00 ef be ad 7e or %r4,0x7eadbeef
98: 4f 65 00 00 00 00 00 00 or %r5,%r6
a0: 57 02 00 00 9a 02 00 00 and %r2,0x29a
a8: 57 03 00 00 66 fd ff ff and %r3,-666
b0: 57 04 00 00 ef be ad 7e and %r4,0x7eadbeef
b8: 5f 65 00 00 00 00 00 00 and %r5,%r6
c0: 67 02 00 00 9a 02 00 00 lsh %r2,0x29a
c8: 67 03 00 00 66 fd ff ff lsh %r3,-666
d0: 67 04 00 00 ef be ad 7e lsh %r4,0x7eadbeef
d8: 6f 65 00 00 00 00 00 00 lsh %r5,%r6
e0: 77 02 00 00 9a 02 00 00 rsh %r2,0x29a
e8: 77 03 00 00 66 fd ff ff rsh %r3,-666
f0: 77 04 00 00 ef be ad 7e rsh %r4,0x7eadbeef
f8: 7f 65 00 00 00 00 00 00 rsh %r5,%r6
100: 97 02 00 00 9a 02 00 00 mod %r2,0x29a
108: 97 03 00 00 66 fd ff ff mod %r3,-666
110: 97 04 00 00 ef be ad 7e mod %r4,0x7eadbeef
118: 9f 65 00 00 00 00 00 00 mod %r5,%r6
120: a7 02 00 00 9a 02 00 00 xor %r2,0x29a
128: a7 03 00 00 66 fd ff ff xor %r3,-666
130: a7 04 00 00 ef be ad 7e xor %r4,0x7eadbeef
138: af 65 00 00 00 00 00 00 xor %r5,%r6
140: b7 02 00 00 9a 02 00 00 mov %r2,0x29a
148: b7 03 00 00 66 fd ff ff mov %r3,-666
150: b7 04 00 00 ef be ad 7e mov %r4,0x7eadbeef
158: bf 65 00 00 00 00 00 00 mov %r5,%r6
160: c7 02 00 00 9a 02 00 00 arsh %r2,0x29a
168: c7 03 00 00 66 fd ff ff arsh %r3,-666
170: c7 04 00 00 ef be ad 7e arsh %r4,0x7eadbeef
178: cf 65 00 00 00 00 00 00 arsh %r5,%r6
180: 87 02 00 00 00 00 00 00 neg %r2

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#as: --EB
#objdump: -dr
#source: alu32-pseudoc.s
#dump: alu32-be.dump
#name: eBPF ALU instructions, big-endian, pseudo-c syntax

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@ -1,66 +1,5 @@
#as: --EB
#source: alu32.s
#source: alu32-pseudoc.s
#objdump: -dr
#name: eBPF ALU instructions, big-endian
.*: +file format .*bpf.*
Disassembly of section .text:
0+ <.text>:
0: 04 20 00 00 00 00 02 9a add32 %r2,0x29a
8: 04 30 00 00 ff ff fd 66 add32 %r3,-666
10: 04 40 00 00 7e ad be ef add32 %r4,0x7eadbeef
18: 0c 56 00 00 00 00 00 00 add32 %r5,%r6
20: 14 20 00 00 00 00 02 9a sub32 %r2,0x29a
28: 14 30 00 00 ff ff fd 66 sub32 %r3,-666
30: 14 40 00 00 7e ad be ef sub32 %r4,0x7eadbeef
38: 1c 56 00 00 00 00 00 00 sub32 %r5,%r6
40: 24 20 00 00 00 00 02 9a mul32 %r2,0x29a
48: 24 30 00 00 ff ff fd 66 mul32 %r3,-666
50: 24 40 00 00 7e ad be ef mul32 %r4,0x7eadbeef
58: 2c 56 00 00 00 00 00 00 mul32 %r5,%r6
60: 34 20 00 00 00 00 02 9a div32 %r2,0x29a
68: 34 30 00 00 ff ff fd 66 div32 %r3,-666
70: 34 40 00 00 7e ad be ef div32 %r4,0x7eadbeef
78: 3c 56 00 00 00 00 00 00 div32 %r5,%r6
80: 44 20 00 00 00 00 02 9a or32 %r2,0x29a
88: 44 30 00 00 ff ff fd 66 or32 %r3,-666
90: 44 40 00 00 7e ad be ef or32 %r4,0x7eadbeef
98: 4c 56 00 00 00 00 00 00 or32 %r5,%r6
a0: 54 20 00 00 00 00 02 9a and32 %r2,0x29a
a8: 54 30 00 00 ff ff fd 66 and32 %r3,-666
b0: 54 40 00 00 7e ad be ef and32 %r4,0x7eadbeef
b8: 5c 56 00 00 00 00 00 00 and32 %r5,%r6
c0: 64 20 00 00 00 00 02 9a lsh32 %r2,0x29a
c8: 64 30 00 00 ff ff fd 66 lsh32 %r3,-666
d0: 64 40 00 00 7e ad be ef lsh32 %r4,0x7eadbeef
d8: 6c 56 00 00 00 00 00 00 lsh32 %r5,%r6
e0: 74 20 00 00 00 00 02 9a rsh32 %r2,0x29a
e8: 74 30 00 00 ff ff fd 66 rsh32 %r3,-666
f0: 74 40 00 00 7e ad be ef rsh32 %r4,0x7eadbeef
f8: 7c 56 00 00 00 00 00 00 rsh32 %r5,%r6
100: 94 20 00 00 00 00 02 9a mod32 %r2,0x29a
108: 94 30 00 00 ff ff fd 66 mod32 %r3,-666
110: 94 40 00 00 7e ad be ef mod32 %r4,0x7eadbeef
118: 9c 56 00 00 00 00 00 00 mod32 %r5,%r6
120: a4 20 00 00 00 00 02 9a xor32 %r2,0x29a
128: a4 30 00 00 ff ff fd 66 xor32 %r3,-666
130: a4 40 00 00 7e ad be ef xor32 %r4,0x7eadbeef
138: ac 56 00 00 00 00 00 00 xor32 %r5,%r6
140: b4 20 00 00 00 00 02 9a mov32 %r2,0x29a
148: b4 30 00 00 ff ff fd 66 mov32 %r3,-666
150: b4 40 00 00 7e ad be ef mov32 %r4,0x7eadbeef
158: bc 56 00 00 00 00 00 00 mov32 %r5,%r6
160: c4 20 00 00 00 00 02 9a arsh32 %r2,0x29a
168: c4 30 00 00 ff ff fd 66 arsh32 %r3,-666
170: c4 40 00 00 7e ad be ef arsh32 %r4,0x7eadbeef
178: cc 56 00 00 00 00 00 00 arsh32 %r5,%r6
180: 84 20 00 00 00 00 00 00 neg32 %r2
188: d4 90 00 00 00 00 00 10 endle %r9,16
190: d4 80 00 00 00 00 00 20 endle %r8,32
198: d4 70 00 00 00 00 00 40 endle %r7,64
1a0: dc 60 00 00 00 00 00 10 endbe %r6,16
1a8: dc 50 00 00 00 00 00 20 endbe %r5,32
1b0: dc 40 00 00 00 00 00 40 endbe %r4,64
#source: alu32-pseudoc.s
#dump: alu32-be.dump
#name: eBPF ALU instructions, big-endian, normal syntax

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.*: +file format .*bpf.*
Disassembly of section .text:
0+ <.text>:
0: 04 20 00 00 00 00 02 9a add32 %r2,0x29a
8: 04 30 00 00 ff ff fd 66 add32 %r3,-666
10: 04 40 00 00 7e ad be ef add32 %r4,0x7eadbeef
18: 0c 56 00 00 00 00 00 00 add32 %r5,%r6
20: 14 20 00 00 00 00 02 9a sub32 %r2,0x29a
28: 14 30 00 00 ff ff fd 66 sub32 %r3,-666
30: 14 40 00 00 7e ad be ef sub32 %r4,0x7eadbeef
38: 1c 56 00 00 00 00 00 00 sub32 %r5,%r6
40: 24 20 00 00 00 00 02 9a mul32 %r2,0x29a
48: 24 30 00 00 ff ff fd 66 mul32 %r3,-666
50: 24 40 00 00 7e ad be ef mul32 %r4,0x7eadbeef
58: 2c 56 00 00 00 00 00 00 mul32 %r5,%r6
60: 34 20 00 00 00 00 02 9a div32 %r2,0x29a
68: 34 30 00 00 ff ff fd 66 div32 %r3,-666
70: 34 40 00 00 7e ad be ef div32 %r4,0x7eadbeef
78: 3c 56 00 00 00 00 00 00 div32 %r5,%r6
80: 44 20 00 00 00 00 02 9a or32 %r2,0x29a
88: 44 30 00 00 ff ff fd 66 or32 %r3,-666
90: 44 40 00 00 7e ad be ef or32 %r4,0x7eadbeef
98: 4c 56 00 00 00 00 00 00 or32 %r5,%r6
a0: 54 20 00 00 00 00 02 9a and32 %r2,0x29a
a8: 54 30 00 00 ff ff fd 66 and32 %r3,-666
b0: 54 40 00 00 7e ad be ef and32 %r4,0x7eadbeef
b8: 5c 56 00 00 00 00 00 00 and32 %r5,%r6
c0: 64 20 00 00 00 00 02 9a lsh32 %r2,0x29a
c8: 64 30 00 00 ff ff fd 66 lsh32 %r3,-666
d0: 64 40 00 00 7e ad be ef lsh32 %r4,0x7eadbeef
d8: 6c 56 00 00 00 00 00 00 lsh32 %r5,%r6
e0: 74 20 00 00 00 00 02 9a rsh32 %r2,0x29a
e8: 74 30 00 00 ff ff fd 66 rsh32 %r3,-666
f0: 74 40 00 00 7e ad be ef rsh32 %r4,0x7eadbeef
f8: 7c 56 00 00 00 00 00 00 rsh32 %r5,%r6
100: 94 20 00 00 00 00 02 9a mod32 %r2,0x29a
108: 94 30 00 00 ff ff fd 66 mod32 %r3,-666
110: 94 40 00 00 7e ad be ef mod32 %r4,0x7eadbeef
118: 9c 56 00 00 00 00 00 00 mod32 %r5,%r6
120: a4 20 00 00 00 00 02 9a xor32 %r2,0x29a
128: a4 30 00 00 ff ff fd 66 xor32 %r3,-666
130: a4 40 00 00 7e ad be ef xor32 %r4,0x7eadbeef
138: ac 56 00 00 00 00 00 00 xor32 %r5,%r6
140: b4 20 00 00 00 00 02 9a mov32 %r2,0x29a
148: b4 30 00 00 ff ff fd 66 mov32 %r3,-666
150: b4 40 00 00 7e ad be ef mov32 %r4,0x7eadbeef
158: bc 56 00 00 00 00 00 00 mov32 %r5,%r6
160: c4 20 00 00 00 00 02 9a arsh32 %r2,0x29a
168: c4 30 00 00 ff ff fd 66 arsh32 %r3,-666
170: c4 40 00 00 7e ad be ef arsh32 %r4,0x7eadbeef
178: cc 56 00 00 00 00 00 00 arsh32 %r5,%r6
180: 84 20 00 00 00 00 00 00 neg32 %r2
188: d4 90 00 00 00 00 00 10 endle %r9,16
190: d4 80 00 00 00 00 00 20 endle %r8,32
198: d4 70 00 00 00 00 00 40 endle %r7,64
1a0: dc 60 00 00 00 00 00 10 endbe %r6,16
1a8: dc 50 00 00 00 00 00 20 endbe %r5,32
1b0: dc 40 00 00 00 00 00 40 endbe %r4,64

View File

@ -0,0 +1,5 @@
#as: --EL
#objdump: -dr
#source: alu32-pseudoc.s
#dump: alu32.dump
#name: eBPF ALU instructions, pseudo-c syntax

View File

@ -1,66 +1,5 @@
#as: --EL
#objdump: -dr
#source: alu32.s
#source: alu32-pseudoc.s
#name: eBPF ALU instructions
.*: +file format .*bpf.*
Disassembly of section .text:
0+ <.text>:
0: 04 02 00 00 9a 02 00 00 add32 %r2,0x29a
8: 04 03 00 00 66 fd ff ff add32 %r3,-666
10: 04 04 00 00 ef be ad 7e add32 %r4,0x7eadbeef
18: 0c 65 00 00 00 00 00 00 add32 %r5,%r6
20: 14 02 00 00 9a 02 00 00 sub32 %r2,0x29a
28: 14 03 00 00 66 fd ff ff sub32 %r3,-666
30: 14 04 00 00 ef be ad 7e sub32 %r4,0x7eadbeef
38: 1c 65 00 00 00 00 00 00 sub32 %r5,%r6
40: 24 02 00 00 9a 02 00 00 mul32 %r2,0x29a
48: 24 03 00 00 66 fd ff ff mul32 %r3,-666
50: 24 04 00 00 ef be ad 7e mul32 %r4,0x7eadbeef
58: 2c 65 00 00 00 00 00 00 mul32 %r5,%r6
60: 34 02 00 00 9a 02 00 00 div32 %r2,0x29a
68: 34 03 00 00 66 fd ff ff div32 %r3,-666
70: 34 04 00 00 ef be ad 7e div32 %r4,0x7eadbeef
78: 3c 65 00 00 00 00 00 00 div32 %r5,%r6
80: 44 02 00 00 9a 02 00 00 or32 %r2,0x29a
88: 44 03 00 00 66 fd ff ff or32 %r3,-666
90: 44 04 00 00 ef be ad 7e or32 %r4,0x7eadbeef
98: 4c 65 00 00 00 00 00 00 or32 %r5,%r6
a0: 54 02 00 00 9a 02 00 00 and32 %r2,0x29a
a8: 54 03 00 00 66 fd ff ff and32 %r3,-666
b0: 54 04 00 00 ef be ad 7e and32 %r4,0x7eadbeef
b8: 5c 65 00 00 00 00 00 00 and32 %r5,%r6
c0: 64 02 00 00 9a 02 00 00 lsh32 %r2,0x29a
c8: 64 03 00 00 66 fd ff ff lsh32 %r3,-666
d0: 64 04 00 00 ef be ad 7e lsh32 %r4,0x7eadbeef
d8: 6c 65 00 00 00 00 00 00 lsh32 %r5,%r6
e0: 74 02 00 00 9a 02 00 00 rsh32 %r2,0x29a
e8: 74 03 00 00 66 fd ff ff rsh32 %r3,-666
f0: 74 04 00 00 ef be ad 7e rsh32 %r4,0x7eadbeef
f8: 7c 65 00 00 00 00 00 00 rsh32 %r5,%r6
100: 94 02 00 00 9a 02 00 00 mod32 %r2,0x29a
108: 94 03 00 00 66 fd ff ff mod32 %r3,-666
110: 94 04 00 00 ef be ad 7e mod32 %r4,0x7eadbeef
118: 9c 65 00 00 00 00 00 00 mod32 %r5,%r6
120: a4 02 00 00 9a 02 00 00 xor32 %r2,0x29a
128: a4 03 00 00 66 fd ff ff xor32 %r3,-666
130: a4 04 00 00 ef be ad 7e xor32 %r4,0x7eadbeef
138: ac 65 00 00 00 00 00 00 xor32 %r5,%r6
140: b4 02 00 00 9a 02 00 00 mov32 %r2,0x29a
148: b4 03 00 00 66 fd ff ff mov32 %r3,-666
150: b4 04 00 00 ef be ad 7e mov32 %r4,0x7eadbeef
158: bc 65 00 00 00 00 00 00 mov32 %r5,%r6
160: c4 02 00 00 9a 02 00 00 arsh32 %r2,0x29a
168: c4 03 00 00 66 fd ff ff arsh32 %r3,-666
170: c4 04 00 00 ef be ad 7e arsh32 %r4,0x7eadbeef
178: cc 65 00 00 00 00 00 00 arsh32 %r5,%r6
180: 84 02 00 00 00 00 00 00 neg32 %r2
188: d4 09 00 00 10 00 00 00 endle %r9,16
190: d4 08 00 00 20 00 00 00 endle %r8,32
198: d4 07 00 00 40 00 00 00 endle %r7,64
1a0: dc 06 00 00 10 00 00 00 endbe %r6,16
1a8: dc 05 00 00 20 00 00 00 endbe %r5,32
1b0: dc 04 00 00 40 00 00 00 endbe %r4,64
#dump: alu32.dump
#name: eBPF ALU instructions, normal syntax

View File

@ -0,0 +1,60 @@
.*: +file format .*bpf.*
Disassembly of section .text:
0+ <.text>:
0: 04 02 00 00 9a 02 00 00 add32 %r2,0x29a
8: 04 03 00 00 66 fd ff ff add32 %r3,-666
10: 04 04 00 00 ef be ad 7e add32 %r4,0x7eadbeef
18: 0c 65 00 00 00 00 00 00 add32 %r5,%r6
20: 14 02 00 00 9a 02 00 00 sub32 %r2,0x29a
28: 14 03 00 00 66 fd ff ff sub32 %r3,-666
30: 14 04 00 00 ef be ad 7e sub32 %r4,0x7eadbeef
38: 1c 65 00 00 00 00 00 00 sub32 %r5,%r6
40: 24 02 00 00 9a 02 00 00 mul32 %r2,0x29a
48: 24 03 00 00 66 fd ff ff mul32 %r3,-666
50: 24 04 00 00 ef be ad 7e mul32 %r4,0x7eadbeef
58: 2c 65 00 00 00 00 00 00 mul32 %r5,%r6
60: 34 02 00 00 9a 02 00 00 div32 %r2,0x29a
68: 34 03 00 00 66 fd ff ff div32 %r3,-666
70: 34 04 00 00 ef be ad 7e div32 %r4,0x7eadbeef
78: 3c 65 00 00 00 00 00 00 div32 %r5,%r6
80: 44 02 00 00 9a 02 00 00 or32 %r2,0x29a
88: 44 03 00 00 66 fd ff ff or32 %r3,-666
90: 44 04 00 00 ef be ad 7e or32 %r4,0x7eadbeef
98: 4c 65 00 00 00 00 00 00 or32 %r5,%r6
a0: 54 02 00 00 9a 02 00 00 and32 %r2,0x29a
a8: 54 03 00 00 66 fd ff ff and32 %r3,-666
b0: 54 04 00 00 ef be ad 7e and32 %r4,0x7eadbeef
b8: 5c 65 00 00 00 00 00 00 and32 %r5,%r6
c0: 64 02 00 00 9a 02 00 00 lsh32 %r2,0x29a
c8: 64 03 00 00 66 fd ff ff lsh32 %r3,-666
d0: 64 04 00 00 ef be ad 7e lsh32 %r4,0x7eadbeef
d8: 6c 65 00 00 00 00 00 00 lsh32 %r5,%r6
e0: 74 02 00 00 9a 02 00 00 rsh32 %r2,0x29a
e8: 74 03 00 00 66 fd ff ff rsh32 %r3,-666
f0: 74 04 00 00 ef be ad 7e rsh32 %r4,0x7eadbeef
f8: 7c 65 00 00 00 00 00 00 rsh32 %r5,%r6
100: 94 02 00 00 9a 02 00 00 mod32 %r2,0x29a
108: 94 03 00 00 66 fd ff ff mod32 %r3,-666
110: 94 04 00 00 ef be ad 7e mod32 %r4,0x7eadbeef
118: 9c 65 00 00 00 00 00 00 mod32 %r5,%r6
120: a4 02 00 00 9a 02 00 00 xor32 %r2,0x29a
128: a4 03 00 00 66 fd ff ff xor32 %r3,-666
130: a4 04 00 00 ef be ad 7e xor32 %r4,0x7eadbeef
138: ac 65 00 00 00 00 00 00 xor32 %r5,%r6
140: b4 02 00 00 9a 02 00 00 mov32 %r2,0x29a
148: b4 03 00 00 66 fd ff ff mov32 %r3,-666
150: b4 04 00 00 ef be ad 7e mov32 %r4,0x7eadbeef
158: bc 65 00 00 00 00 00 00 mov32 %r5,%r6
160: c4 02 00 00 9a 02 00 00 arsh32 %r2,0x29a
168: c4 03 00 00 66 fd ff ff arsh32 %r3,-666
170: c4 04 00 00 ef be ad 7e arsh32 %r4,0x7eadbeef
178: cc 65 00 00 00 00 00 00 arsh32 %r5,%r6
180: 84 02 00 00 00 00 00 00 neg32 %r2
188: d4 09 00 00 10 00 00 00 endle %r9,16
190: d4 08 00 00 20 00 00 00 endle %r8,32
198: d4 07 00 00 40 00 00 00 endle %r7,64
1a0: dc 06 00 00 10 00 00 00 endbe %r6,16
1a8: dc 05 00 00 20 00 00 00 endbe %r5,32
1b0: dc 04 00 00 40 00 00 00 endbe %r4,64

View File

@ -0,0 +1,5 @@
#as: --EL
#objdump: -dr
#source: atomic-pseudoc.s
#dump: atomic.dump
#name: eBPF atomic instructions, normal syntax

View File

@ -1,13 +1,5 @@
#as: --EL
#objdump: -dr
#source: atomic.s
#source: atomic-pseudoc.s
#name: eBPF atomic instructions
.*: +file format .*bpf.*
Disassembly of section .text:
0+ <.text>:
0: db 21 ef 1e 00 00 00 00 xadddw \[%r1\+0x1eef\],%r2
8: c3 21 ef 1e 00 00 00 00 xaddw \[%r1\+0x1eef\],%r2
#dump: atomic.dump
#name: eBPF atomic instructions, normal syntax

View File

@ -0,0 +1,7 @@
.*: +file format .*bpf.*
Disassembly of section .text:
0+ <.text>:
0: db 21 ef 1e 00 00 00 00 xadddw \[%r1\+0x1eef\],%r2
8: c3 21 ef 1e 00 00 00 00 xaddw \[%r1\+0x1eef\],%r2

View File

@ -19,20 +19,30 @@
if {[istarget bpf*-*-*]} {
run_dump_test lddw
run_dump_test lddw-pseudoc
run_dump_test alu
run_dump_test alu-pseudoc
run_dump_test alu32
run_dump_test alu32-pseudoc
run_dump_test mem
run_dump_test mem-pseudoc
run_dump_test jump
run_dump_test jump-pseudoc
run_dump_test jump32
run_dump_test jump32-pseudoc
run_dump_test call
run_dump_test exit
run_dump_test atomic
run_dump_test atomic-pseudoc
run_dump_test data
run_dump_test pseudoc-normal
run_dump_test lddw-be
run_dump_test lddw-be-pseudoc
run_dump_test alu-be
run_dump_test alu-be-pseudoc
run_dump_test alu32-be
run_dump_test alu32-be-pseudoc
run_dump_test mem-be
run_dump_test jump-be
run_dump_test call-be
@ -42,6 +52,7 @@ if {[istarget bpf*-*-*]} {
run_dump_test pseudoc-normal-be
run_dump_test indcall-1
run_dump_test indcall-1-pseudoc
run_list_test indcall-bad-1
run_dump_test alu-xbpf

View File

@ -0,0 +1,5 @@
#as: -mxbpf --EL
#objdump: -mxbpf -dr
#source: indcall-1-pseudoc.s
#dump: indcall-1.dump
#name: BPF indirect call 1, pseudoc syntax

View File

@ -5,7 +5,7 @@ main:
r0 = 1
r1 = 1
r2 = 2
r6 = 56 ll
r6 = bar ll
callx r6
exit
bar:

View File

@ -1,24 +1,5 @@
#as: -mxbpf --EL
#objdump: -mxbpf -dr
#source: indcall-1.s
#source: indcall-1-pseudoc.s
#name: BPF indirect call 1
.*: +file format .*bpf.*
Disassembly of section \.text:
0000000000000000 <main>:
0: b7 00 00 00 01 00 00 00 mov %r0,1
8: b7 01 00 00 01 00 00 00 mov %r1,1
10: b7 02 00 00 02 00 00 00 mov %r2,2
18: 18 06 00 00 38 00 00 00 lddw %r6,0x38
20: 00 00 00 00 00 00 00 00[ ]*
18: R_BPF_64_64 .text
28: 8d 06 00 00 00 00 00 00 call %r6
30: 95 00 00 00 00 00 00 00 exit
0000000000000038 <bar>:
38: b7 00 00 00 00 00 00 00 mov %r0,0
40: 95 00 00 00 00 00 00 00 exit
#pass
#dump: indcall-1.dump
#name: BPF indirect call 1, normal syntax

View File

@ -0,0 +1,18 @@
.*: +file format .*bpf.*
Disassembly of section \.text:
0000000000000000 <main>:
0: b7 00 00 00 01 00 00 00 mov %r0,1
8: b7 01 00 00 01 00 00 00 mov %r1,1
10: b7 02 00 00 02 00 00 00 mov %r2,2
18: 18 06 00 00 38 00 00 00 lddw %r6,0x38
20: 00 00 00 00 00 00 00 00[ ]*
18: R_BPF_64_64 .text
28: 8d 06 00 00 00 00 00 00 call %r6
30: 95 00 00 00 00 00 00 00 exit
0000000000000038 <bar>:
38: b7 00 00 00 00 00 00 00 mov %r0,0
40: 95 00 00 00 00 00 00 00 exit
#pass

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@ -0,0 +1,5 @@
#as: --EL
#objdump: -dr
#source: jump-pseudoc.s
#dump: jump.dump
#name: eBPF JUMP instructions, pseudoc syntax

View File

@ -1,33 +1,5 @@
#as: --EL
#objdump: -dr
#source: jump.s
#source: jump-pseudoc.s
#name: eBPF JUMP instructions
.*: +file format .*bpf.*
Disassembly of section .text:
0+ <.text>:
0: 05 00 03 00 00 00 00 00 ja 3
8: 0f 11 00 00 00 00 00 00 add %r1,%r1
10: 15 03 01 00 03 00 00 00 jeq %r3,3,1
18: 1d 43 00 00 00 00 00 00 jeq %r3,%r4,0
20: 35 03 fd ff 03 00 00 00 jge %r3,3,-3
28: 3d 43 fc ff 00 00 00 00 jge %r3,%r4,-4
30: a5 03 01 00 03 00 00 00 jlt %r3,3,1
38: ad 43 00 00 00 00 00 00 jlt %r3,%r4,0
40: b5 03 01 00 03 00 00 00 jle %r3,3,1
48: bd 43 00 00 00 00 00 00 jle %r3,%r4,0
50: 45 03 01 00 03 00 00 00 jset %r3,3,1
58: 4d 43 00 00 00 00 00 00 jset %r3,%r4,0
60: 55 03 01 00 03 00 00 00 jne %r3,3,1
68: 5d 43 00 00 00 00 00 00 jne %r3,%r4,0
70: 65 03 01 00 03 00 00 00 jsgt %r3,3,1
78: 6d 43 00 00 00 00 00 00 jsgt %r3,%r4,0
80: 75 03 01 00 03 00 00 00 jsge %r3,3,1
88: 7d 43 00 00 00 00 00 00 jsge %r3,%r4,0
90: c5 03 01 00 03 00 00 00 jslt %r3,3,1
98: cd 43 00 00 00 00 00 00 jslt %r3,%r4,0
a0: d5 03 01 00 03 00 00 00 jsle %r3,3,1
a8: dd 43 00 00 00 00 00 00 jsle %r3,%r4,0
#dump: jump.dump
#name: eBPF JUMP instructions, normal syntax

View File

@ -0,0 +1,27 @@
.*: +file format .*bpf.*
Disassembly of section .text:
0+ <.text>:
0: 05 00 03 00 00 00 00 00 ja 3
8: 0f 11 00 00 00 00 00 00 add %r1,%r1
10: 15 03 01 00 03 00 00 00 jeq %r3,3,1
18: 1d 43 00 00 00 00 00 00 jeq %r3,%r4,0
20: 35 03 fd ff 03 00 00 00 jge %r3,3,-3
28: 3d 43 fc ff 00 00 00 00 jge %r3,%r4,-4
30: a5 03 01 00 03 00 00 00 jlt %r3,3,1
38: ad 43 00 00 00 00 00 00 jlt %r3,%r4,0
40: b5 03 01 00 03 00 00 00 jle %r3,3,1
48: bd 43 00 00 00 00 00 00 jle %r3,%r4,0
50: 45 03 01 00 03 00 00 00 jset %r3,3,1
58: 4d 43 00 00 00 00 00 00 jset %r3,%r4,0
60: 55 03 01 00 03 00 00 00 jne %r3,3,1
68: 5d 43 00 00 00 00 00 00 jne %r3,%r4,0
70: 65 03 01 00 03 00 00 00 jsgt %r3,3,1
78: 6d 43 00 00 00 00 00 00 jsgt %r3,%r4,0
80: 75 03 01 00 03 00 00 00 jsge %r3,3,1
88: 7d 43 00 00 00 00 00 00 jsge %r3,%r4,0
90: c5 03 01 00 03 00 00 00 jslt %r3,3,1
98: cd 43 00 00 00 00 00 00 jslt %r3,%r4,0
a0: d5 03 01 00 03 00 00 00 jsle %r3,3,1
a8: dd 43 00 00 00 00 00 00 jsle %r3,%r4,0

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@ -0,0 +1,5 @@
#as: --EL
#objdump: -dr
#source: jump32-pseudoc.s
#dump: jump32.dump
#name: eBPF JUMP32 instructions, pseudoc syntax

View File

@ -1,33 +1,5 @@
#as: --EL
#objdump: -dr
#source: jump32.s
#source: jump32-pseudoc.s
#name: eBPF JUMP32 instructions
.*: +file format .*bpf.*
Disassembly of section .text:
0+ <.text>:
0: 05 00 03 00 00 00 00 00 ja 3
8: 0f 11 00 00 00 00 00 00 add %r1,%r1
10: 16 03 01 00 03 00 00 00 jeq32 %r3,3,1
18: 1e 43 00 00 00 00 00 00 jeq32 %r3,%r4,0
20: 36 03 fd ff 03 00 00 00 jge32 %r3,3,-3
28: 3e 43 fc ff 00 00 00 00 jge32 %r3,%r4,-4
30: a6 03 01 00 03 00 00 00 jlt32 %r3,3,1
38: ae 43 00 00 00 00 00 00 jlt32 %r3,%r4,0
40: b6 03 01 00 03 00 00 00 jle32 %r3,3,1
48: be 43 00 00 00 00 00 00 jle32 %r3,%r4,0
50: 46 03 01 00 03 00 00 00 jset32 %r3,3,1
58: 4e 43 00 00 00 00 00 00 jset32 %r3,%r4,0
60: 56 03 01 00 03 00 00 00 jne32 %r3,3,1
68: 5e 43 00 00 00 00 00 00 jne32 %r3,%r4,0
70: 66 03 01 00 03 00 00 00 jsgt32 %r3,3,1
78: 6e 43 00 00 00 00 00 00 jsgt32 %r3,%r4,0
80: 76 03 01 00 03 00 00 00 jsge32 %r3,3,1
88: 7e 43 00 00 00 00 00 00 jsge32 %r3,%r4,0
90: c6 03 01 00 03 00 00 00 jslt32 %r3,3,1
98: ce 43 00 00 00 00 00 00 jslt32 %r3,%r4,0
a0: d6 03 01 00 03 00 00 00 jsle32 %r3,3,1
a8: de 43 00 00 00 00 00 00 jsle32 %r3,%r4,0
#dump: jump32.dump
#name: eBPF JUMP32 instructions, normal syntax

View File

@ -0,0 +1,27 @@
.*: +file format .*bpf.*
Disassembly of section .text:
0+ <.text>:
0: 05 00 03 00 00 00 00 00 ja 3
8: 0f 11 00 00 00 00 00 00 add %r1,%r1
10: 16 03 01 00 03 00 00 00 jeq32 %r3,3,1
18: 1e 43 00 00 00 00 00 00 jeq32 %r3,%r4,0
20: 36 03 fd ff 03 00 00 00 jge32 %r3,3,-3
28: 3e 43 fc ff 00 00 00 00 jge32 %r3,%r4,-4
30: a6 03 01 00 03 00 00 00 jlt32 %r3,3,1
38: ae 43 00 00 00 00 00 00 jlt32 %r3,%r4,0
40: b6 03 01 00 03 00 00 00 jle32 %r3,3,1
48: be 43 00 00 00 00 00 00 jle32 %r3,%r4,0
50: 46 03 01 00 03 00 00 00 jset32 %r3,3,1
58: 4e 43 00 00 00 00 00 00 jset32 %r3,%r4,0
60: 56 03 01 00 03 00 00 00 jne32 %r3,3,1
68: 5e 43 00 00 00 00 00 00 jne32 %r3,%r4,0
70: 66 03 01 00 03 00 00 00 jsgt32 %r3,3,1
78: 6e 43 00 00 00 00 00 00 jsgt32 %r3,%r4,0
80: 76 03 01 00 03 00 00 00 jsge32 %r3,3,1
88: 7e 43 00 00 00 00 00 00 jsge32 %r3,%r4,0
90: c6 03 01 00 03 00 00 00 jslt32 %r3,3,1
98: ce 43 00 00 00 00 00 00 jslt32 %r3,%r4,0
a0: d6 03 01 00 03 00 00 00 jsle32 %r3,3,1
a8: de 43 00 00 00 00 00 00 jsle32 %r3,%r4,0

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@ -0,0 +1,5 @@
#as: --EB
#source: lddw-pseudoc.s
#objdump: -dr
#dump: lddw-be.dump
#name: eBPF LDDW, big-endian, pseudoc syntax

View File

@ -1,19 +1,5 @@
#as: --EB
#source: lddw.s
#source: lddw-pseudoc.s
#objdump: -dr
#name: eBPF LDDW, big-endian
.*: +file format .*bpf.*
Disassembly of section .text:
0+ <.text>:
0: 18 30 00 00 00 00 00 01 lddw %r3,1
8: 00 00 00 00 00 00 00 00
10: 18 40 00 00 de ad be ef lddw %r4,0xdeadbeef
18: 00 00 00 00 00 00 00 00
20: 18 50 00 00 55 66 77 88 lddw %r5,0x1122334455667788
28: 00 00 00 00 11 22 33 44
30: 18 60 00 00 ff ff ff fe lddw %r6,-2
38: 00 00 00 00 ff ff ff ff
#dump: lddw-be.dump
#name: eBPF LDDW, big-endian, normal syntax

View File

@ -0,0 +1,13 @@
.*: +file format .*bpf.*
Disassembly of section .text:
0+ <.text>:
0: 18 30 00 00 00 00 00 01 lddw %r3,1
8: 00 00 00 00 00 00 00 00
10: 18 40 00 00 de ad be ef lddw %r4,0xdeadbeef
18: 00 00 00 00 00 00 00 00
20: 18 50 00 00 55 66 77 88 lddw %r5,0x1122334455667788
28: 00 00 00 00 11 22 33 44
30: 18 60 00 00 ff ff ff fe lddw %r6,-2
38: 00 00 00 00 ff ff ff ff

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@ -0,0 +1,5 @@
#as: --EL
#objdump: -dr
#source: lddw-pseudoc.s
#dump: lddw.dump
#name: eBPF LDDW, pseudoc syntax

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@ -1,19 +1,5 @@
#as: --EL
#objdump: -dr
#source: lddw.s
#source: lddw-pseudoc.s
#name: eBPF LDDW
.*: +file format .*bpf.*
Disassembly of section .text:
0+ <.text>:
0: 18 03 00 00 01 00 00 00 lddw %r3,1
8: 00 00 00 00 00 00 00 00
10: 18 04 00 00 ef be ad de lddw %r4,0xdeadbeef
18: 00 00 00 00 00 00 00 00
20: 18 05 00 00 88 77 66 55 lddw %r5,0x1122334455667788
28: 00 00 00 00 44 33 22 11
30: 18 06 00 00 fe ff ff ff lddw %r6,-2
38: 00 00 00 00 ff ff ff ff
#dump: lddw.dump
#name: eBPF LDDW, normal syntax

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.*: +file format .*bpf.*
Disassembly of section .text:
0+ <.text>:
0: 18 03 00 00 01 00 00 00 lddw %r3,1
8: 00 00 00 00 00 00 00 00
10: 18 04 00 00 ef be ad de lddw %r4,0xdeadbeef
18: 00 00 00 00 00 00 00 00
20: 18 05 00 00 88 77 66 55 lddw %r5,0x1122334455667788
28: 00 00 00 00 44 33 22 11
30: 18 06 00 00 fe ff ff ff lddw %r6,-2
38: 00 00 00 00 ff ff ff ff

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#as: --EL
#objdump: -dr
#source: mem-pseudoc.s
#dump: mem.dump
#name: eBPF MEM instructions, modulus lddw, pseudo-c syntax

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#as: --EL
#objdump: -dr
#source: mem.s
#source: mem-pseudoc.s
#name: eBPF MEM instructions, modulus lddw
.*: +file format .*bpf.*
Disassembly of section .text:
0+ <.text>:
0: 20 00 00 00 ef be 00 00 ldabsw 0xbeef
8: 28 00 00 00 ef be 00 00 ldabsh 0xbeef
10: 30 00 00 00 ef be 00 00 ldabsb 0xbeef
18: 38 00 00 00 ef be 00 00 ldabsdw 0xbeef
20: 40 30 00 00 ef be 00 00 ldindw %r3,0xbeef
28: 48 50 00 00 ef be 00 00 ldindh %r5,0xbeef
30: 50 70 00 00 ef be 00 00 ldindb %r7,0xbeef
38: 58 90 00 00 ef be 00 00 ldinddw %r9,0xbeef
40: 61 12 ef 7e 00 00 00 00 ldxw %r2,\[%r1\+0x7eef\]
48: 69 12 ef 7e 00 00 00 00 ldxh %r2,\[%r1\+0x7eef\]
50: 71 12 ef 7e 00 00 00 00 ldxb %r2,\[%r1\+0x7eef\]
58: 79 12 fe ff 00 00 00 00 ldxdw %r2,\[%r1\+-2\]
60: 63 21 ef 7e 00 00 00 00 stxw \[%r1\+0x7eef\],%r2
68: 6b 21 ef 7e 00 00 00 00 stxh \[%r1\+0x7eef\],%r2
70: 73 21 ef 7e 00 00 00 00 stxb \[%r1\+0x7eef\],%r2
78: 7b 21 fe ff 00 00 00 00 stxdw \[%r1\+-2\],%r2
80: 72 01 ef 7e 44 33 22 11 stb \[%r1\+0x7eef\],0x11223344
88: 6a 01 ef 7e 44 33 22 11 sth \[%r1\+0x7eef\],0x11223344
90: 62 01 ef 7e 44 33 22 11 stw \[%r1\+0x7eef\],0x11223344
98: 7a 01 fe ff 44 33 22 11 stdw \[%r1\+-2\],0x11223344
#dump: mem.dump
#name: eBPF MEM instructions, modulus lddw, normal syntax

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.*: +file format .*bpf.*
Disassembly of section .text:
0+ <.text>:
0: 20 00 00 00 ef be 00 00 ldabsw 0xbeef
8: 28 00 00 00 ef be 00 00 ldabsh 0xbeef
10: 30 00 00 00 ef be 00 00 ldabsb 0xbeef
18: 38 00 00 00 ef be 00 00 ldabsdw 0xbeef
20: 40 30 00 00 ef be 00 00 ldindw %r3,0xbeef
28: 48 50 00 00 ef be 00 00 ldindh %r5,0xbeef
30: 50 70 00 00 ef be 00 00 ldindb %r7,0xbeef
38: 58 90 00 00 ef be 00 00 ldinddw %r9,0xbeef
40: 61 12 ef 7e 00 00 00 00 ldxw %r2,\[%r1\+0x7eef\]
48: 69 12 ef 7e 00 00 00 00 ldxh %r2,\[%r1\+0x7eef\]
50: 71 12 ef 7e 00 00 00 00 ldxb %r2,\[%r1\+0x7eef\]
58: 79 12 fe ff 00 00 00 00 ldxdw %r2,\[%r1\+-2\]
60: 63 21 ef 7e 00 00 00 00 stxw \[%r1\+0x7eef\],%r2
68: 6b 21 ef 7e 00 00 00 00 stxh \[%r1\+0x7eef\],%r2
70: 73 21 ef 7e 00 00 00 00 stxb \[%r1\+0x7eef\],%r2
78: 7b 21 fe ff 00 00 00 00 stxdw \[%r1\+-2\],%r2
80: 72 01 ef 7e 44 33 22 11 stb \[%r1\+0x7eef\],0x11223344
88: 6a 01 ef 7e 44 33 22 11 sth \[%r1\+0x7eef\],0x11223344
90: 62 01 ef 7e 44 33 22 11 stw \[%r1\+0x7eef\],0x11223344
98: 7a 01 fe ff 44 33 22 11 stdw \[%r1\+-2\],0x11223344