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Fix for PR18233, emit a NOP after a relaxable 16 bit insn so that optimised
insns will start on a 32 bit boundary.
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@ -1,3 +1,9 @@
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1998-12-21 Nick Clifton <nickc@cygnus.com>
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* config/tc-m32r.c (md_assemble): Emit a NOP after a relaxable 16
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bit insn when optimizing, so that parallelised instructions will
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start on a 32 bit boundary.
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1998-12-19 Gavin Romig-Koch <gavin@cygnus.com>
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* config/tc-mips.c (mips_eabi64): New.
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@ -731,6 +731,7 @@ target_make_parallel (buffer)
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/* Assemble two instructions with an explicit parallel operation (||) or
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sequential operation (->). */
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static void
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assemble_two_insns (str, str2, parallel_p)
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char * str;
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@ -761,7 +762,14 @@ assemble_two_insns (str, str2, parallel_p)
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return;
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}
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if (! enable_special
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/* Check it. */
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if (CGEN_FIELDS_BITSIZE (&first.fields) != 16)
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{
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/* xgettext:c-format */
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as_bad (_("not a 16 bit instruction '%s'"), str);
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return;
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}
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else if (! enable_special
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&& CGEN_INSN_ATTR (first.insn, CGEN_INSN_SPECIAL))
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{
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/* xgettext:c-format */
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@ -838,7 +846,13 @@ assemble_two_insns (str, str2, parallel_p)
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}
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/* Check it. */
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if (! enable_special
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if (CGEN_FIELDS_BITSIZE (&second.fields) != 16)
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{
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/* xgettext:c-format */
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as_bad (_("not a 16 bit instruction '%s'"), str);
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return;
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}
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else if (! enable_special
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&& CGEN_INSN_ATTR (second.insn, CGEN_INSN_SPECIAL))
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{
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/* xgettext:c-format */
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@ -1040,6 +1054,13 @@ md_assemble (str)
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insn.orig_insn = insn.insn;
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/* start-sanitize-m32rx */
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/* If the previous insn was relaxable, then it may be expanded
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to fill the current 16 bit slot. Emit a NOP here to occupy
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this slot, so that we can start at optimizing at a 32 bit
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boundary. */
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if (prev_insn.insn && seen_relaxable_p && optimize)
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fill_insn (0);
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if (enable_m32rx)
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{
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/* Get the indices of the operands of the instruction.
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