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x86: bogus VMOVD with 64-bit operands should only allow for registers

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These templates exist solely to satisfy gcc's needs, and gcc only
produces these with register operands.
This commit is contained in:
Jan Beulich 2018-03-08 08:26:35 +01:00 committed by Jan Beulich
parent 73053c1fc4
commit 2907c2f555
7 changed files with 17 additions and 12 deletions
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6
gas/ChangeLog
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@ -1,3 +1,9 @@
2018-03-08 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/i386/x86-64-movd.s: Drop bogus vmovd memory forms.
* testsuite/gas/i386/x86-64-movd.d,
testsuite/gas/i386/x86-64-movd-intel.d: Adjust expectations.
2018-03-08 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (operand_type_and_not): New.

2
gas/testsuite/gas/i386/x86-64-movd-intel.d
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@ -40,8 +40,6 @@ Disassembly of section .text:
+[a-f0-9]+: 62 f1 7d 08 7e 48 20 vmovd DWORD PTR \[rax\+0x80\],xmm1
+[a-f0-9]+: 62 f1 7d 08 7e 48 20 vmovd DWORD PTR \[rax\+0x80\],xmm1
+[a-f0-9]+: 62 f1 7d 08 7e c8 vmovd eax,xmm1
+[a-f0-9]+: c4 e1 f9 6e 88 80 00 00 00 vmovq xmm1,QWORD PTR \[rax\+0x80\]
+[a-f0-9]+: c4 e1 f9 6e c8 vmovq xmm1,rax
+[a-f0-9]+: c4 e1 f9 7e 88 80 00 00 00 vmovq QWORD PTR \[rax\+0x80\],xmm1
+[a-f0-9]+: c4 e1 f9 7e c8 vmovq rax,xmm1
#pass

2
gas/testsuite/gas/i386/x86-64-movd.d
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@ -39,8 +39,6 @@ Disassembly of section .text:
+[a-f0-9]+: 62 f1 7d 08 7e 48 20 vmovd %xmm1,0x80\(%rax\)
+[a-f0-9]+: 62 f1 7d 08 7e 48 20 vmovd %xmm1,0x80\(%rax\)
+[a-f0-9]+: 62 f1 7d 08 7e c8 vmovd %xmm1,%eax
+[a-f0-9]+: c4 e1 f9 6e 88 80 00 00 00 vmovq 0x80\(%rax\),%xmm1
+[a-f0-9]+: c4 e1 f9 6e c8 vmovq %rax,%xmm1
+[a-f0-9]+: c4 e1 f9 7e 88 80 00 00 00 vmovq %xmm1,0x80\(%rax\)
+[a-f0-9]+: c4 e1 f9 7e c8 vmovq %xmm1,%rax
#pass

2
gas/testsuite/gas/i386/x86-64-movd.s
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@ -35,7 +35,5 @@ _start:
{evex} vmovd dword ptr [rax + 128], xmm1
{evex} vmovd [rax + 128], xmm1
{evex} vmovd eax, xmm1
vmovd xmm1, qword ptr [rax + 128]
vmovd xmm1, rax
vmovd qword ptr [rax + 128], xmm1
vmovd rax, xmm1

5
opcodes/ChangeLog
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@ -1,3 +1,8 @@
2018-03-08 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl (vmovd): Disallow Qword memory operands.
* i386-tlb.h: Re-generate.
2018-03-08 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory

4
opcodes/i386-opc.tbl
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@ -2058,9 +2058,9 @@ vmovaps, 2, 0x29, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|CheckRegSize|No_
// support assembler for AMD64, we accept 64bit operand on vmovd so
// that we can use one template for both SSE and AVX instructions.
vmovd, 2, 0x666e, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Dword|Unspecified|BaseIndex, RegXMM }
vmovd, 2, 0x666e, None, 1, CpuAVX|Cpu64, Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { Reg64|Qword|BaseIndex, RegXMM }
vmovd, 2, 0x666e, None, 1, CpuAVX|Cpu64, Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { Reg64, RegXMM }
vmovd, 2, 0x667e, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|Reg32|BaseIndex }
vmovd, 2, 0x667e, None, 1, CpuAVX|Cpu64, Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { RegXMM, Reg64|Qword|BaseIndex }
vmovd, 2, 0x667e, None, 1, CpuAVX|Cpu64, Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { RegXMM, Reg64|RegMem }
vmovddup, 2, 0xf212, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
vmovddup, 2, 0xf212, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|RegYMM, RegYMM }
vmovdqa, 2, 0x666f, None, 1, CpuAVX, Load|Modrm|Vex|VexOpcode=0|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }

8
opcodes/i386-tbl.h
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@ -40876,8 +40876,8 @@ const insn_template i386_optab[] =
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0 },
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0,
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0,
0, 0, 0 } },
{ { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0,
@ -40913,8 +40913,8 @@ const insn_template i386_optab[] =
{ { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0,
0, 0, 0 } },
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0,
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0,
0, 0, 0 } } } },
{ "vmovd", 2, 0x666E, None, 1,
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,