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[ARC][committed] Update int_vector_base aux register.

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INT_VECTOR_BASE auxiliary register is available across all ARC
architectures.

xxxx-xx-xx  Claudiu Zissulescu <claziss@gmail.com>

	* arc-regs.h (int_vector_base): Make it available for all ARC
	CPUs.

Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>
This commit is contained in:
Claudiu Zissulescu 2020-02-25 10:27:07 +02:00
parent 70d497007d
commit 265b467340
2 changed files with 6 additions and 2 deletions
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5
opcodes/ChangeLog
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@ -1,3 +1,8 @@
2020-02-25 Claudiu Zissulescu <claziss@gmail.com>
* arc-regs.h (int_vector_base): Make it available for all ARC
CPUs.
2020-02-20 Nelson Chu <nelson.chu@sifive.com>
* riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is

3
opcodes/arc-regs.h
View File

@ -71,8 +71,7 @@ DEF (0x21, ARC_OPCODE_ARCALL, NONE, count0)
DEF (0x22, ARC_OPCODE_ARCALL, NONE, control0)
DEF (0x23, ARC_OPCODE_ARCALL, NONE, limit0)
DEF (0x24, ARC_OPCODE_ARCV1, NONE, pcport)
DEF (0x25, ARC_OPCODE_ARC700, NONE, int_vector_base)
DEF (0x25, ARC_OPCODE_ARCV2, NONE, int_vector_base)
DEF (0x25, ARC_OPCODE_ARCALL, NONE, int_vector_base)
DEF (0x26, ARC_OPCODE_ARC600, NONE, aux_vbfdw_mode)
DEF (0x27, ARC_OPCODE_ARC600, NONE, aux_vbfdw_bm0)
DEF (0x28, ARC_OPCODE_ARC600, NONE, aux_vbfdw_bm1)