mirror of
https://sourceware.org/git/binutils-gdb.git
synced 2025-02-17 13:10:12 +08:00
RISC-V: Removed the v0.93 bitmanip ZBA/ZBB/ZBC instructions.
bfd/
* elfxx-riscv.c (riscv_parse_prefixed_ext): Removed zb*.
gas/
* config/tc-riscv.c (riscv_multi_subset_supports): Removed
INSN_CLASS_ZB*.
* testsuite/gas/riscv/bitmanip-insns-32.d: Removed.
* testsuite/gas/riscv/bitmanip-insns-64.d: Removed.
* testsuite/gas/riscv/bitmanip-insns.s: Removed.
include/
* opcode/riscv-opc.h: Removed macros for zb* extensions.
* opcode/riscv.h (riscv_insn_class): Removed INSN_CLASS_ZB*.
opcodes/
* riscv-opc.c (MASK_RVB_IMM): Removed.
(riscv_opcodes): Removed zb* instructions.
(riscv_ext_version_table): Removed versions for zb*.
This commit is contained in:
Nelson Chu
parent
7d409ac001
commit
24075dcc85
@ -1,3 +1,7 @@
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2021-02-04 Nelson Chu <nelson.chu@sifive.com>
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* elfxx-riscv.c (riscv_parse_prefixed_ext): Removed zb*.
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2021-02-04 Alan Modra <amodra@gmail.com>
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PR 27311
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@ -1595,7 +1595,7 @@ riscv_parse_prefixed_ext (riscv_parse_subset_t *rps,
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static const char * const riscv_std_z_ext_strtab[] =
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{
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"zicsr", "zifencei", "zihintpause", "zba", "zbb", "zbc", NULL
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"zicsr", "zifencei", "zihintpause", NULL
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};
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static const char * const riscv_std_s_ext_strtab[] =
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@ -1,3 +1,11 @@
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2021-02-04 Nelson Chu <nelson.chu@sifive.com>
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* config/tc-riscv.c (riscv_multi_subset_supports): Removed
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INSN_CLASS_ZB*.
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* testsuite/gas/riscv/bitmanip-insns-32.d: Removed.
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* testsuite/gas/riscv/bitmanip-insns-64.d: Removed.
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* testsuite/gas/riscv/bitmanip-insns.s: Removed.
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2021-02-03 Andreas Krebbel <krebbel@linux.ibm.com>
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* doc/c-s390.texi: Document vector instruction formats.
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@ -242,16 +242,6 @@ riscv_multi_subset_supports (enum riscv_insn_class insn_class)
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case INSN_CLASS_ZIHINTPAUSE:
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return riscv_subset_supports ("zihintpause");
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case INSN_CLASS_ZBA:
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return riscv_subset_supports ("zba");
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case INSN_CLASS_ZBB:
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return riscv_subset_supports ("zbb");
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case INSN_CLASS_ZBC:
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return riscv_subset_supports ("zbc");
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case INSN_CLASS_ZBA_OR_ZBB:
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return (riscv_subset_supports ("zba")
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|| riscv_subset_supports ("zbb"));
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default:
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as_fatal ("internal: unreachable");
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return FALSE;
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@ -1,37 +0,0 @@
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#as: -march=rv32i_zba_zbb_zbc
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#source: bitmanip-insns.s
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#objdump: -dr -Mno-aliases
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.*:[ ]+file format .*
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Disassembly of section .text:
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0+000 <.text>:
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[ ]+[0-9a-f]+:[ ]+0805c533[ ]+zext.h[ ]+a0,a1
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[ ]+[0-9a-f]+:[ ]+6985d513[ ]+rev8[ ]+a0,a1
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[ ]+[0-9a-f]+:[ ]+2875d513[ ]+orc.b[ ]+a0,a1
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[ ]+[0-9a-f]+:[ ]+20c5a533[ ]+sh1add[ ]+a0,a1,a2
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[ ]+[0-9a-f]+:[ ]+20c5c533[ ]+sh2add[ ]+a0,a1,a2
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[ ]+[0-9a-f]+:[ ]+20c5e533[ ]+sh3add[ ]+a0,a1,a2
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[ ]+[0-9a-f]+:[ ]+60059513[ ]+clz[ ]+a0,a1
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[ ]+[0-9a-f]+:[ ]+60159513[ ]+ctz[ ]+a0,a1
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[ ]+[0-9a-f]+:[ ]+60259513[ ]+cpop[ ]+a0,a1
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[ ]+[0-9a-f]+:[ ]+0ac5c533[ ]+min[ ]+a0,a1,a2
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[ ]+[0-9a-f]+:[ ]+0ac5e533[ ]+max[ ]+a0,a1,a2
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[ ]+[0-9a-f]+:[ ]+0ac5d533[ ]+minu[ ]+a0,a1,a2
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[ ]+[0-9a-f]+:[ ]+0ac5f533[ ]+maxu[ ]+a0,a1,a2
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[ ]+[0-9a-f]+:[ ]+60459513[ ]+sext.b[ ]+a0,a1
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[ ]+[0-9a-f]+:[ ]+60559513[ ]+sext.h[ ]+a0,a1
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[ ]+[0-9a-f]+:[ ]+40c5f533[ ]+andn[ ]+a0,a1,a2
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[ ]+[0-9a-f]+:[ ]+40c5e533[ ]+orn[ ]+a0,a1,a2
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[ ]+[0-9a-f]+:[ ]+00c5c533[ ]+xor[ ]+a0,a1,a2
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[ ]+[0-9a-f]+:[ ]+6005d513[ ]+rori[ ]+a0,a1,0x0
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[ ]+[0-9a-f]+:[ ]+61f5d513[ ]+rori[ ]+a0,a1,0x1f
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[ ]+[0-9a-f]+:[ ]+60c5d533[ ]+ror[ ]+a0,a1,a2
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[ ]+[0-9a-f]+:[ ]+6005d513[ ]+rori[ ]+a0,a1,0x0
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[ ]+[0-9a-f]+:[ ]+61f5d513[ ]+rori[ ]+a0,a1,0x1f
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[ ]+[0-9a-f]+:[ ]+60c59533[ ]+rol[ ]+a0,a1,a2
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[ ]+[0-9a-f]+:[ ]+0ac59533[ ]+clmul[ ]+a0,a1,a2
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[ ]+[0-9a-f]+:[ ]+0ac5b533[ ]+clmulh[ ]+a0,a1,a2
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[ ]+[0-9a-f]+:[ ]+0ac5a533[ ]+clmulr[ ]+a0,a1,a2
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@ -1,55 +0,0 @@
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#as: -march=rv64i_zba_zbb_zbc -defsym __64_bit__=1
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#source: bitmanip-insns.s
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#objdump: -dr -Mno-aliases
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.*:[ ]+file format .*
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Disassembly of section .text:
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0+000 <.text>:
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[ ]+[0-9a-f]+:[ ]+0805c53b[ ]+zext.h[ ]+a0,a1
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[ ]+[0-9a-f]+:[ ]+6b85d513[ ]+rev8[ ]+a0,a1
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[ ]+[0-9a-f]+:[ ]+2875d513[ ]+orc.b[ ]+a0,a1
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[ ]+[0-9a-f]+:[ ]+0805853b[ ]+add.uw[ ]+a0,a1,zero
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[ ]+[0-9a-f]+:[ ]+20c5a533[ ]+sh1add[ ]+a0,a1,a2
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[ ]+[0-9a-f]+:[ ]+20c5c533[ ]+sh2add[ ]+a0,a1,a2
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[ ]+[0-9a-f]+:[ ]+20c5e533[ ]+sh3add[ ]+a0,a1,a2
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[ ]+[0-9a-f]+:[ ]+20c5a53b[ ]+sh1add.uw[ ]+a0,a1,a2
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[ ]+[0-9a-f]+:[ ]+20c5c53b[ ]+sh2add.uw[ ]+a0,a1,a2
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[ ]+[0-9a-f]+:[ ]+20c5e53b[ ]+sh3add.uw[ ]+a0,a1,a2
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[ ]+[0-9a-f]+:[ ]+08c5853b[ ]+add.uw[ ]+a0,a1,a2
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[ ]+[0-9a-f]+:[ ]+0805951b[ ]+slli.uw[ ]+a0,a1,0x0
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[ ]+[0-9a-f]+:[ ]+0bf5951b[ ]+slli.uw[ ]+a0,a1,0x3f
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[ ]+[0-9a-f]+:[ ]+60059513[ ]+clz[ ]+a0,a1
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[ ]+[0-9a-f]+:[ ]+60159513[ ]+ctz[ ]+a0,a1
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[ ]+[0-9a-f]+:[ ]+60259513[ ]+cpop[ ]+a0,a1
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[ ]+[0-9a-f]+:[ ]+0ac5c533[ ]+min[ ]+a0,a1,a2
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[ ]+[0-9a-f]+:[ ]+0ac5e533[ ]+max[ ]+a0,a1,a2
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[ ]+[0-9a-f]+:[ ]+0ac5d533[ ]+minu[ ]+a0,a1,a2
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[ ]+[0-9a-f]+:[ ]+0ac5f533[ ]+maxu[ ]+a0,a1,a2
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[ ]+[0-9a-f]+:[ ]+60459513[ ]+sext.b[ ]+a0,a1
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[ ]+[0-9a-f]+:[ ]+60559513[ ]+sext.h[ ]+a0,a1
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[ ]+[0-9a-f]+:[ ]+40c5f533[ ]+andn[ ]+a0,a1,a2
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[ ]+[0-9a-f]+:[ ]+40c5e533[ ]+orn[ ]+a0,a1,a2
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[ ]+[0-9a-f]+:[ ]+00c5c533[ ]+xor[ ]+a0,a1,a2
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[ ]+[0-9a-f]+:[ ]+6005d513[ ]+rori[ ]+a0,a1,0x0
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[ ]+[0-9a-f]+:[ ]+61f5d513[ ]+rori[ ]+a0,a1,0x1f
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[ ]+[0-9a-f]+:[ ]+60c5d533[ ]+ror[ ]+a0,a1,a2
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[ ]+[0-9a-f]+:[ ]+6005d513[ ]+rori[ ]+a0,a1,0x0
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[ ]+[0-9a-f]+:[ ]+61f5d513[ ]+rori[ ]+a0,a1,0x1f
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[ ]+[0-9a-f]+:[ ]+60c59533[ ]+rol[ ]+a0,a1,a2
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[ ]+[0-9a-f]+:[ ]+6005951b[ ]+clzw[ ]+a0,a1
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[ ]+[0-9a-f]+:[ ]+6015951b[ ]+ctzw[ ]+a0,a1
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[ ]+[0-9a-f]+:[ ]+6025951b[ ]+cpopw[ ]+a0,a1
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[ ]+[0-9a-f]+:[ ]+63f5d513[ ]+rori[ ]+a0,a1,0x3f
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[ ]+[0-9a-f]+:[ ]+63f5d513[ ]+rori[ ]+a0,a1,0x3f
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[ ]+[0-9a-f]+:[ ]+6005d51b[ ]+roriw[ ]+a0,a1,0x0
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[ ]+[0-9a-f]+:[ ]+61f5d51b[ ]+roriw[ ]+a0,a1,0x1f
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[ ]+[0-9a-f]+:[ ]+60c5d53b[ ]+rorw[ ]+a0,a1,a2
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[ ]+[0-9a-f]+:[ ]+6005d51b[ ]+roriw[ ]+a0,a1,0x0
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[ ]+[0-9a-f]+:[ ]+61f5d51b[ ]+roriw[ ]+a0,a1,0x1f
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[ ]+[0-9a-f]+:[ ]+60c5953b[ ]+rolw[ ]+a0,a1,a2
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[ ]+[0-9a-f]+:[ ]+0ac59533[ ]+clmul[ ]+a0,a1,a2
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[ ]+[0-9a-f]+:[ ]+0ac5b533[ ]+clmulh[ ]+a0,a1,a2
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[ ]+[0-9a-f]+:[ ]+0ac5a533[ ]+clmulr[ ]+a0,a1,a2
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@ -1,58 +0,0 @@
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# pseudo/aliaese
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zext.h a0, a1
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rev8 a0, a1
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orc.b a0, a1
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.ifdef __64_bit__
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zext.w a0, a1
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.endif
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# ZBA
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sh1add a0, a1, a2
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sh2add a0, a1, a2
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sh3add a0, a1, a2
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.ifdef __64_bit__
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sh1add.uw a0, a1, a2
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sh2add.uw a0, a1, a2
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sh3add.uw a0, a1, a2
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add.uw a0, a1, a2
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slli.uw a0, a1, 0
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slli.uw a0, a1, 63
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.endif
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# ZBB
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clz a0, a1
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ctz a0, a1
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cpop a0, a1
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min a0, a1, a2
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max a0, a1, a2
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minu a0, a1, a2
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maxu a0, a1, a2
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sext.b a0, a1
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sext.h a0, a1
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andn a0, a1, a2
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orn a0, a1, a2
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xor a0, a1, a2
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rori a0, a1, 0
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rori a0, a1, 31
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ror a0, a1, a2
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ror a0, a1, 0
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ror a0, a1, 31
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rol a0, a1, a2
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.ifdef __64_bit__
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clzw a0, a1
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ctzw a0, a1
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cpopw a0, a1
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rori a0, a1, 63
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ror a0, a1, 63
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roriw a0, a1, 0
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roriw a0, a1, 31
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rorw a0, a1, a2
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rorw a0, a1, 0
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rorw a0, a1, 31
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rolw a0, a1, a2
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.endif
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# ZBC
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clmul a0, a1, a2
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clmulh a0, a1, a2
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clmulr a0, a1, a2
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@ -1,3 +1,8 @@
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2021-02-04 Nelson Chu <nelson.chu@sifive.com>
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* opcode/riscv-opc.h: Removed macros for zb* extensions.
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* opcode/riscv.h (riscv_insn_class): Removed INSN_CLASS_ZB*.
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2021-01-15 Nelson Chu <nelson.chu@sifive.com>
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* opcode/riscv.h: Indent and GNU coding standards tidy,
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@ -191,78 +191,6 @@
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#define MASK_REMW 0xfe00707f
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#define MATCH_REMUW 0x200703b
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#define MASK_REMUW 0xfe00707f
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#define MATCH_GREVI 0x68005013
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#define MASK_GREVI 0xfc00707f
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#define MATCH_GORCI 0x28005013
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#define MASK_GORCI 0xfc00707f
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#define MATCH_PACK 0x8004033
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#define MASK_PACK 0xfe00707f
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#define MATCH_PACKW 0x800403b
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#define MASK_PACKW 0xfe00707f
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#define MATCH_SH1ADD 0x20002033
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#define MASK_SH1ADD 0xfe00707f
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#define MATCH_SH2ADD 0x20004033
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#define MASK_SH2ADD 0xfe00707f
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#define MATCH_SH3ADD 0x20006033
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#define MASK_SH3ADD 0xfe00707f
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#define MATCH_SH1ADD_UW 0x2000203b
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#define MASK_SH1ADD_UW 0xfe00707f
|
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#define MATCH_SH2ADD_UW 0x2000403b
|
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#define MASK_SH2ADD_UW 0xfe00707f
|
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#define MATCH_SH3ADD_UW 0x2000603b
|
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#define MASK_SH3ADD_UW 0xfe00707f
|
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#define MATCH_ADD_UW 0x800003b
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#define MASK_ADD_UW 0xfe00707f
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#define MATCH_SLLI_UW 0x800101b
|
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#define MASK_SLLI_UW 0xfc00707f
|
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#define MATCH_CLZ 0x60001013
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#define MASK_CLZ 0xfff0707f
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#define MATCH_CTZ 0x60101013
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#define MASK_CTZ 0xfff0707f
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#define MATCH_CPOP 0x60201013
|
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#define MASK_CPOP 0xfff0707f
|
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#define MATCH_MIN 0xa004033
|
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#define MASK_MIN 0xfe00707f
|
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#define MATCH_MAX 0xa006033
|
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#define MASK_MAX 0xfe00707f
|
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#define MATCH_MINU 0xa005033
|
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#define MASK_MINU 0xfe00707f
|
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#define MATCH_MAXU 0xa007033
|
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#define MASK_MAXU 0xfe00707f
|
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#define MATCH_SEXT_B 0x60401013
|
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#define MASK_SEXT_B 0xfff0707f
|
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#define MATCH_SEXT_H 0x60501013
|
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#define MASK_SEXT_H 0xfff0707f
|
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#define MATCH_ANDN 0x40007033
|
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#define MASK_ANDN 0xfe00707f
|
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#define MATCH_ORN 0x40006033
|
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#define MASK_ORN 0xfe00707f
|
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#define MATCH_XNOR 0x40004033
|
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#define MASK_XNOR 0xfe00707f
|
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#define MATCH_RORI 0x60005013
|
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#define MASK_RORI 0xfc00707f
|
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#define MATCH_ROR 0x60005033
|
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#define MASK_ROR 0xfe00707f
|
||||
#define MATCH_ROL 0x60001033
|
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#define MASK_ROL 0xfe00707f
|
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#define MATCH_CLZW 0x6000101b
|
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#define MASK_CLZW 0xfff0707f
|
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#define MATCH_CTZW 0x6010101b
|
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#define MASK_CTZW 0xfff0707f
|
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#define MATCH_CPOPW 0x6020101b
|
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#define MASK_CPOPW 0xfff0707f
|
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#define MATCH_RORIW 0x6000501b
|
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#define MASK_RORIW 0xfe00707f
|
||||
#define MATCH_RORW 0x6000503b
|
||||
#define MASK_RORW 0xfe00707f
|
||||
#define MATCH_ROLW 0x6000103b
|
||||
#define MASK_ROLW 0xfe00707f
|
||||
#define MATCH_CLMUL 0xa001033
|
||||
#define MASK_CLMUL 0xfe00707f
|
||||
#define MATCH_CLMULH 0xa003033
|
||||
#define MASK_CLMULH 0xfe00707f
|
||||
#define MATCH_CLMULR 0xa002033
|
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#define MASK_CLMULR 0xfe00707f
|
||||
#define MATCH_AMOADD_W 0x202f
|
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#define MASK_AMOADD_W 0xf800707f
|
||||
#define MATCH_AMOXOR_W 0x2000202f
|
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@ -1002,42 +930,6 @@ DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW)
|
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DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW)
|
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DECLARE_INSN(remw, MATCH_REMW, MASK_REMW)
|
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DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW)
|
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DECLARE_INSN(grevi, MATCH_GREVI, MASK_GREVI)
|
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DECLARE_INSN(gorci, MATCH_GORCI, MASK_GORCI)
|
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DECLARE_INSN(pack, MATCH_PACK, MASK_PACK)
|
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DECLARE_INSN(packw, MATCH_PACKW, MASK_PACKW)
|
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DECLARE_INSN(sh1add, MATCH_SH1ADD, MASK_SH1ADD)
|
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DECLARE_INSN(sh2add, MATCH_SH2ADD, MASK_SH2ADD)
|
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DECLARE_INSN(sh3add, MATCH_SH3ADD, MASK_SH3ADD)
|
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DECLARE_INSN(sh1add_uw, MATCH_SH1ADD_UW, MASK_SH1ADD_UW)
|
||||
DECLARE_INSN(sh2add_uw, MATCH_SH2ADD_UW, MASK_SH2ADD_UW)
|
||||
DECLARE_INSN(sh3add_uw, MATCH_SH3ADD_UW, MASK_SH3ADD_UW)
|
||||
DECLARE_INSN(add_uw, MATCH_ADD_UW, MASK_ADD_UW)
|
||||
DECLARE_INSN(slli_uw, MATCH_SLLI_UW, MASK_SLLI_UW)
|
||||
DECLARE_INSN(clz, MATCH_CLZ, MASK_CLZ)
|
||||
DECLARE_INSN(ctz, MATCH_CTZ, MASK_CTZ)
|
||||
DECLARE_INSN(cpop, MATCH_CPOP, MASK_CPOP)
|
||||
DECLARE_INSN(min, MATCH_MIN, MASK_MIN)
|
||||
DECLARE_INSN(max, MATCH_MAX, MASK_MAX)
|
||||
DECLARE_INSN(minu, MATCH_MINU, MASK_MINU)
|
||||
DECLARE_INSN(maxu, MATCH_MAXU, MASK_MAXU)
|
||||
DECLARE_INSN(sext_b, MATCH_SEXT_B, MASK_SEXT_B)
|
||||
DECLARE_INSN(sext_h, MATCH_SEXT_H, MASK_SEXT_H)
|
||||
DECLARE_INSN(andn, MATCH_ANDN, MASK_ANDN)
|
||||
DECLARE_INSN(orn, MATCH_ORN, MASK_ORN)
|
||||
DECLARE_INSN(xnor, MATCH_XNOR, MASK_XNOR)
|
||||
DECLARE_INSN(rori, MATCH_RORI, MASK_RORI)
|
||||
DECLARE_INSN(ror, MATCH_ROR, MASK_ROR)
|
||||
DECLARE_INSN(rol, MATCH_ROL, MASK_ROL)
|
||||
DECLARE_INSN(clzw, MATCH_CLZW, MASK_CLZW)
|
||||
DECLARE_INSN(ctzw, MATCH_CTZW, MASK_CTZW)
|
||||
DECLARE_INSN(cpopw, MATCH_CPOPW, MASK_CPOPW)
|
||||
DECLARE_INSN(roriw, MATCH_RORIW, MASK_RORIW)
|
||||
DECLARE_INSN(rorw, MATCH_RORW, MASK_RORW)
|
||||
DECLARE_INSN(rolw, MATCH_ROLW, MASK_ROLW)
|
||||
DECLARE_INSN(clmul, MATCH_CLMUL, MASK_CLMUL)
|
||||
DECLARE_INSN(clmulr, MATCH_CLMULR, MASK_CLMULR)
|
||||
DECLARE_INSN(clmulh, MATCH_CLMULH, MASK_CLMULH)
|
||||
DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W)
|
||||
DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W)
|
||||
DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W)
|
||||
|
||||
@ -311,10 +311,6 @@ enum riscv_insn_class
|
||||
INSN_CLASS_ZICSR,
|
||||
INSN_CLASS_ZIFENCEI,
|
||||
INSN_CLASS_ZIHINTPAUSE,
|
||||
INSN_CLASS_ZBA,
|
||||
INSN_CLASS_ZBB,
|
||||
INSN_CLASS_ZBC,
|
||||
INSN_CLASS_ZBA_OR_ZBB,
|
||||
};
|
||||
|
||||
/* This structure holds information for a particular instruction. */
|
||||
|
||||
@ -1,3 +1,9 @@
|
||||
2021-02-04 Nelson Chu <nelson.chu@sifive.com>
|
||||
|
||||
* riscv-opc.c (MASK_RVB_IMM): Removed.
|
||||
(riscv_opcodes): Removed zb* instructions.
|
||||
(riscv_ext_version_table): Removed versions for zb*.
|
||||
|
||||
2021-01-26 Alan Modra <amodra@gmail.com>
|
||||
|
||||
* i386-gen.c (parse_template): Ensure entire template_instance
|
||||
|
||||
@ -81,7 +81,6 @@ const char * const riscv_fpr_names_abi[NFPR] =
|
||||
#define MASK_AQ (OP_MASK_AQ << OP_SH_AQ)
|
||||
#define MASK_RL (OP_MASK_RL << OP_SH_RL)
|
||||
#define MASK_AQRL (MASK_AQ | MASK_RL)
|
||||
#define MASK_RVB_IMM (OP_MASK_SHAMT << OP_SH_SHAMT)
|
||||
|
||||
static int
|
||||
match_opcode (const struct riscv_opcode *op, insn_t insn)
|
||||
@ -241,7 +240,10 @@ const struct riscv_opcode riscv_opcodes[] =
|
||||
{"mv", 0, INSN_CLASS_I, "d,s", MATCH_ADDI, MASK_ADDI|MASK_IMM, match_opcode, INSN_ALIAS },
|
||||
{"move", 0, INSN_CLASS_C, "d,CV", MATCH_C_MV, MASK_C_MV, match_c_add, INSN_ALIAS },
|
||||
{"move", 0, INSN_CLASS_I, "d,s", MATCH_ADDI, MASK_ADDI|MASK_IMM, match_opcode, INSN_ALIAS },
|
||||
{"sext.b", 0, INSN_CLASS_I, "d,s", 0, (int) M_SEXTB, match_never, INSN_MACRO },
|
||||
{"sext.h", 0, INSN_CLASS_I, "d,s", 0, (int) M_SEXTH, match_never, INSN_MACRO },
|
||||
{"zext.b", 0, INSN_CLASS_I, "d,s", MATCH_ANDI|ENCODE_ITYPE_IMM (255), MASK_ANDI | MASK_IMM, match_opcode, INSN_ALIAS },
|
||||
{"zext.h", 0, INSN_CLASS_I, "d,s", 0, (int) M_ZEXTH, match_never, INSN_MACRO },
|
||||
{"andi", 0, INSN_CLASS_C, "Cs,Cw,Co", MATCH_C_ANDI, MASK_C_ANDI, match_opcode, INSN_ALIAS },
|
||||
{"andi", 0, INSN_CLASS_I, "d,s,j", MATCH_ANDI, MASK_ANDI, match_opcode, 0 },
|
||||
{"and", 0, INSN_CLASS_C, "Cs,Cw,Ct", MATCH_C_AND, MASK_C_AND, match_opcode, INSN_ALIAS },
|
||||
@ -373,6 +375,7 @@ const struct riscv_opcode riscv_opcodes[] =
|
||||
{"sd", 64, INSN_CLASS_C, "Ct,Cl(Cs)", MATCH_C_SD, MASK_C_SD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE },
|
||||
{"sd", 64, INSN_CLASS_I, "t,q(s)", MATCH_SD, MASK_SD, match_opcode, INSN_DREF|INSN_8_BYTE },
|
||||
{"sd", 64, INSN_CLASS_I, "t,A,s", 0, (int) M_SD, match_never, INSN_MACRO },
|
||||
{"zext.w", 64, INSN_CLASS_I, "d,s", 0, (int) M_ZEXTW, match_never, INSN_MACRO },
|
||||
{"sext.w", 64, INSN_CLASS_C, "d,CU", MATCH_C_ADDIW, MASK_C_ADDIW|MASK_RVC_IMM, match_rd_nonzero, INSN_ALIAS },
|
||||
{"sext.w", 64, INSN_CLASS_I, "d,s", MATCH_ADDIW, MASK_ADDIW|MASK_IMM, match_opcode, INSN_ALIAS },
|
||||
{"addiw", 64, INSN_CLASS_C, "d,CU,Co", MATCH_C_ADDIW, MASK_C_ADDIW, match_rd_nonzero, INSN_ALIAS },
|
||||
@ -500,54 +503,6 @@ const struct riscv_opcode riscv_opcodes[] =
|
||||
{"remw", 64, INSN_CLASS_M, "d,s,t", MATCH_REMW, MASK_REMW, match_opcode, 0 },
|
||||
{"remuw", 64, INSN_CLASS_M, "d,s,t", MATCH_REMUW, MASK_REMUW, match_opcode, 0 },
|
||||
|
||||
/* Bitmanip instruction subset - ZBA/ZBB/ZBC. */
|
||||
{"sh1add", 0, INSN_CLASS_ZBA, "d,s,t", MATCH_SH1ADD, MASK_SH1ADD, match_opcode, 0 },
|
||||
{"sh2add", 0, INSN_CLASS_ZBA, "d,s,t", MATCH_SH2ADD, MASK_SH2ADD, match_opcode, 0 },
|
||||
{"sh3add", 0, INSN_CLASS_ZBA, "d,s,t", MATCH_SH3ADD, MASK_SH3ADD, match_opcode, 0 },
|
||||
{"sh1add.uw", 64, INSN_CLASS_ZBA, "d,s,t", MATCH_SH1ADD_UW, MASK_SH1ADD_UW, match_opcode, 0 },
|
||||
{"sh2add.uw", 64, INSN_CLASS_ZBA, "d,s,t", MATCH_SH2ADD_UW, MASK_SH2ADD_UW, match_opcode, 0 },
|
||||
{"sh3add.uw", 64, INSN_CLASS_ZBA, "d,s,t", MATCH_SH3ADD_UW, MASK_SH3ADD_UW, match_opcode, 0 },
|
||||
{"zext.w", 64, INSN_CLASS_ZBA_OR_ZBB, "d,s",MATCH_ADD_UW, MASK_ADD_UW|MASK_RS2, match_opcode, INSN_ALIAS },
|
||||
{"zext.w", 64, INSN_CLASS_I, "d,s", 0, (int) M_ZEXTW, match_never, INSN_MACRO },
|
||||
{"add.uw", 64, INSN_CLASS_ZBA, "d,s,t", MATCH_ADD_UW, MASK_ADD_UW, match_opcode, 0 },
|
||||
{"slli.uw", 64, INSN_CLASS_ZBA, "d,s,>", MATCH_SLLI_UW, MASK_SLLI_UW, match_opcode, 0 },
|
||||
|
||||
{"clz", 0, INSN_CLASS_ZBB, "d,s", MATCH_CLZ, MASK_CLZ, match_opcode, 0 },
|
||||
{"ctz", 0, INSN_CLASS_ZBB, "d,s", MATCH_CTZ, MASK_CTZ, match_opcode, 0 },
|
||||
{"cpop", 0, INSN_CLASS_ZBB, "d,s", MATCH_CPOP, MASK_CPOP, match_opcode, 0 },
|
||||
{"min", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_MIN, MASK_MIN, match_opcode, 0 },
|
||||
{"max", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_MAX, MASK_MAX, match_opcode, 0 },
|
||||
{"minu", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_MINU, MASK_MINU, match_opcode, 0 },
|
||||
{"maxu", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_MAXU, MASK_MAXU, match_opcode, 0 },
|
||||
{"sext.b", 0, INSN_CLASS_ZBB, "d,s", MATCH_SEXT_B, MASK_SEXT_B, match_opcode, 0 },
|
||||
{"sext.b", 0, INSN_CLASS_I, "d,s", 0, (int) M_SEXTB, match_never, INSN_MACRO },
|
||||
{"sext.h", 0, INSN_CLASS_ZBB, "d,s", MATCH_SEXT_H, MASK_SEXT_H, match_opcode, 0 },
|
||||
{"sext.h", 0, INSN_CLASS_I, "d,s", 0, (int) M_SEXTH, match_never, INSN_MACRO },
|
||||
{"zext.h", 32, INSN_CLASS_ZBB, "d,s", MATCH_PACK, MASK_PACK|MASK_RS2, match_opcode, 0 },
|
||||
{"zext.h", 64, INSN_CLASS_ZBB, "d,s", MATCH_PACKW, MASK_PACKW|MASK_RS2, match_opcode, 0 },
|
||||
{"zext.h", 0, INSN_CLASS_I, "d,s", 0, (int) M_ZEXTH, match_never, INSN_MACRO },
|
||||
{"andn", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_ANDN, MASK_ANDN, match_opcode, 0 },
|
||||
{"orn", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_ORN, MASK_ORN, match_opcode, 0 },
|
||||
{"xnor", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_XNOR, MASK_XNOR, match_opcode, 0 },
|
||||
{"rori", 0, INSN_CLASS_ZBB, "d,s,>", MATCH_RORI, MASK_RORI, match_opcode, 0 },
|
||||
{"ror", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_ROR, MASK_ROR, match_opcode, 0 },
|
||||
{"ror", 0, INSN_CLASS_ZBB, "d,s,>", MATCH_RORI, MASK_RORI, match_opcode, INSN_ALIAS },
|
||||
{"rol", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_ROL, MASK_ROL, match_opcode, 0 },
|
||||
{"clzw", 64, INSN_CLASS_ZBB, "d,s", MATCH_CLZW, MASK_CLZW, match_opcode, 0 },
|
||||
{"ctzw", 64, INSN_CLASS_ZBB, "d,s", MATCH_CTZW, MASK_CTZW, match_opcode, 0 },
|
||||
{"cpopw", 64, INSN_CLASS_ZBB, "d,s", MATCH_CPOPW, MASK_CPOPW, match_opcode, 0 },
|
||||
{"roriw", 64, INSN_CLASS_ZBB, "d,s,<", MATCH_RORIW, MASK_RORIW, match_opcode, 0 },
|
||||
{"rorw", 64, INSN_CLASS_ZBB, "d,s,t", MATCH_RORW, MASK_RORW, match_opcode, 0 },
|
||||
{"rorw", 64, INSN_CLASS_ZBB, "d,s,<", MATCH_RORIW, MASK_RORIW, match_opcode, INSN_ALIAS },
|
||||
{"rolw", 64, INSN_CLASS_ZBB, "d,s,t", MATCH_ROLW, MASK_ROLW, match_opcode, 0 },
|
||||
{"rev8", 32, INSN_CLASS_ZBB, "d,s", MATCH_GREVI|ENCODE_ITYPE_IMM (0x18), MASK_GREVI|MASK_RVB_IMM, match_opcode, 0 },
|
||||
{"rev8", 64, INSN_CLASS_ZBB, "d,s", MATCH_GREVI|ENCODE_ITYPE_IMM (0x38), MASK_GREVI|MASK_RVB_IMM, match_opcode, 0 },
|
||||
{"orc.b", 0, INSN_CLASS_ZBB, "d,s", MATCH_GORCI|ENCODE_ITYPE_IMM (0x7), MASK_GORCI|MASK_RVB_IMM, match_opcode, 0 },
|
||||
|
||||
{"clmul", 0, INSN_CLASS_ZBC, "d,s,t", MATCH_CLMUL, MASK_CLMUL, match_opcode, 0 },
|
||||
{"clmulh", 0, INSN_CLASS_ZBC, "d,s,t", MATCH_CLMULH, MASK_CLMULH, match_opcode, 0 },
|
||||
{"clmulr", 0, INSN_CLASS_ZBC, "d,s,t", MATCH_CLMULR, MASK_CLMULR, match_opcode, 0 },
|
||||
|
||||
/* Single-precision floating-point instruction subset. */
|
||||
{"frcsr", 0, INSN_CLASS_F, "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS },
|
||||
{"frsr", 0, INSN_CLASS_F, "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS },
|
||||
@ -976,10 +931,6 @@ const struct riscv_ext_version riscv_ext_version_table[] =
|
||||
|
||||
{"zihintpause", ISA_SPEC_CLASS_DRAFT, 1, 0},
|
||||
|
||||
{"zba", ISA_SPEC_CLASS_DRAFT, 0, 93},
|
||||
{"zbb", ISA_SPEC_CLASS_DRAFT, 0, 93},
|
||||
{"zbc", ISA_SPEC_CLASS_DRAFT, 0, 93},
|
||||
|
||||
/* Terminate the list. */
|
||||
{NULL, 0, 0, 0}
|
||||
};
|
||||
|
||||
Loading…
Reference in New Issue
Block a user