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Add support for the m32r2 processor

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This commit is contained in:
Nick Clifton 2003-12-11 11:33:44 +00:00
parent 8bfdb6721b
commit 16b47b253e
30 changed files with 16057 additions and 168 deletions
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32
sim/m32r/ChangeLog
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@ -1,3 +1,35 @@
2003-12-11 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
* Makefile.in: Add support for new machine m32r2.
* cpu2.c: New file for m32r2 support.
* cpu2.h: Likewise.
* decode2.c: Likewise.
* decode2.h: Likewise.
* m32r2.c: Likewise.
* mloop2.in: Likewise.
* model2.c: Likewise.
* sem2-switch.c: Likewise.
* arch.c: Regenerate.
* arch.h: Regenerate.
* cpu.c: Regenerate.
* arch.c: Regenerate.
* cpuall.c: Regenerate.
* cpux.c: Regenerate.
* cpux.h: Regenerate.
* decode.c: Regenerate.
* decode.h: Regenerate.
* decodex.c: Regenerate.
* decodex.h: Regenerate.
* model.c: Regenerate.
* modelx.c: Regenerate.
* sem-switch.c: Regenerate.
* sem.c: Regenerate.
* semx-switch.c: Regenerate.
* m32r-sim.h: Add EVB register support.
* sim-if.c: Likewise.
* sim-main.h: Likewise.
* traps.c: Likewise.
2003-09-08 Dave Brolley <brolley@redhat.com>
On behalf of Doug Evans <dje@sebabeach.org>

40
sim/m32r/Makefile.in
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@ -1,5 +1,5 @@
# Makefile template for Configure for the m32r simulator
# Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
# Copyright (C) 1996, 1997, 1998, 1999, 2000, 2003 Free Software Foundation, Inc.
# Contributed by Cygnus Support.
#
# This file is part of GDB, the GNU debugger.
@ -22,6 +22,7 @@
M32R_OBJS = m32r.o cpu.o decode.o sem.o model.o mloop.o
M32RX_OBJS = m32rx.o cpux.o decodex.o modelx.o mloopx.o
M32R2_OBJS = m32r2.o cpu2.o decode2.o model2.o mloop2.o
CONFIG_DEVICES = dv-sockser.o
CONFIG_DEVICES =
@ -38,6 +39,7 @@ SIM_OBJS = \
sim-if.o arch.o \
$(M32R_OBJS) \
$(M32RX_OBJS) \
$(M32R2_OBJS) \
traps.o devices.o \
$(CONFIG_DEVICES)
@ -113,10 +115,35 @@ decodex.o: decodex.c $(M32RXF_INCLUDE_DEPS)
semx.o: semx.c $(M32RXF_INCLUDE_DEPS)
modelx.o: modelx.c $(M32RXF_INCLUDE_DEPS)
# M32R2 objs
M32R2F_INCLUDE_DEPS = \
$(CGEN_MAIN_CPU_DEPS) \
cpu2.h decode2.h eng2.h
m32r2.o: m32r2.c $(M32R2F_INCLUDE_DEPS)
# FIXME: Use of `mono' is wip.
mloop2.c eng2.h: stamp-2mloop
stamp-2mloop: $(srcdir)/../common/genmloop.sh mloop2.in Makefile
$(SHELL) $(srccom)/genmloop.sh \
-mono -no-fast -pbb -parallel-write -switch sem2-switch.c \
-cpu m32r2f -infile $(srcdir)/mloop2.in
$(SHELL) $(srcroot)/move-if-change eng.hin eng2.h
$(SHELL) $(srcroot)/move-if-change mloop.cin mloop2.c
touch stamp-2mloop
mloop2.o: mloop2.c sem2-switch.c $(M32R2F_INCLUDE_DEPS)
cpu2.o: cpu2.c $(M32R2F_INCLUDE_DEPS)
decode2.o: decode2.c $(M32R2F_INCLUDE_DEPS)
sem2.o: sem2.c $(M32R2F_INCLUDE_DEPS)
model2.o: model2.c $(M32R2F_INCLUDE_DEPS)
m32r-clean:
rm -f mloop.c eng.h stamp-mloop
rm -f mloopx.c engx.h stamp-xmloop
rm -f stamp-arch stamp-cpu stamp-xcpu
rm -f mloop2.c eng2.h stamp-2mloop
rm -f stamp-arch stamp-cpu stamp-xcpu stamp-2cpu
rm -f tmp-*
# cgen support, enable with --enable-cgen-maint
@ -148,3 +175,12 @@ stamp-xcpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(CGEN_CPU_DIR)/
EXTRAFILES="$(CGEN_CPU_SEMSW)"
touch stamp-xcpu
cpux.h semx-switch.c modelx.c decodex.c decodex.h: $(CGEN_MAINT) stamp-xcpu
stamp-2cpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(CGEN_CPU_DIR)/m32r.cpu
$(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \
cpu=m32r2f mach=m32r2 SUFFIX=2 \
archfile=$(CGEN_CPU_DIR)/m32r.cpu \
FLAGS="with-scache with-profile=fn" \
EXTRAFILES="$(CGEN_CPU_SEMSW)"
touch stamp-2cpu
cpu2.h sem2-switch.c model2.c decode2.c decode2.h: $(CGEN_MAINT) stamp-2cpu

5
sim/m32r/arch.c
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@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -32,6 +32,9 @@ const MACH *sim_machs[] =
#endif
#ifdef HAVE_CPU_M32RXF
& m32rx_mach,
#endif
#ifdef HAVE_CPU_M32R2F
& m32r2_mach,
#endif
0
};

9
sim/m32r/arch.h
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@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -29,7 +29,8 @@ with this program; if not, write to the Free Software Foundation, Inc.,
/* Enum declaration for model types. */
typedef enum model_type {
MODEL_M32R_D, MODEL_TEST, MODEL_M32RX, MODEL_MAX
MODEL_M32R_D, MODEL_TEST, MODEL_M32RX, MODEL_M32R2
, MODEL_MAX
} MODEL_TYPE;
#define MAX_MODELS ((int) MODEL_MAX)
@ -39,7 +40,9 @@ typedef enum unit_type {
UNIT_NONE, UNIT_M32R_D_U_STORE, UNIT_M32R_D_U_LOAD, UNIT_M32R_D_U_CTI
, UNIT_M32R_D_U_MAC, UNIT_M32R_D_U_CMP, UNIT_M32R_D_U_EXEC, UNIT_TEST_U_EXEC
, UNIT_M32RX_U_STORE, UNIT_M32RX_U_LOAD, UNIT_M32RX_U_CTI, UNIT_M32RX_U_MAC
, UNIT_M32RX_U_CMP, UNIT_M32RX_U_EXEC, UNIT_MAX
, UNIT_M32RX_U_CMP, UNIT_M32RX_U_EXEC, UNIT_M32R2_U_STORE, UNIT_M32R2_U_LOAD
, UNIT_M32R2_U_CTI, UNIT_M32R2_U_MAC, UNIT_M32R2_U_CMP, UNIT_M32R2_U_EXEC
, UNIT_MAX
} UNIT_TYPE;
#define MAX_UNITS (2)

2
sim/m32r/cpu.c
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@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
This file is part of the GNU simulators.

55
sim/m32r/cpu.h
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -123,6 +123,9 @@ union sem_fields {
struct { /* no operands */
int empty;
} fmt_empty;
struct { /* */
UINT f_uimm8;
} sfmt_clrpsw;
struct { /* */
UINT f_uimm4;
} sfmt_trap;
@ -152,6 +155,13 @@ union sem_fields {
unsigned char in_sr;
unsigned char out_h_gr_SI_14;
} sfmt_jl;
struct { /* */
SI* i_sr;
INT f_simm16;
UINT f_r2;
UINT f_uimm3;
unsigned char in_sr;
} sfmt_bset;
struct { /* */
SI* i_dr;
UINT f_r1;
@ -628,6 +638,49 @@ struct scache {
f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
f_uimm4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
#define EXTRACT_IFMT_CLRPSW_VARS \
UINT f_op1; \
UINT f_r1; \
UINT f_uimm8; \
unsigned int length;
#define EXTRACT_IFMT_CLRPSW_CODE \
length = 2; \
f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
f_uimm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \
#define EXTRACT_IFMT_BSET_VARS \
UINT f_op1; \
UINT f_bit4; \
UINT f_uimm3; \
UINT f_op2; \
UINT f_r2; \
INT f_simm16; \
unsigned int length;
#define EXTRACT_IFMT_BSET_CODE \
length = 4; \
f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
f_bit4 = EXTRACT_MSB0_UINT (insn, 32, 4, 1); \
f_uimm3 = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
#define EXTRACT_IFMT_BTST_VARS \
UINT f_op1; \
UINT f_bit4; \
UINT f_uimm3; \
UINT f_op2; \
UINT f_r2; \
unsigned int length;
#define EXTRACT_IFMT_BTST_CODE \
length = 2; \
f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
f_bit4 = EXTRACT_MSB0_UINT (insn, 16, 4, 1); \
f_uimm3 = EXTRACT_MSB0_UINT (insn, 16, 5, 3); \
f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
/* Collection of various things for the trace handler to use. */
typedef struct trace_record {

197
sim/m32r/cpu2.c Normal file
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@ -0,0 +1,197 @@
/* Misc. support for CPU family m32r2f.
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
This file is part of the GNU simulators.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#define WANT_CPU m32r2f
#define WANT_CPU_M32R2F
#include "sim-main.h"
#include "cgen-ops.h"
/* Get the value of h-pc. */
USI
m32r2f_h_pc_get (SIM_CPU *current_cpu)
{
return CPU (h_pc);
}
/* Set a value for h-pc. */
void
m32r2f_h_pc_set (SIM_CPU *current_cpu, USI newval)
{
CPU (h_pc) = newval;
}
/* Get the value of h-gr. */
SI
m32r2f_h_gr_get (SIM_CPU *current_cpu, UINT regno)
{
return CPU (h_gr[regno]);
}
/* Set a value for h-gr. */
void
m32r2f_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
{
CPU (h_gr[regno]) = newval;
}
/* Get the value of h-cr. */
USI
m32r2f_h_cr_get (SIM_CPU *current_cpu, UINT regno)
{
return GET_H_CR (regno);
}
/* Set a value for h-cr. */
void
m32r2f_h_cr_set (SIM_CPU *current_cpu, UINT regno, USI newval)
{
SET_H_CR (regno, newval);
}
/* Get the value of h-accum. */
DI
m32r2f_h_accum_get (SIM_CPU *current_cpu)
{
return GET_H_ACCUM ();
}
/* Set a value for h-accum. */
void
m32r2f_h_accum_set (SIM_CPU *current_cpu, DI newval)
{
SET_H_ACCUM (newval);
}
/* Get the value of h-accums. */
DI
m32r2f_h_accums_get (SIM_CPU *current_cpu, UINT regno)
{
return GET_H_ACCUMS (regno);
}
/* Set a value for h-accums. */
void
m32r2f_h_accums_set (SIM_CPU *current_cpu, UINT regno, DI newval)
{
SET_H_ACCUMS (regno, newval);
}
/* Get the value of h-cond. */
BI
m32r2f_h_cond_get (SIM_CPU *current_cpu)
{
return CPU (h_cond);
}
/* Set a value for h-cond. */
void
m32r2f_h_cond_set (SIM_CPU *current_cpu, BI newval)
{
CPU (h_cond) = newval;
}
/* Get the value of h-psw. */
UQI
m32r2f_h_psw_get (SIM_CPU *current_cpu)
{
return GET_H_PSW ();
}
/* Set a value for h-psw. */
void
m32r2f_h_psw_set (SIM_CPU *current_cpu, UQI newval)
{
SET_H_PSW (newval);
}
/* Get the value of h-bpsw. */
UQI
m32r2f_h_bpsw_get (SIM_CPU *current_cpu)
{
return CPU (h_bpsw);
}
/* Set a value for h-bpsw. */
void
m32r2f_h_bpsw_set (SIM_CPU *current_cpu, UQI newval)
{
CPU (h_bpsw) = newval;
}
/* Get the value of h-bbpsw. */
UQI
m32r2f_h_bbpsw_get (SIM_CPU *current_cpu)
{
return CPU (h_bbpsw);
}
/* Set a value for h-bbpsw. */
void
m32r2f_h_bbpsw_set (SIM_CPU *current_cpu, UQI newval)
{
CPU (h_bbpsw) = newval;
}
/* Get the value of h-lock. */
BI
m32r2f_h_lock_get (SIM_CPU *current_cpu)
{
return CPU (h_lock);
}
/* Set a value for h-lock. */
void
m32r2f_h_lock_set (SIM_CPU *current_cpu, BI newval)
{
CPU (h_lock) = newval;
}
/* Record trace results for INSN. */
void
m32r2f_record_trace_results (SIM_CPU *current_cpu, CGEN_INSN *insn,
int *indices, TRACE_RECORD *tr)
{
}

1046
sim/m32r/cpu2.h Normal file
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File diff suppressed because it is too large Load Diff

10
sim/m32r/cpuall.h
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@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -41,8 +41,16 @@ with this program; if not, write to the Free Software Foundation, Inc.,
#include "decodex.h"
#endif
#ifdef WANT_CPU_M32R2F
#include "eng2.h"
#include "cgen-engine.h"
#include "cpu2.h"
#include "decode2.h"
#endif
extern const MACH m32r_mach;
extern const MACH m32rx_mach;
extern const MACH m32r2_mach;
#ifndef WANT_CPU
/* The ARGBUF struct. */

2
sim/m32r/cpux.c
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
This file is part of the GNU simulators.

78
sim/m32r/cpux.h
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -128,6 +128,9 @@ union sem_fields {
struct { /* no operands */
int empty;
} fmt_empty;
struct { /* */
UINT f_uimm8;
} sfmt_clrpsw;
struct { /* */
UINT f_uimm4;
} sfmt_trap;
@ -174,6 +177,13 @@ union sem_fields {
unsigned char in_sr;
unsigned char out_h_gr_SI_14;
} sfmt_jl;
struct { /* */
SI* i_sr;
INT f_simm16;
UINT f_r2;
UINT f_uimm3;
unsigned char in_sr;
} sfmt_bset;
struct { /* */
SI* i_dr;
UINT f_r1;
@ -725,6 +735,49 @@ struct scache {
f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
#define EXTRACT_IFMT_CLRPSW_VARS \
UINT f_op1; \
UINT f_r1; \
UINT f_uimm8; \
unsigned int length;
#define EXTRACT_IFMT_CLRPSW_CODE \
length = 2; \
f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
f_uimm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \
#define EXTRACT_IFMT_BSET_VARS \
UINT f_op1; \
UINT f_bit4; \
UINT f_uimm3; \
UINT f_op2; \
UINT f_r2; \
INT f_simm16; \
unsigned int length;
#define EXTRACT_IFMT_BSET_CODE \
length = 4; \
f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
f_bit4 = EXTRACT_MSB0_UINT (insn, 32, 4, 1); \
f_uimm3 = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
#define EXTRACT_IFMT_BTST_VARS \
UINT f_op1; \
UINT f_bit4; \
UINT f_uimm3; \
UINT f_op2; \
UINT f_r2; \
unsigned int length;
#define EXTRACT_IFMT_BTST_CODE \
length = 2; \
f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
f_bit4 = EXTRACT_MSB0_UINT (insn, 16, 4, 1); \
f_uimm3 = EXTRACT_MSB0_UINT (insn, 16, 5, 3); \
f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
/* Queued output values of an instruction. */
struct parexec {
@ -921,6 +974,16 @@ struct parexec {
USI h_memory_SI_new_src2_idx;
SI src2;
} sfmt_st_plus;
struct { /* e.g. sth $src1,@$src2+ */
HI h_memory_HI_new_src2;
USI h_memory_HI_new_src2_idx;
SI src2;
} sfmt_sth_plus;
struct { /* e.g. stb $src1,@$src2+ */
QI h_memory_QI_new_src2;
USI h_memory_QI_new_src2_idx;
SI src2;
} sfmt_stb_plus;
struct { /* e.g. trap $uimm4 */
UQI h_bbpsw_UQI;
UQI h_bpsw_UQI;
@ -955,6 +1018,19 @@ struct parexec {
struct { /* e.g. sc */
int empty;
} sfmt_sc;
struct { /* e.g. clrpsw $uimm8 */
USI h_cr_USI_0;
} sfmt_clrpsw;
struct { /* e.g. setpsw $uimm8 */
USI h_cr_USI_0;
} sfmt_setpsw;
struct { /* e.g. bset $uimm3,@($slo16,$sr) */
QI h_memory_QI_add__DFLT_sr_slo16;
USI h_memory_QI_add__DFLT_sr_slo16_idx;
} sfmt_bset;
struct { /* e.g. btst $uimm3,$sr */
BI condbit;
} sfmt_btst;
} operands;
/* For conditionally written operands, bitmask of which ones were. */
int written;

117
sim/m32r/decode.c
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@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -145,6 +145,11 @@ static const struct insn_sem m32rbf_insn_sem[] =
{ M32R_INSN_SUBX, M32RBF_INSN_SUBX, M32RBF_SFMT_ADDX },
{ M32R_INSN_TRAP, M32RBF_INSN_TRAP, M32RBF_SFMT_TRAP },
{ M32R_INSN_UNLOCK, M32RBF_INSN_UNLOCK, M32RBF_SFMT_UNLOCK },
{ M32R_INSN_CLRPSW, M32RBF_INSN_CLRPSW, M32RBF_SFMT_CLRPSW },
{ M32R_INSN_SETPSW, M32RBF_INSN_SETPSW, M32RBF_SFMT_SETPSW },
{ M32R_INSN_BSET, M32RBF_INSN_BSET, M32RBF_SFMT_BSET },
{ M32R_INSN_BCLR, M32RBF_INSN_BCLR, M32RBF_SFMT_BSET },
{ M32R_INSN_BTST, M32RBF_INSN_BTST, M32RBF_SFMT_BTST },
};
static const struct insn_sem m32rbf_insn_sem_invalid = {
@ -237,6 +242,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
case 12 : itype = M32RBF_INSN_AND; goto extract_sfmt_add;
case 13 : itype = M32RBF_INSN_XOR; goto extract_sfmt_add;
case 14 : itype = M32RBF_INSN_OR; goto extract_sfmt_add;
case 15 : itype = M32RBF_INSN_BTST; goto extract_sfmt_btst;
case 16 : itype = M32RBF_INSN_SRL; goto extract_sfmt_add;
case 18 : itype = M32RBF_INSN_SRA; goto extract_sfmt_add;
case 20 : itype = M32RBF_INSN_SLL; goto extract_sfmt_add;
@ -344,6 +350,8 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
switch (val)
{
case 0 : itype = M32RBF_INSN_NOP; goto extract_sfmt_nop;
case 1 : itype = M32RBF_INSN_SETPSW; goto extract_sfmt_setpsw;
case 2 : itype = M32RBF_INSN_CLRPSW; goto extract_sfmt_clrpsw;
case 12 : itype = M32RBF_INSN_BC8; goto extract_sfmt_bc8;
case 13 : itype = M32RBF_INSN_BNC8; goto extract_sfmt_bc8;
case 14 : itype = M32RBF_INSN_BL8; goto extract_sfmt_bl8;
@ -367,13 +375,15 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
case 126 : /* fall through */
case 127 :
{
unsigned int val = (((insn >> 8) & (3 << 0)));
unsigned int val = (((insn >> 8) & (15 << 0)));
switch (val)
{
case 0 : itype = M32RBF_INSN_BC8; goto extract_sfmt_bc8;
case 1 : itype = M32RBF_INSN_BNC8; goto extract_sfmt_bc8;
case 2 : itype = M32RBF_INSN_BL8; goto extract_sfmt_bl8;
case 3 : itype = M32RBF_INSN_BRA8; goto extract_sfmt_bra8;
case 1 : itype = M32RBF_INSN_SETPSW; goto extract_sfmt_setpsw;
case 2 : itype = M32RBF_INSN_CLRPSW; goto extract_sfmt_clrpsw;
case 12 : itype = M32RBF_INSN_BC8; goto extract_sfmt_bc8;
case 13 : itype = M32RBF_INSN_BNC8; goto extract_sfmt_bc8;
case 14 : itype = M32RBF_INSN_BL8; goto extract_sfmt_bl8;
case 15 : itype = M32RBF_INSN_BRA8; goto extract_sfmt_bra8;
default : itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
}
}
@ -395,6 +405,8 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
case 160 : itype = M32RBF_INSN_STB_D; goto extract_sfmt_stb_d;
case 162 : itype = M32RBF_INSN_STH_D; goto extract_sfmt_sth_d;
case 164 : itype = M32RBF_INSN_ST_D; goto extract_sfmt_st_d;
case 166 : itype = M32RBF_INSN_BSET; goto extract_sfmt_bset;
case 167 : itype = M32RBF_INSN_BCLR; goto extract_sfmt_bset;
case 168 : itype = M32RBF_INSN_LDB_D; goto extract_sfmt_ldb_d;
case 169 : itype = M32RBF_INSN_LDUB_D; goto extract_sfmt_ldb_d;
case 170 : itype = M32RBF_INSN_LDH_D; goto extract_sfmt_ldh_d;
@ -2001,6 +2013,99 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
FLD (in_src2) = f_r2;
}
#endif
#undef FLD
return idesc;
}
extract_sfmt_clrpsw:
{
const IDESC *idesc = &m32rbf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_clrpsw.f
UINT f_uimm8;
f_uimm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8);
/* Record the fields for the semantic handler. */
FLD (f_uimm8) = f_uimm8;
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_clrpsw", "f_uimm8 0x%x", 'x', f_uimm8, (char *) 0));
#undef FLD
return idesc;
}
extract_sfmt_setpsw:
{
const IDESC *idesc = &m32rbf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_clrpsw.f
UINT f_uimm8;
f_uimm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8);
/* Record the fields for the semantic handler. */
FLD (f_uimm8) = f_uimm8;
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_setpsw", "f_uimm8 0x%x", 'x', f_uimm8, (char *) 0));
#undef FLD
return idesc;
}
extract_sfmt_bset:
{
const IDESC *idesc = &m32rbf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_bset.f
UINT f_uimm3;
UINT f_r2;
INT f_simm16;
f_uimm3 = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
/* Record the fields for the semantic handler. */
FLD (f_simm16) = f_simm16;
FLD (f_r2) = f_r2;
FLD (f_uimm3) = f_uimm3;
FLD (i_sr) = & CPU (h_gr)[f_r2];
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bset", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_uimm3 0x%x", 'x', f_uimm3, "sr 0x%x", 'x', f_r2, (char *) 0));
#if WITH_PROFILE_MODEL_P
/* Record the fields for profiling. */
if (PROFILE_MODEL_P (current_cpu))
{
FLD (in_sr) = f_r2;
}
#endif
#undef FLD
return idesc;
}
extract_sfmt_btst:
{
const IDESC *idesc = &m32rbf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_bset.f
UINT f_uimm3;
UINT f_r2;
f_uimm3 = EXTRACT_MSB0_UINT (insn, 16, 5, 3);
f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
/* Record the fields for the semantic handler. */
FLD (f_r2) = f_r2;
FLD (f_uimm3) = f_uimm3;
FLD (i_sr) = & CPU (h_gr)[f_r2];
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_btst", "f_r2 0x%x", 'x', f_r2, "f_uimm3 0x%x", 'x', f_uimm3, "sr 0x%x", 'x', f_r2, (char *) 0));
#if WITH_PROFILE_MODEL_P
/* Record the fields for profiling. */
if (PROFILE_MODEL_P (current_cpu))
{
FLD (in_sr) = f_r2;
}
#endif
#undef FLD
return idesc;
}

8
sim/m32r/decode.h
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -60,7 +60,8 @@ typedef enum m32rbf_insn_type {
, M32RBF_INSN_ST, M32RBF_INSN_ST_D, M32RBF_INSN_STB, M32RBF_INSN_STB_D
, M32RBF_INSN_STH, M32RBF_INSN_STH_D, M32RBF_INSN_ST_PLUS, M32RBF_INSN_ST_MINUS
, M32RBF_INSN_SUB, M32RBF_INSN_SUBV, M32RBF_INSN_SUBX, M32RBF_INSN_TRAP
, M32RBF_INSN_UNLOCK, M32RBF_INSN__MAX
, M32RBF_INSN_UNLOCK, M32RBF_INSN_CLRPSW, M32RBF_INSN_SETPSW, M32RBF_INSN_BSET
, M32RBF_INSN_BCLR, M32RBF_INSN_BTST, M32RBF_INSN__MAX
} M32RBF_INSN_TYPE;
/* Enum declaration for semantic formats in cpu family m32rbf. */
@ -78,7 +79,8 @@ typedef enum m32rbf_sfmt_type {
, M32RBF_SFMT_NOP, M32RBF_SFMT_RAC, M32RBF_SFMT_RTE, M32RBF_SFMT_SETH
, M32RBF_SFMT_SLL3, M32RBF_SFMT_SLLI, M32RBF_SFMT_ST, M32RBF_SFMT_ST_D
, M32RBF_SFMT_STB, M32RBF_SFMT_STB_D, M32RBF_SFMT_STH, M32RBF_SFMT_STH_D
, M32RBF_SFMT_ST_PLUS, M32RBF_SFMT_TRAP, M32RBF_SFMT_UNLOCK
, M32RBF_SFMT_ST_PLUS, M32RBF_SFMT_TRAP, M32RBF_SFMT_UNLOCK, M32RBF_SFMT_CLRPSW
, M32RBF_SFMT_SETPSW, M32RBF_SFMT_BSET, M32RBF_SFMT_BTST
} M32RBF_SFMT_TYPE;
/* Function unit handlers (user written). */

2609
sim/m32r/decode2.c Normal file
View File

File diff suppressed because it is too large Load Diff

151
sim/m32r/decode2.h Normal file
View File

@ -0,0 +1,151 @@
/* Decode header for m32r2f.
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
This file is part of the GNU simulators.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#ifndef M32R2F_DECODE_H
#define M32R2F_DECODE_H
extern const IDESC *m32r2f_decode (SIM_CPU *, IADDR,
CGEN_INSN_INT, CGEN_INSN_INT,
ARGBUF *);
extern void m32r2f_init_idesc_table (SIM_CPU *);
extern void m32r2f_sem_init_idesc_table (SIM_CPU *);
extern void m32r2f_semf_init_idesc_table (SIM_CPU *);
/* Enum declaration for instructions in cpu family m32r2f. */
typedef enum m32r2f_insn_type {
M32R2F_INSN_X_INVALID, M32R2F_INSN_X_AFTER, M32R2F_INSN_X_BEFORE, M32R2F_INSN_X_CTI_CHAIN
, M32R2F_INSN_X_CHAIN, M32R2F_INSN_X_BEGIN, M32R2F_INSN_ADD, M32R2F_INSN_ADD3
, M32R2F_INSN_AND, M32R2F_INSN_AND3, M32R2F_INSN_OR, M32R2F_INSN_OR3
, M32R2F_INSN_XOR, M32R2F_INSN_XOR3, M32R2F_INSN_ADDI, M32R2F_INSN_ADDV
, M32R2F_INSN_ADDV3, M32R2F_INSN_ADDX, M32R2F_INSN_BC8, M32R2F_INSN_BC24
, M32R2F_INSN_BEQ, M32R2F_INSN_BEQZ, M32R2F_INSN_BGEZ, M32R2F_INSN_BGTZ
, M32R2F_INSN_BLEZ, M32R2F_INSN_BLTZ, M32R2F_INSN_BNEZ, M32R2F_INSN_BL8
, M32R2F_INSN_BL24, M32R2F_INSN_BCL8, M32R2F_INSN_BCL24, M32R2F_INSN_BNC8
, M32R2F_INSN_BNC24, M32R2F_INSN_BNE, M32R2F_INSN_BRA8, M32R2F_INSN_BRA24
, M32R2F_INSN_BNCL8, M32R2F_INSN_BNCL24, M32R2F_INSN_CMP, M32R2F_INSN_CMPI
, M32R2F_INSN_CMPU, M32R2F_INSN_CMPUI, M32R2F_INSN_CMPEQ, M32R2F_INSN_CMPZ
, M32R2F_INSN_DIV, M32R2F_INSN_DIVU, M32R2F_INSN_REM, M32R2F_INSN_REMU
, M32R2F_INSN_REMH, M32R2F_INSN_REMUH, M32R2F_INSN_REMB, M32R2F_INSN_REMUB
, M32R2F_INSN_DIVUH, M32R2F_INSN_DIVB, M32R2F_INSN_DIVUB, M32R2F_INSN_DIVH
, M32R2F_INSN_JC, M32R2F_INSN_JNC, M32R2F_INSN_JL, M32R2F_INSN_JMP
, M32R2F_INSN_LD, M32R2F_INSN_LD_D, M32R2F_INSN_LDB, M32R2F_INSN_LDB_D
, M32R2F_INSN_LDH, M32R2F_INSN_LDH_D, M32R2F_INSN_LDUB, M32R2F_INSN_LDUB_D
, M32R2F_INSN_LDUH, M32R2F_INSN_LDUH_D, M32R2F_INSN_LD_PLUS, M32R2F_INSN_LD24
, M32R2F_INSN_LDI8, M32R2F_INSN_LDI16, M32R2F_INSN_LOCK, M32R2F_INSN_MACHI_A
, M32R2F_INSN_MACLO_A, M32R2F_INSN_MACWHI_A, M32R2F_INSN_MACWLO_A, M32R2F_INSN_MUL
, M32R2F_INSN_MULHI_A, M32R2F_INSN_MULLO_A, M32R2F_INSN_MULWHI_A, M32R2F_INSN_MULWLO_A
, M32R2F_INSN_MV, M32R2F_INSN_MVFACHI_A, M32R2F_INSN_MVFACLO_A, M32R2F_INSN_MVFACMI_A
, M32R2F_INSN_MVFC, M32R2F_INSN_MVTACHI_A, M32R2F_INSN_MVTACLO_A, M32R2F_INSN_MVTC
, M32R2F_INSN_NEG, M32R2F_INSN_NOP, M32R2F_INSN_NOT, M32R2F_INSN_RAC_DSI
, M32R2F_INSN_RACH_DSI, M32R2F_INSN_RTE, M32R2F_INSN_SETH, M32R2F_INSN_SLL
, M32R2F_INSN_SLL3, M32R2F_INSN_SLLI, M32R2F_INSN_SRA, M32R2F_INSN_SRA3
, M32R2F_INSN_SRAI, M32R2F_INSN_SRL, M32R2F_INSN_SRL3, M32R2F_INSN_SRLI
, M32R2F_INSN_ST, M32R2F_INSN_ST_D, M32R2F_INSN_STB, M32R2F_INSN_STB_D
, M32R2F_INSN_STH, M32R2F_INSN_STH_D, M32R2F_INSN_ST_PLUS, M32R2F_INSN_STH_PLUS
, M32R2F_INSN_STB_PLUS, M32R2F_INSN_ST_MINUS, M32R2F_INSN_SUB, M32R2F_INSN_SUBV
, M32R2F_INSN_SUBX, M32R2F_INSN_TRAP, M32R2F_INSN_UNLOCK, M32R2F_INSN_SATB
, M32R2F_INSN_SATH, M32R2F_INSN_SAT, M32R2F_INSN_PCMPBZ, M32R2F_INSN_SADD
, M32R2F_INSN_MACWU1, M32R2F_INSN_MSBLO, M32R2F_INSN_MULWU1, M32R2F_INSN_MACLH1
, M32R2F_INSN_SC, M32R2F_INSN_SNC, M32R2F_INSN_CLRPSW, M32R2F_INSN_SETPSW
, M32R2F_INSN_BSET, M32R2F_INSN_BCLR, M32R2F_INSN_BTST, M32R2F_INSN_PAR_ADD
, M32R2F_INSN_WRITE_ADD, M32R2F_INSN_PAR_AND, M32R2F_INSN_WRITE_AND, M32R2F_INSN_PAR_OR
, M32R2F_INSN_WRITE_OR, M32R2F_INSN_PAR_XOR, M32R2F_INSN_WRITE_XOR, M32R2F_INSN_PAR_ADDI
, M32R2F_INSN_WRITE_ADDI, M32R2F_INSN_PAR_ADDV, M32R2F_INSN_WRITE_ADDV, M32R2F_INSN_PAR_ADDX
, M32R2F_INSN_WRITE_ADDX, M32R2F_INSN_PAR_BC8, M32R2F_INSN_WRITE_BC8, M32R2F_INSN_PAR_BL8
, M32R2F_INSN_WRITE_BL8, M32R2F_INSN_PAR_BCL8, M32R2F_INSN_WRITE_BCL8, M32R2F_INSN_PAR_BNC8
, M32R2F_INSN_WRITE_BNC8, M32R2F_INSN_PAR_BRA8, M32R2F_INSN_WRITE_BRA8, M32R2F_INSN_PAR_BNCL8
, M32R2F_INSN_WRITE_BNCL8, M32R2F_INSN_PAR_CMP, M32R2F_INSN_WRITE_CMP, M32R2F_INSN_PAR_CMPU
, M32R2F_INSN_WRITE_CMPU, M32R2F_INSN_PAR_CMPEQ, M32R2F_INSN_WRITE_CMPEQ, M32R2F_INSN_PAR_CMPZ
, M32R2F_INSN_WRITE_CMPZ, M32R2F_INSN_PAR_JC, M32R2F_INSN_WRITE_JC, M32R2F_INSN_PAR_JNC
, M32R2F_INSN_WRITE_JNC, M32R2F_INSN_PAR_JL, M32R2F_INSN_WRITE_JL, M32R2F_INSN_PAR_JMP
, M32R2F_INSN_WRITE_JMP, M32R2F_INSN_PAR_LD, M32R2F_INSN_WRITE_LD, M32R2F_INSN_PAR_LDB
, M32R2F_INSN_WRITE_LDB, M32R2F_INSN_PAR_LDH, M32R2F_INSN_WRITE_LDH, M32R2F_INSN_PAR_LDUB
, M32R2F_INSN_WRITE_LDUB, M32R2F_INSN_PAR_LDUH, M32R2F_INSN_WRITE_LDUH, M32R2F_INSN_PAR_LD_PLUS
, M32R2F_INSN_WRITE_LD_PLUS, M32R2F_INSN_PAR_LDI8, M32R2F_INSN_WRITE_LDI8, M32R2F_INSN_PAR_LOCK
, M32R2F_INSN_WRITE_LOCK, M32R2F_INSN_PAR_MACHI_A, M32R2F_INSN_WRITE_MACHI_A, M32R2F_INSN_PAR_MACLO_A
, M32R2F_INSN_WRITE_MACLO_A, M32R2F_INSN_PAR_MACWHI_A, M32R2F_INSN_WRITE_MACWHI_A, M32R2F_INSN_PAR_MACWLO_A
, M32R2F_INSN_WRITE_MACWLO_A, M32R2F_INSN_PAR_MUL, M32R2F_INSN_WRITE_MUL, M32R2F_INSN_PAR_MULHI_A
, M32R2F_INSN_WRITE_MULHI_A, M32R2F_INSN_PAR_MULLO_A, M32R2F_INSN_WRITE_MULLO_A, M32R2F_INSN_PAR_MULWHI_A
, M32R2F_INSN_WRITE_MULWHI_A, M32R2F_INSN_PAR_MULWLO_A, M32R2F_INSN_WRITE_MULWLO_A, M32R2F_INSN_PAR_MV
, M32R2F_INSN_WRITE_MV, M32R2F_INSN_PAR_MVFACHI_A, M32R2F_INSN_WRITE_MVFACHI_A, M32R2F_INSN_PAR_MVFACLO_A
, M32R2F_INSN_WRITE_MVFACLO_A, M32R2F_INSN_PAR_MVFACMI_A, M32R2F_INSN_WRITE_MVFACMI_A, M32R2F_INSN_PAR_MVFC
, M32R2F_INSN_WRITE_MVFC, M32R2F_INSN_PAR_MVTACHI_A, M32R2F_INSN_WRITE_MVTACHI_A, M32R2F_INSN_PAR_MVTACLO_A
, M32R2F_INSN_WRITE_MVTACLO_A, M32R2F_INSN_PAR_MVTC, M32R2F_INSN_WRITE_MVTC, M32R2F_INSN_PAR_NEG
, M32R2F_INSN_WRITE_NEG, M32R2F_INSN_PAR_NOP, M32R2F_INSN_WRITE_NOP, M32R2F_INSN_PAR_NOT
, M32R2F_INSN_WRITE_NOT, M32R2F_INSN_PAR_RAC_DSI, M32R2F_INSN_WRITE_RAC_DSI, M32R2F_INSN_PAR_RACH_DSI
, M32R2F_INSN_WRITE_RACH_DSI, M32R2F_INSN_PAR_RTE, M32R2F_INSN_WRITE_RTE, M32R2F_INSN_PAR_SLL
, M32R2F_INSN_WRITE_SLL, M32R2F_INSN_PAR_SLLI, M32R2F_INSN_WRITE_SLLI, M32R2F_INSN_PAR_SRA
, M32R2F_INSN_WRITE_SRA, M32R2F_INSN_PAR_SRAI, M32R2F_INSN_WRITE_SRAI, M32R2F_INSN_PAR_SRL
, M32R2F_INSN_WRITE_SRL, M32R2F_INSN_PAR_SRLI, M32R2F_INSN_WRITE_SRLI, M32R2F_INSN_PAR_ST
, M32R2F_INSN_WRITE_ST, M32R2F_INSN_PAR_STB, M32R2F_INSN_WRITE_STB, M32R2F_INSN_PAR_STH
, M32R2F_INSN_WRITE_STH, M32R2F_INSN_PAR_ST_PLUS, M32R2F_INSN_WRITE_ST_PLUS, M32R2F_INSN_PAR_STH_PLUS
, M32R2F_INSN_WRITE_STH_PLUS, M32R2F_INSN_PAR_STB_PLUS, M32R2F_INSN_WRITE_STB_PLUS, M32R2F_INSN_PAR_ST_MINUS
, M32R2F_INSN_WRITE_ST_MINUS, M32R2F_INSN_PAR_SUB, M32R2F_INSN_WRITE_SUB, M32R2F_INSN_PAR_SUBV
, M32R2F_INSN_WRITE_SUBV, M32R2F_INSN_PAR_SUBX, M32R2F_INSN_WRITE_SUBX, M32R2F_INSN_PAR_TRAP
, M32R2F_INSN_WRITE_TRAP, M32R2F_INSN_PAR_UNLOCK, M32R2F_INSN_WRITE_UNLOCK, M32R2F_INSN_PAR_PCMPBZ
, M32R2F_INSN_WRITE_PCMPBZ, M32R2F_INSN_PAR_SADD, M32R2F_INSN_WRITE_SADD, M32R2F_INSN_PAR_MACWU1
, M32R2F_INSN_WRITE_MACWU1, M32R2F_INSN_PAR_MSBLO, M32R2F_INSN_WRITE_MSBLO, M32R2F_INSN_PAR_MULWU1
, M32R2F_INSN_WRITE_MULWU1, M32R2F_INSN_PAR_MACLH1, M32R2F_INSN_WRITE_MACLH1, M32R2F_INSN_PAR_SC
, M32R2F_INSN_WRITE_SC, M32R2F_INSN_PAR_SNC, M32R2F_INSN_WRITE_SNC, M32R2F_INSN_PAR_CLRPSW
, M32R2F_INSN_WRITE_CLRPSW, M32R2F_INSN_PAR_SETPSW, M32R2F_INSN_WRITE_SETPSW, M32R2F_INSN_PAR_BTST
, M32R2F_INSN_WRITE_BTST, M32R2F_INSN__MAX
} M32R2F_INSN_TYPE;
/* Enum declaration for semantic formats in cpu family m32r2f. */
typedef enum m32r2f_sfmt_type {
M32R2F_SFMT_EMPTY, M32R2F_SFMT_ADD, M32R2F_SFMT_ADD3, M32R2F_SFMT_AND3
, M32R2F_SFMT_OR3, M32R2F_SFMT_ADDI, M32R2F_SFMT_ADDV, M32R2F_SFMT_ADDV3
, M32R2F_SFMT_ADDX, M32R2F_SFMT_BC8, M32R2F_SFMT_BC24, M32R2F_SFMT_BEQ
, M32R2F_SFMT_BEQZ, M32R2F_SFMT_BL8, M32R2F_SFMT_BL24, M32R2F_SFMT_BCL8
, M32R2F_SFMT_BCL24, M32R2F_SFMT_BRA8, M32R2F_SFMT_BRA24, M32R2F_SFMT_CMP
, M32R2F_SFMT_CMPI, M32R2F_SFMT_CMPZ, M32R2F_SFMT_DIV, M32R2F_SFMT_JC
, M32R2F_SFMT_JL, M32R2F_SFMT_JMP, M32R2F_SFMT_LD, M32R2F_SFMT_LD_D
, M32R2F_SFMT_LDB, M32R2F_SFMT_LDB_D, M32R2F_SFMT_LDH, M32R2F_SFMT_LDH_D
, M32R2F_SFMT_LD_PLUS, M32R2F_SFMT_LD24, M32R2F_SFMT_LDI8, M32R2F_SFMT_LDI16
, M32R2F_SFMT_LOCK, M32R2F_SFMT_MACHI_A, M32R2F_SFMT_MULHI_A, M32R2F_SFMT_MV
, M32R2F_SFMT_MVFACHI_A, M32R2F_SFMT_MVFC, M32R2F_SFMT_MVTACHI_A, M32R2F_SFMT_MVTC
, M32R2F_SFMT_NOP, M32R2F_SFMT_RAC_DSI, M32R2F_SFMT_RTE, M32R2F_SFMT_SETH
, M32R2F_SFMT_SLL3, M32R2F_SFMT_SLLI, M32R2F_SFMT_ST, M32R2F_SFMT_ST_D
, M32R2F_SFMT_STB, M32R2F_SFMT_STB_D, M32R2F_SFMT_STH, M32R2F_SFMT_STH_D
, M32R2F_SFMT_ST_PLUS, M32R2F_SFMT_STH_PLUS, M32R2F_SFMT_STB_PLUS, M32R2F_SFMT_TRAP
, M32R2F_SFMT_UNLOCK, M32R2F_SFMT_SATB, M32R2F_SFMT_SAT, M32R2F_SFMT_SADD
, M32R2F_SFMT_MACWU1, M32R2F_SFMT_MSBLO, M32R2F_SFMT_MULWU1, M32R2F_SFMT_SC
, M32R2F_SFMT_CLRPSW, M32R2F_SFMT_SETPSW, M32R2F_SFMT_BSET, M32R2F_SFMT_BTST
} M32R2F_SFMT_TYPE;
/* Function unit handlers (user written). */
extern int m32r2f_model_m32r2_u_store (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*src1*/, INT /*src2*/);
extern int m32r2f_model_m32r2_u_load (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*sr*/, INT /*dr*/);
extern int m32r2f_model_m32r2_u_cti (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*sr*/);
extern int m32r2f_model_m32r2_u_mac (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*src1*/, INT /*src2*/);
extern int m32r2f_model_m32r2_u_cmp (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*src1*/, INT /*src2*/);
extern int m32r2f_model_m32r2_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*sr*/, INT /*dr*/, INT /*dr*/);
/* Profiling before/after handlers (user written) */
extern void m32r2f_model_insn_before (SIM_CPU *, int /*first_p*/);
extern void m32r2f_model_insn_after (SIM_CPU *, int /*last_p*/, int /*cycles*/);
#endif /* M32R2F_DECODE_H */

189
sim/m32r/decodex.c
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -152,6 +152,8 @@ static const struct insn_sem m32rxf_insn_sem[] =
{ M32R_INSN_STH, M32RXF_INSN_STH, M32RXF_SFMT_STH, M32RXF_INSN_PAR_STH, M32RXF_INSN_WRITE_STH },
{ M32R_INSN_STH_D, M32RXF_INSN_STH_D, M32RXF_SFMT_STH_D, NOPAR, NOPAR },
{ M32R_INSN_ST_PLUS, M32RXF_INSN_ST_PLUS, M32RXF_SFMT_ST_PLUS, M32RXF_INSN_PAR_ST_PLUS, M32RXF_INSN_WRITE_ST_PLUS },
{ M32R_INSN_STH_PLUS, M32RXF_INSN_STH_PLUS, M32RXF_SFMT_STH_PLUS, M32RXF_INSN_PAR_STH_PLUS, M32RXF_INSN_WRITE_STH_PLUS },
{ M32R_INSN_STB_PLUS, M32RXF_INSN_STB_PLUS, M32RXF_SFMT_STB_PLUS, M32RXF_INSN_PAR_STB_PLUS, M32RXF_INSN_WRITE_STB_PLUS },
{ M32R_INSN_ST_MINUS, M32RXF_INSN_ST_MINUS, M32RXF_SFMT_ST_PLUS, M32RXF_INSN_PAR_ST_MINUS, M32RXF_INSN_WRITE_ST_MINUS },
{ M32R_INSN_SUB, M32RXF_INSN_SUB, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_SUB, M32RXF_INSN_WRITE_SUB },
{ M32R_INSN_SUBV, M32RXF_INSN_SUBV, M32RXF_SFMT_ADDV, M32RXF_INSN_PAR_SUBV, M32RXF_INSN_WRITE_SUBV },
@ -169,6 +171,11 @@ static const struct insn_sem m32rxf_insn_sem[] =
{ M32R_INSN_MACLH1, M32RXF_INSN_MACLH1, M32RXF_SFMT_MACWU1, M32RXF_INSN_PAR_MACLH1, M32RXF_INSN_WRITE_MACLH1 },
{ M32R_INSN_SC, M32RXF_INSN_SC, M32RXF_SFMT_SC, M32RXF_INSN_PAR_SC, M32RXF_INSN_WRITE_SC },
{ M32R_INSN_SNC, M32RXF_INSN_SNC, M32RXF_SFMT_SC, M32RXF_INSN_PAR_SNC, M32RXF_INSN_WRITE_SNC },
{ M32R_INSN_CLRPSW, M32RXF_INSN_CLRPSW, M32RXF_SFMT_CLRPSW, M32RXF_INSN_PAR_CLRPSW, M32RXF_INSN_WRITE_CLRPSW },
{ M32R_INSN_SETPSW, M32RXF_INSN_SETPSW, M32RXF_SFMT_SETPSW, M32RXF_INSN_PAR_SETPSW, M32RXF_INSN_WRITE_SETPSW },
{ M32R_INSN_BSET, M32RXF_INSN_BSET, M32RXF_SFMT_BSET, NOPAR, NOPAR },
{ M32R_INSN_BCLR, M32RXF_INSN_BCLR, M32RXF_SFMT_BSET, NOPAR, NOPAR },
{ M32R_INSN_BTST, M32RXF_INSN_BTST, M32RXF_SFMT_BTST, M32RXF_INSN_PAR_BTST, M32RXF_INSN_WRITE_BTST },
};
static const struct insn_sem m32rxf_insn_sem_invalid = {
@ -282,6 +289,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
case 12 : itype = M32RXF_INSN_AND; goto extract_sfmt_add;
case 13 : itype = M32RXF_INSN_XOR; goto extract_sfmt_add;
case 14 : itype = M32RXF_INSN_OR; goto extract_sfmt_add;
case 15 : itype = M32RXF_INSN_BTST; goto extract_sfmt_btst;
case 16 : itype = M32RXF_INSN_SRL; goto extract_sfmt_add;
case 18 : itype = M32RXF_INSN_SRA; goto extract_sfmt_add;
case 20 : itype = M32RXF_INSN_SLL; goto extract_sfmt_add;
@ -304,7 +312,9 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
case 29 : itype = M32RXF_INSN_RTE; goto extract_sfmt_rte;
case 31 : itype = M32RXF_INSN_TRAP; goto extract_sfmt_trap;
case 32 : itype = M32RXF_INSN_STB; goto extract_sfmt_stb;
case 33 : itype = M32RXF_INSN_STB_PLUS; goto extract_sfmt_stb_plus;
case 34 : itype = M32RXF_INSN_STH; goto extract_sfmt_sth;
case 35 : itype = M32RXF_INSN_STH_PLUS; goto extract_sfmt_sth_plus;
case 36 : itype = M32RXF_INSN_ST; goto extract_sfmt_st;
case 37 : itype = M32RXF_INSN_UNLOCK; goto extract_sfmt_unlock;
case 38 : itype = M32RXF_INSN_ST_PLUS; goto extract_sfmt_st_plus;
@ -404,6 +414,10 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
switch (val)
{
case 0 : itype = M32RXF_INSN_NOP; goto extract_sfmt_nop;
case 2 : /* fall through */
case 3 : itype = M32RXF_INSN_SETPSW; goto extract_sfmt_setpsw;
case 4 : /* fall through */
case 5 : itype = M32RXF_INSN_CLRPSW; goto extract_sfmt_clrpsw;
case 9 : itype = M32RXF_INSN_SC; goto extract_sfmt_sc;
case 11 : itype = M32RXF_INSN_SNC; goto extract_sfmt_sc;
case 16 : /* fall through */
@ -437,15 +451,17 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
case 126 : /* fall through */
case 127 :
{
unsigned int val = (((insn >> 8) & (7 << 0)));
unsigned int val = (((insn >> 8) & (15 << 0)));
switch (val)
{
case 0 : itype = M32RXF_INSN_BCL8; goto extract_sfmt_bcl8;
case 1 : itype = M32RXF_INSN_BNCL8; goto extract_sfmt_bcl8;
case 4 : itype = M32RXF_INSN_BC8; goto extract_sfmt_bc8;
case 5 : itype = M32RXF_INSN_BNC8; goto extract_sfmt_bc8;
case 6 : itype = M32RXF_INSN_BL8; goto extract_sfmt_bl8;
case 7 : itype = M32RXF_INSN_BRA8; goto extract_sfmt_bra8;
case 1 : itype = M32RXF_INSN_SETPSW; goto extract_sfmt_setpsw;
case 2 : itype = M32RXF_INSN_CLRPSW; goto extract_sfmt_clrpsw;
case 8 : itype = M32RXF_INSN_BCL8; goto extract_sfmt_bcl8;
case 9 : itype = M32RXF_INSN_BNCL8; goto extract_sfmt_bcl8;
case 12 : itype = M32RXF_INSN_BC8; goto extract_sfmt_bc8;
case 13 : itype = M32RXF_INSN_BNC8; goto extract_sfmt_bc8;
case 14 : itype = M32RXF_INSN_BL8; goto extract_sfmt_bl8;
case 15 : itype = M32RXF_INSN_BRA8; goto extract_sfmt_bra8;
default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
}
}
@ -487,6 +503,8 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
case 160 : itype = M32RXF_INSN_STB_D; goto extract_sfmt_stb_d;
case 162 : itype = M32RXF_INSN_STH_D; goto extract_sfmt_sth_d;
case 164 : itype = M32RXF_INSN_ST_D; goto extract_sfmt_st_d;
case 166 : itype = M32RXF_INSN_BSET; goto extract_sfmt_bset;
case 167 : itype = M32RXF_INSN_BCLR; goto extract_sfmt_bset;
case 168 : itype = M32RXF_INSN_LDB_D; goto extract_sfmt_ldb_d;
case 169 : itype = M32RXF_INSN_LDUB_D; goto extract_sfmt_ldb_d;
case 170 : itype = M32RXF_INSN_LDH_D; goto extract_sfmt_ldh_d;
@ -2153,6 +2171,68 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
FLD (i_src2) = & CPU (h_gr)[f_r2];
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st_plus", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
#if WITH_PROFILE_MODEL_P
/* Record the fields for profiling. */
if (PROFILE_MODEL_P (current_cpu))
{
FLD (in_src1) = f_r1;
FLD (in_src2) = f_r2;
FLD (out_src2) = f_r2;
}
#endif
#undef FLD
return idesc;
}
extract_sfmt_sth_plus:
{
const IDESC *idesc = &m32rxf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_st_plus.f
UINT f_r1;
UINT f_r2;
f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
/* Record the fields for the semantic handler. */
FLD (f_r1) = f_r1;
FLD (f_r2) = f_r2;
FLD (i_src1) = & CPU (h_gr)[f_r1];
FLD (i_src2) = & CPU (h_gr)[f_r2];
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sth_plus", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
#if WITH_PROFILE_MODEL_P
/* Record the fields for profiling. */
if (PROFILE_MODEL_P (current_cpu))
{
FLD (in_src1) = f_r1;
FLD (in_src2) = f_r2;
FLD (out_src2) = f_r2;
}
#endif
#undef FLD
return idesc;
}
extract_sfmt_stb_plus:
{
const IDESC *idesc = &m32rxf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_st_plus.f
UINT f_r1;
UINT f_r2;
f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
/* Record the fields for the semantic handler. */
FLD (f_r1) = f_r1;
FLD (f_r2) = f_r2;
FLD (i_src1) = & CPU (h_gr)[f_r1];
FLD (i_src2) = & CPU (h_gr)[f_r2];
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb_plus", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
#if WITH_PROFILE_MODEL_P
/* Record the fields for profiling. */
if (PROFILE_MODEL_P (current_cpu))
@ -2391,6 +2471,99 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
/* Record the fields for the semantic handler. */
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sc", (char *) 0));
#undef FLD
return idesc;
}
extract_sfmt_clrpsw:
{
const IDESC *idesc = &m32rxf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_clrpsw.f
UINT f_uimm8;
f_uimm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8);
/* Record the fields for the semantic handler. */
FLD (f_uimm8) = f_uimm8;
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_clrpsw", "f_uimm8 0x%x", 'x', f_uimm8, (char *) 0));
#undef FLD
return idesc;
}
extract_sfmt_setpsw:
{
const IDESC *idesc = &m32rxf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_clrpsw.f
UINT f_uimm8;
f_uimm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8);
/* Record the fields for the semantic handler. */
FLD (f_uimm8) = f_uimm8;
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_setpsw", "f_uimm8 0x%x", 'x', f_uimm8, (char *) 0));
#undef FLD
return idesc;
}
extract_sfmt_bset:
{
const IDESC *idesc = &m32rxf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_bset.f
UINT f_uimm3;
UINT f_r2;
INT f_simm16;
f_uimm3 = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
/* Record the fields for the semantic handler. */
FLD (f_simm16) = f_simm16;
FLD (f_r2) = f_r2;
FLD (f_uimm3) = f_uimm3;
FLD (i_sr) = & CPU (h_gr)[f_r2];
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bset", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_uimm3 0x%x", 'x', f_uimm3, "sr 0x%x", 'x', f_r2, (char *) 0));
#if WITH_PROFILE_MODEL_P
/* Record the fields for profiling. */
if (PROFILE_MODEL_P (current_cpu))
{
FLD (in_sr) = f_r2;
}
#endif
#undef FLD
return idesc;
}
extract_sfmt_btst:
{
const IDESC *idesc = &m32rxf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_bset.f
UINT f_uimm3;
UINT f_r2;
f_uimm3 = EXTRACT_MSB0_UINT (insn, 16, 5, 3);
f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
/* Record the fields for the semantic handler. */
FLD (f_r2) = f_r2;
FLD (f_uimm3) = f_uimm3;
FLD (i_sr) = & CPU (h_gr)[f_r2];
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_btst", "f_r2 0x%x", 'x', f_r2, "f_uimm3 0x%x", 'x', f_uimm3, "sr 0x%x", 'x', f_r2, (char *) 0));
#if WITH_PROFILE_MODEL_P
/* Record the fields for profiling. */
if (PROFILE_MODEL_P (current_cpu))
{
FLD (in_sr) = f_r2;
}
#endif
#undef FLD
return idesc;
}

99
sim/m32r/decodex.h
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -61,49 +61,53 @@ typedef enum m32rxf_insn_type {
, M32RXF_INSN_SRA3, M32RXF_INSN_SRAI, M32RXF_INSN_SRL, M32RXF_INSN_SRL3
, M32RXF_INSN_SRLI, M32RXF_INSN_ST, M32RXF_INSN_ST_D, M32RXF_INSN_STB
, M32RXF_INSN_STB_D, M32RXF_INSN_STH, M32RXF_INSN_STH_D, M32RXF_INSN_ST_PLUS
, M32RXF_INSN_ST_MINUS, M32RXF_INSN_SUB, M32RXF_INSN_SUBV, M32RXF_INSN_SUBX
, M32RXF_INSN_TRAP, M32RXF_INSN_UNLOCK, M32RXF_INSN_SATB, M32RXF_INSN_SATH
, M32RXF_INSN_SAT, M32RXF_INSN_PCMPBZ, M32RXF_INSN_SADD, M32RXF_INSN_MACWU1
, M32RXF_INSN_MSBLO, M32RXF_INSN_MULWU1, M32RXF_INSN_MACLH1, M32RXF_INSN_SC
, M32RXF_INSN_SNC, M32RXF_INSN_PAR_ADD, M32RXF_INSN_WRITE_ADD, M32RXF_INSN_PAR_AND
, M32RXF_INSN_WRITE_AND, M32RXF_INSN_PAR_OR, M32RXF_INSN_WRITE_OR, M32RXF_INSN_PAR_XOR
, M32RXF_INSN_WRITE_XOR, M32RXF_INSN_PAR_ADDI, M32RXF_INSN_WRITE_ADDI, M32RXF_INSN_PAR_ADDV
, M32RXF_INSN_WRITE_ADDV, M32RXF_INSN_PAR_ADDX, M32RXF_INSN_WRITE_ADDX, M32RXF_INSN_PAR_BC8
, M32RXF_INSN_WRITE_BC8, M32RXF_INSN_PAR_BL8, M32RXF_INSN_WRITE_BL8, M32RXF_INSN_PAR_BCL8
, M32RXF_INSN_WRITE_BCL8, M32RXF_INSN_PAR_BNC8, M32RXF_INSN_WRITE_BNC8, M32RXF_INSN_PAR_BRA8
, M32RXF_INSN_WRITE_BRA8, M32RXF_INSN_PAR_BNCL8, M32RXF_INSN_WRITE_BNCL8, M32RXF_INSN_PAR_CMP
, M32RXF_INSN_WRITE_CMP, M32RXF_INSN_PAR_CMPU, M32RXF_INSN_WRITE_CMPU, M32RXF_INSN_PAR_CMPEQ
, M32RXF_INSN_WRITE_CMPEQ, M32RXF_INSN_PAR_CMPZ, M32RXF_INSN_WRITE_CMPZ, M32RXF_INSN_PAR_JC
, M32RXF_INSN_WRITE_JC, M32RXF_INSN_PAR_JNC, M32RXF_INSN_WRITE_JNC, M32RXF_INSN_PAR_JL
, M32RXF_INSN_WRITE_JL, M32RXF_INSN_PAR_JMP, M32RXF_INSN_WRITE_JMP, M32RXF_INSN_PAR_LD
, M32RXF_INSN_WRITE_LD, M32RXF_INSN_PAR_LDB, M32RXF_INSN_WRITE_LDB, M32RXF_INSN_PAR_LDH
, M32RXF_INSN_WRITE_LDH, M32RXF_INSN_PAR_LDUB, M32RXF_INSN_WRITE_LDUB, M32RXF_INSN_PAR_LDUH
, M32RXF_INSN_WRITE_LDUH, M32RXF_INSN_PAR_LD_PLUS, M32RXF_INSN_WRITE_LD_PLUS, M32RXF_INSN_PAR_LDI8
, M32RXF_INSN_WRITE_LDI8, M32RXF_INSN_PAR_LOCK, M32RXF_INSN_WRITE_LOCK, M32RXF_INSN_PAR_MACHI_A
, M32RXF_INSN_WRITE_MACHI_A, M32RXF_INSN_PAR_MACLO_A, M32RXF_INSN_WRITE_MACLO_A, M32RXF_INSN_PAR_MACWHI_A
, M32RXF_INSN_WRITE_MACWHI_A, M32RXF_INSN_PAR_MACWLO_A, M32RXF_INSN_WRITE_MACWLO_A, M32RXF_INSN_PAR_MUL
, M32RXF_INSN_WRITE_MUL, M32RXF_INSN_PAR_MULHI_A, M32RXF_INSN_WRITE_MULHI_A, M32RXF_INSN_PAR_MULLO_A
, M32RXF_INSN_WRITE_MULLO_A, M32RXF_INSN_PAR_MULWHI_A, M32RXF_INSN_WRITE_MULWHI_A, M32RXF_INSN_PAR_MULWLO_A
, M32RXF_INSN_WRITE_MULWLO_A, M32RXF_INSN_PAR_MV, M32RXF_INSN_WRITE_MV, M32RXF_INSN_PAR_MVFACHI_A
, M32RXF_INSN_WRITE_MVFACHI_A, M32RXF_INSN_PAR_MVFACLO_A, M32RXF_INSN_WRITE_MVFACLO_A, M32RXF_INSN_PAR_MVFACMI_A
, M32RXF_INSN_WRITE_MVFACMI_A, M32RXF_INSN_PAR_MVFC, M32RXF_INSN_WRITE_MVFC, M32RXF_INSN_PAR_MVTACHI_A
, M32RXF_INSN_WRITE_MVTACHI_A, M32RXF_INSN_PAR_MVTACLO_A, M32RXF_INSN_WRITE_MVTACLO_A, M32RXF_INSN_PAR_MVTC
, M32RXF_INSN_WRITE_MVTC, M32RXF_INSN_PAR_NEG, M32RXF_INSN_WRITE_NEG, M32RXF_INSN_PAR_NOP
, M32RXF_INSN_WRITE_NOP, M32RXF_INSN_PAR_NOT, M32RXF_INSN_WRITE_NOT, M32RXF_INSN_PAR_RAC_DSI
, M32RXF_INSN_WRITE_RAC_DSI, M32RXF_INSN_PAR_RACH_DSI, M32RXF_INSN_WRITE_RACH_DSI, M32RXF_INSN_PAR_RTE
, M32RXF_INSN_WRITE_RTE, M32RXF_INSN_PAR_SLL, M32RXF_INSN_WRITE_SLL, M32RXF_INSN_PAR_SLLI
, M32RXF_INSN_WRITE_SLLI, M32RXF_INSN_PAR_SRA, M32RXF_INSN_WRITE_SRA, M32RXF_INSN_PAR_SRAI
, M32RXF_INSN_WRITE_SRAI, M32RXF_INSN_PAR_SRL, M32RXF_INSN_WRITE_SRL, M32RXF_INSN_PAR_SRLI
, M32RXF_INSN_WRITE_SRLI, M32RXF_INSN_PAR_ST, M32RXF_INSN_WRITE_ST, M32RXF_INSN_PAR_STB
, M32RXF_INSN_WRITE_STB, M32RXF_INSN_PAR_STH, M32RXF_INSN_WRITE_STH, M32RXF_INSN_PAR_ST_PLUS
, M32RXF_INSN_WRITE_ST_PLUS, M32RXF_INSN_PAR_ST_MINUS, M32RXF_INSN_WRITE_ST_MINUS, M32RXF_INSN_PAR_SUB
, M32RXF_INSN_WRITE_SUB, M32RXF_INSN_PAR_SUBV, M32RXF_INSN_WRITE_SUBV, M32RXF_INSN_PAR_SUBX
, M32RXF_INSN_WRITE_SUBX, M32RXF_INSN_PAR_TRAP, M32RXF_INSN_WRITE_TRAP, M32RXF_INSN_PAR_UNLOCK
, M32RXF_INSN_WRITE_UNLOCK, M32RXF_INSN_PAR_PCMPBZ, M32RXF_INSN_WRITE_PCMPBZ, M32RXF_INSN_PAR_SADD
, M32RXF_INSN_WRITE_SADD, M32RXF_INSN_PAR_MACWU1, M32RXF_INSN_WRITE_MACWU1, M32RXF_INSN_PAR_MSBLO
, M32RXF_INSN_WRITE_MSBLO, M32RXF_INSN_PAR_MULWU1, M32RXF_INSN_WRITE_MULWU1, M32RXF_INSN_PAR_MACLH1
, M32RXF_INSN_WRITE_MACLH1, M32RXF_INSN_PAR_SC, M32RXF_INSN_WRITE_SC, M32RXF_INSN_PAR_SNC
, M32RXF_INSN_WRITE_SNC, M32RXF_INSN__MAX
, M32RXF_INSN_STH_PLUS, M32RXF_INSN_STB_PLUS, M32RXF_INSN_ST_MINUS, M32RXF_INSN_SUB
, M32RXF_INSN_SUBV, M32RXF_INSN_SUBX, M32RXF_INSN_TRAP, M32RXF_INSN_UNLOCK
, M32RXF_INSN_SATB, M32RXF_INSN_SATH, M32RXF_INSN_SAT, M32RXF_INSN_PCMPBZ
, M32RXF_INSN_SADD, M32RXF_INSN_MACWU1, M32RXF_INSN_MSBLO, M32RXF_INSN_MULWU1
, M32RXF_INSN_MACLH1, M32RXF_INSN_SC, M32RXF_INSN_SNC, M32RXF_INSN_CLRPSW
, M32RXF_INSN_SETPSW, M32RXF_INSN_BSET, M32RXF_INSN_BCLR, M32RXF_INSN_BTST
, M32RXF_INSN_PAR_ADD, M32RXF_INSN_WRITE_ADD, M32RXF_INSN_PAR_AND, M32RXF_INSN_WRITE_AND
, M32RXF_INSN_PAR_OR, M32RXF_INSN_WRITE_OR, M32RXF_INSN_PAR_XOR, M32RXF_INSN_WRITE_XOR
, M32RXF_INSN_PAR_ADDI, M32RXF_INSN_WRITE_ADDI, M32RXF_INSN_PAR_ADDV, M32RXF_INSN_WRITE_ADDV
, M32RXF_INSN_PAR_ADDX, M32RXF_INSN_WRITE_ADDX, M32RXF_INSN_PAR_BC8, M32RXF_INSN_WRITE_BC8
, M32RXF_INSN_PAR_BL8, M32RXF_INSN_WRITE_BL8, M32RXF_INSN_PAR_BCL8, M32RXF_INSN_WRITE_BCL8
, M32RXF_INSN_PAR_BNC8, M32RXF_INSN_WRITE_BNC8, M32RXF_INSN_PAR_BRA8, M32RXF_INSN_WRITE_BRA8
, M32RXF_INSN_PAR_BNCL8, M32RXF_INSN_WRITE_BNCL8, M32RXF_INSN_PAR_CMP, M32RXF_INSN_WRITE_CMP
, M32RXF_INSN_PAR_CMPU, M32RXF_INSN_WRITE_CMPU, M32RXF_INSN_PAR_CMPEQ, M32RXF_INSN_WRITE_CMPEQ
, M32RXF_INSN_PAR_CMPZ, M32RXF_INSN_WRITE_CMPZ, M32RXF_INSN_PAR_JC, M32RXF_INSN_WRITE_JC
, M32RXF_INSN_PAR_JNC, M32RXF_INSN_WRITE_JNC, M32RXF_INSN_PAR_JL, M32RXF_INSN_WRITE_JL
, M32RXF_INSN_PAR_JMP, M32RXF_INSN_WRITE_JMP, M32RXF_INSN_PAR_LD, M32RXF_INSN_WRITE_LD
, M32RXF_INSN_PAR_LDB, M32RXF_INSN_WRITE_LDB, M32RXF_INSN_PAR_LDH, M32RXF_INSN_WRITE_LDH
, M32RXF_INSN_PAR_LDUB, M32RXF_INSN_WRITE_LDUB, M32RXF_INSN_PAR_LDUH, M32RXF_INSN_WRITE_LDUH
, M32RXF_INSN_PAR_LD_PLUS, M32RXF_INSN_WRITE_LD_PLUS, M32RXF_INSN_PAR_LDI8, M32RXF_INSN_WRITE_LDI8
, M32RXF_INSN_PAR_LOCK, M32RXF_INSN_WRITE_LOCK, M32RXF_INSN_PAR_MACHI_A, M32RXF_INSN_WRITE_MACHI_A
, M32RXF_INSN_PAR_MACLO_A, M32RXF_INSN_WRITE_MACLO_A, M32RXF_INSN_PAR_MACWHI_A, M32RXF_INSN_WRITE_MACWHI_A
, M32RXF_INSN_PAR_MACWLO_A, M32RXF_INSN_WRITE_MACWLO_A, M32RXF_INSN_PAR_MUL, M32RXF_INSN_WRITE_MUL
, M32RXF_INSN_PAR_MULHI_A, M32RXF_INSN_WRITE_MULHI_A, M32RXF_INSN_PAR_MULLO_A, M32RXF_INSN_WRITE_MULLO_A
, M32RXF_INSN_PAR_MULWHI_A, M32RXF_INSN_WRITE_MULWHI_A, M32RXF_INSN_PAR_MULWLO_A, M32RXF_INSN_WRITE_MULWLO_A
, M32RXF_INSN_PAR_MV, M32RXF_INSN_WRITE_MV, M32RXF_INSN_PAR_MVFACHI_A, M32RXF_INSN_WRITE_MVFACHI_A
, M32RXF_INSN_PAR_MVFACLO_A, M32RXF_INSN_WRITE_MVFACLO_A, M32RXF_INSN_PAR_MVFACMI_A, M32RXF_INSN_WRITE_MVFACMI_A
, M32RXF_INSN_PAR_MVFC, M32RXF_INSN_WRITE_MVFC, M32RXF_INSN_PAR_MVTACHI_A, M32RXF_INSN_WRITE_MVTACHI_A
, M32RXF_INSN_PAR_MVTACLO_A, M32RXF_INSN_WRITE_MVTACLO_A, M32RXF_INSN_PAR_MVTC, M32RXF_INSN_WRITE_MVTC
, M32RXF_INSN_PAR_NEG, M32RXF_INSN_WRITE_NEG, M32RXF_INSN_PAR_NOP, M32RXF_INSN_WRITE_NOP
, M32RXF_INSN_PAR_NOT, M32RXF_INSN_WRITE_NOT, M32RXF_INSN_PAR_RAC_DSI, M32RXF_INSN_WRITE_RAC_DSI
, M32RXF_INSN_PAR_RACH_DSI, M32RXF_INSN_WRITE_RACH_DSI, M32RXF_INSN_PAR_RTE, M32RXF_INSN_WRITE_RTE
, M32RXF_INSN_PAR_SLL, M32RXF_INSN_WRITE_SLL, M32RXF_INSN_PAR_SLLI, M32RXF_INSN_WRITE_SLLI
, M32RXF_INSN_PAR_SRA, M32RXF_INSN_WRITE_SRA, M32RXF_INSN_PAR_SRAI, M32RXF_INSN_WRITE_SRAI
, M32RXF_INSN_PAR_SRL, M32RXF_INSN_WRITE_SRL, M32RXF_INSN_PAR_SRLI, M32RXF_INSN_WRITE_SRLI
, M32RXF_INSN_PAR_ST, M32RXF_INSN_WRITE_ST, M32RXF_INSN_PAR_STB, M32RXF_INSN_WRITE_STB
, M32RXF_INSN_PAR_STH, M32RXF_INSN_WRITE_STH, M32RXF_INSN_PAR_ST_PLUS, M32RXF_INSN_WRITE_ST_PLUS
, M32RXF_INSN_PAR_STH_PLUS, M32RXF_INSN_WRITE_STH_PLUS, M32RXF_INSN_PAR_STB_PLUS, M32RXF_INSN_WRITE_STB_PLUS
, M32RXF_INSN_PAR_ST_MINUS, M32RXF_INSN_WRITE_ST_MINUS, M32RXF_INSN_PAR_SUB, M32RXF_INSN_WRITE_SUB
, M32RXF_INSN_PAR_SUBV, M32RXF_INSN_WRITE_SUBV, M32RXF_INSN_PAR_SUBX, M32RXF_INSN_WRITE_SUBX
, M32RXF_INSN_PAR_TRAP, M32RXF_INSN_WRITE_TRAP, M32RXF_INSN_PAR_UNLOCK, M32RXF_INSN_WRITE_UNLOCK
, M32RXF_INSN_PAR_PCMPBZ, M32RXF_INSN_WRITE_PCMPBZ, M32RXF_INSN_PAR_SADD, M32RXF_INSN_WRITE_SADD
, M32RXF_INSN_PAR_MACWU1, M32RXF_INSN_WRITE_MACWU1, M32RXF_INSN_PAR_MSBLO, M32RXF_INSN_WRITE_MSBLO
, M32RXF_INSN_PAR_MULWU1, M32RXF_INSN_WRITE_MULWU1, M32RXF_INSN_PAR_MACLH1, M32RXF_INSN_WRITE_MACLH1
, M32RXF_INSN_PAR_SC, M32RXF_INSN_WRITE_SC, M32RXF_INSN_PAR_SNC, M32RXF_INSN_WRITE_SNC
, M32RXF_INSN_PAR_CLRPSW, M32RXF_INSN_WRITE_CLRPSW, M32RXF_INSN_PAR_SETPSW, M32RXF_INSN_WRITE_SETPSW
, M32RXF_INSN_PAR_BTST, M32RXF_INSN_WRITE_BTST, M32RXF_INSN__MAX
} M32RXF_INSN_TYPE;
/* Enum declaration for semantic formats in cpu family m32rxf. */
@ -122,9 +126,10 @@ typedef enum m32rxf_sfmt_type {
, M32RXF_SFMT_NOP, M32RXF_SFMT_RAC_DSI, M32RXF_SFMT_RTE, M32RXF_SFMT_SETH
, M32RXF_SFMT_SLL3, M32RXF_SFMT_SLLI, M32RXF_SFMT_ST, M32RXF_SFMT_ST_D
, M32RXF_SFMT_STB, M32RXF_SFMT_STB_D, M32RXF_SFMT_STH, M32RXF_SFMT_STH_D
, M32RXF_SFMT_ST_PLUS, M32RXF_SFMT_TRAP, M32RXF_SFMT_UNLOCK, M32RXF_SFMT_SATB
, M32RXF_SFMT_SAT, M32RXF_SFMT_SADD, M32RXF_SFMT_MACWU1, M32RXF_SFMT_MSBLO
, M32RXF_SFMT_MULWU1, M32RXF_SFMT_SC
, M32RXF_SFMT_ST_PLUS, M32RXF_SFMT_STH_PLUS, M32RXF_SFMT_STB_PLUS, M32RXF_SFMT_TRAP
, M32RXF_SFMT_UNLOCK, M32RXF_SFMT_SATB, M32RXF_SFMT_SAT, M32RXF_SFMT_SADD
, M32RXF_SFMT_MACWU1, M32RXF_SFMT_MSBLO, M32RXF_SFMT_MULWU1, M32RXF_SFMT_SC
, M32RXF_SFMT_CLRPSW, M32RXF_SFMT_SETPSW, M32RXF_SFMT_BSET, M32RXF_SFMT_BTST
} M32RXF_SFMT_TYPE;
/* Function unit handlers (user written). */

45
sim/m32r/m32r-sim.h
View File

@ -1,27 +1,27 @@
/* collection of junk waiting time to sort out
Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
Copyright (C) 1996, 1997, 1998, 2003 Free Software Foundation, Inc.
Contributed by Cygnus Support.
This file is part of the GNU Simulators.
This file is part of GDB, the GNU debugger.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#ifndef M32R_SIM_H
#define M32R_SIM_H
/* gdb register numbers */
/* GDB register numbers. */
#define PSW_REGNUM 16
#define CBR_REGNUM 17
#define SPI_REGNUM 18
@ -34,6 +34,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
#define ACC1H_REGNUM 25
#define BBPSW_REGNUM 26
#define BBPC_REGNUM 27
#define EVB_REGNUM 28
extern int m32r_decode_gdb_ctrl_regnum (int);
@ -41,27 +42,35 @@ extern int m32r_decode_gdb_ctrl_regnum (int);
FIXME: Eventually move to cgen. */
#define GET_H_SM() ((CPU (h_psw) & 0x80) != 0)
extern USI m32rbf_h_cr_get_handler (SIM_CPU *, UINT);
#ifndef GET_H_CR
extern USI m32rbf_h_cr_get_handler (SIM_CPU *, UINT);
extern void m32rbf_h_cr_set_handler (SIM_CPU *, UINT, USI);
#define GET_H_CR(regno) \
XCONCAT2 (WANT_CPU,_h_cr_get_handler) (current_cpu, (regno))
#define SET_H_CR(regno, val) \
XCONCAT2 (WANT_CPU,_h_cr_set_handler) (current_cpu, (regno), (val))
#endif
extern UQI m32rbf_h_psw_get_handler (SIM_CPU *);
#ifndef GET_H_PSW
extern UQI m32rbf_h_psw_get_handler (SIM_CPU *);
extern void m32rbf_h_psw_set_handler (SIM_CPU *, UQI);
#define GET_H_PSW() \
XCONCAT2 (WANT_CPU,_h_psw_get_handler) (current_cpu)
#define SET_H_PSW(val) \
XCONCAT2 (WANT_CPU,_h_psw_set_handler) (current_cpu, (val))
#endif
extern DI m32rbf_h_accum_get_handler (SIM_CPU *);
#ifndef GET_H_ACCUM
extern DI m32rbf_h_accum_get_handler (SIM_CPU *);
extern void m32rbf_h_accum_set_handler (SIM_CPU *, DI);
#define GET_H_ACCUM() \
XCONCAT2 (WANT_CPU,_h_accum_get_handler) (current_cpu)
#define SET_H_ACCUM(val) \
XCONCAT2 (WANT_CPU,_h_accum_set_handler) (current_cpu, (val))
#endif
/* Misc. profile data. */

51
sim/m32r/m32r.c
View File

@ -1,22 +1,22 @@
/* m32r simulator support code
Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
Copyright (C) 1996, 1997, 1998, 2003 Free Software Foundation, Inc.
Contributed by Cygnus Support.
This file is part of GDB, the GNU debugger.
This file is part of GDB, the GNU debugger.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#define WANT_CPU m32rbf
#define WANT_CPU_M32RBF
@ -39,6 +39,7 @@ m32r_decode_gdb_ctrl_regnum (int gdb_regnum)
case BPC_REGNUM : return H_CR_BPC;
case BBPSW_REGNUM : return H_CR_BBPSW;
case BBPC_REGNUM : return H_CR_BBPC;
case EVB_REGNUM : return H_CR_CR5;
}
abort ();
}
@ -49,7 +50,7 @@ int
m32rbf_fetch_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len)
{
if (rn < 16)
SETTWI (buf, a_m32r_h_gr_get (current_cpu, rn));
SETTWI (buf, m32rbf_h_gr_get (current_cpu, rn));
else
switch (rn)
{
@ -60,17 +61,17 @@ m32rbf_fetch_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len
case BPC_REGNUM :
case BBPSW_REGNUM :
case BBPC_REGNUM :
SETTWI (buf, a_m32r_h_cr_get (current_cpu,
SETTWI (buf, m32rbf_h_cr_get (current_cpu,
m32r_decode_gdb_ctrl_regnum (rn)));
break;
case PC_REGNUM :
SETTWI (buf, a_m32r_h_pc_get (current_cpu));
SETTWI (buf, m32rbf_h_pc_get (current_cpu));
break;
case ACCL_REGNUM :
SETTWI (buf, GETLODI (a_m32r_h_accum_get (current_cpu)));
SETTWI (buf, GETLODI (m32rbf_h_accum_get (current_cpu)));
break;
case ACCH_REGNUM :
SETTWI (buf, GETHIDI (a_m32r_h_accum_get (current_cpu)));
SETTWI (buf, GETHIDI (m32rbf_h_accum_get (current_cpu)));
break;
default :
return 0;
@ -85,7 +86,7 @@ int
m32rbf_store_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len)
{
if (rn < 16)
a_m32r_h_gr_set (current_cpu, rn, GETTWI (buf));
m32rbf_h_gr_set (current_cpu, rn, GETTWI (buf));
else
switch (rn)
{
@ -96,25 +97,25 @@ m32rbf_store_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len
case BPC_REGNUM :
case BBPSW_REGNUM :
case BBPC_REGNUM :
a_m32r_h_cr_set (current_cpu,
m32rbf_h_cr_set (current_cpu,
m32r_decode_gdb_ctrl_regnum (rn),
GETTWI (buf));
break;
case PC_REGNUM :
a_m32r_h_pc_set (current_cpu, GETTWI (buf));
m32rbf_h_pc_set (current_cpu, GETTWI (buf));
break;
case ACCL_REGNUM :
{
DI val = a_m32r_h_accum_get (current_cpu);
DI val = m32rbf_h_accum_get (current_cpu);
SETLODI (val, GETTWI (buf));
a_m32r_h_accum_set (current_cpu, val);
m32rbf_h_accum_set (current_cpu, val);
break;
}
case ACCH_REGNUM :
{
DI val = a_m32r_h_accum_get (current_cpu);
DI val = m32rbf_h_accum_get (current_cpu);
SETHIDI (val, GETTWI (buf));
a_m32r_h_accum_set (current_cpu, val);
m32rbf_h_accum_set (current_cpu, val);
break;
}
default :

311
sim/m32r/m32r2.c Normal file
View File

@ -0,0 +1,311 @@
/* m32r2 simulator support code
Copyright (C) 1997, 1998, 2003 Free Software Foundation, Inc.
Contributed by Cygnus Support.
This file is part of GDB, the GNU debugger.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#define WANT_CPU m32r2f
#define WANT_CPU_M32R2F
#include "sim-main.h"
#include "cgen-mem.h"
#include "cgen-ops.h"
/* The contents of BUF are in target byte order. */
int
m32r2f_fetch_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len)
{
return m32rbf_fetch_register (current_cpu, rn, buf, len);
}
/* The contents of BUF are in target byte order. */
int
m32r2f_store_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len)
{
return m32rbf_store_register (current_cpu, rn, buf, len);
}
/* Cover fns to get/set the control registers.
FIXME: Duplicated from m32r.c. The issue is structure offsets. */
USI
m32r2f_h_cr_get_handler (SIM_CPU *current_cpu, UINT cr)
{
switch (cr)
{
case H_CR_PSW : /* PSW. */
return (((CPU (h_bpsw) & 0xc1) << 8)
| ((CPU (h_psw) & 0xc0) << 0)
| GET_H_COND ());
case H_CR_BBPSW : /* Backup backup psw. */
return CPU (h_bbpsw) & 0xc1;
case H_CR_CBR : /* Condition bit. */
return GET_H_COND ();
case H_CR_SPI : /* Interrupt stack pointer. */
if (! GET_H_SM ())
return CPU (h_gr[H_GR_SP]);
else
return CPU (h_cr[H_CR_SPI]);
case H_CR_SPU : /* User stack pointer. */
if (GET_H_SM ())
return CPU (h_gr[H_GR_SP]);
else
return CPU (h_cr[H_CR_SPU]);
case H_CR_BPC : /* Backup pc. */
return CPU (h_cr[H_CR_BPC]) & 0xfffffffe;
case H_CR_BBPC : /* Backup backup pc. */
return CPU (h_cr[H_CR_BBPC]) & 0xfffffffe;
case 4 : /* ??? unspecified, but apparently available */
case 5 : /* ??? unspecified, but apparently available */
return CPU (h_cr[cr]);
default :
return 0;
}
}
void
m32r2f_h_cr_set_handler (SIM_CPU *current_cpu, UINT cr, USI newval)
{
switch (cr)
{
case H_CR_PSW : /* psw */
{
int old_sm = (CPU (h_psw) & 0x80) != 0;
int new_sm = (newval & 0x80) != 0;
CPU (h_bpsw) = (newval >> 8) & 0xff;
CPU (h_psw) = newval & 0xff;
SET_H_COND (newval & 1);
/* When switching stack modes, update the registers. */
if (old_sm != new_sm)
{
if (old_sm)
{
/* Switching user -> system. */
CPU (h_cr[H_CR_SPU]) = CPU (h_gr[H_GR_SP]);
CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPI]);
}
else
{
/* Switching system -> user. */
CPU (h_cr[H_CR_SPI]) = CPU (h_gr[H_GR_SP]);
CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPU]);
}
}
break;
}
case H_CR_BBPSW : /* backup backup psw */
CPU (h_bbpsw) = newval & 0xff;
break;
case H_CR_CBR : /* condition bit */
SET_H_COND (newval & 1);
break;
case H_CR_SPI : /* interrupt stack pointer */
if (! GET_H_SM ())
CPU (h_gr[H_GR_SP]) = newval;
else
CPU (h_cr[H_CR_SPI]) = newval;
break;
case H_CR_SPU : /* user stack pointer */
if (GET_H_SM ())
CPU (h_gr[H_GR_SP]) = newval;
else
CPU (h_cr[H_CR_SPU]) = newval;
break;
case H_CR_BPC : /* backup pc */
CPU (h_cr[H_CR_BPC]) = newval;
break;
case H_CR_BBPC : /* backup backup pc */
CPU (h_cr[H_CR_BBPC]) = newval;
break;
case 4 : /* ??? unspecified, but apparently available */
case 5 : /* ??? unspecified, but apparently available */
CPU (h_cr[cr]) = newval;
break;
default :
/* ignore */
break;
}
}
/* Cover fns to access h-psw. */
UQI
m32r2f_h_psw_get_handler (SIM_CPU *current_cpu)
{
return (CPU (h_psw) & 0xfe) | (CPU (h_cond) & 1);
}
void
m32r2f_h_psw_set_handler (SIM_CPU *current_cpu, UQI newval)
{
CPU (h_psw) = newval;
CPU (h_cond) = newval & 1;
}
/* Cover fns to access h-accum. */
DI
m32r2f_h_accum_get_handler (SIM_CPU *current_cpu)
{
/* Sign extend the top 8 bits. */
DI r;
r = ANDDI (CPU (h_accum), MAKEDI (0xffffff, 0xffffffff));
r = XORDI (r, MAKEDI (0x800000, 0));
r = SUBDI (r, MAKEDI (0x800000, 0));
return r;
}
void
m32r2f_h_accum_set_handler (SIM_CPU *current_cpu, DI newval)
{
CPU (h_accum) = newval;
}
/* Cover fns to access h-accums. */
DI
m32r2f_h_accums_get_handler (SIM_CPU *current_cpu, UINT regno)
{
/* FIXME: Yes, this is just a quick hack. */
DI r;
if (regno == 0)
r = CPU (h_accum);
else
r = CPU (h_accums[1]);
/* Sign extend the top 8 bits. */
r = ANDDI (r, MAKEDI (0xffffff, 0xffffffff));
r = XORDI (r, MAKEDI (0x800000, 0));
r = SUBDI (r, MAKEDI (0x800000, 0));
return r;
}
void
m32r2f_h_accums_set_handler (SIM_CPU *current_cpu, UINT regno, DI newval)
{
/* FIXME: Yes, this is just a quick hack. */
if (regno == 0)
CPU (h_accum) = newval;
else
CPU (h_accums[1]) = newval;
}
#if WITH_PROFILE_MODEL_P
/* Initialize cycle counting for an insn.
FIRST_P is non-zero if this is the first insn in a set of parallel
insns. */
void
m32r2f_model_insn_before (SIM_CPU *cpu, int first_p)
{
m32rbf_model_insn_before (cpu, first_p);
}
/* Record the cycles computed for an insn.
LAST_P is non-zero if this is the last insn in a set of parallel insns,
and we update the total cycle count.
CYCLES is the cycle count of the insn. */
void
m32r2f_model_insn_after (SIM_CPU *cpu, int last_p, int cycles)
{
m32rbf_model_insn_after (cpu, last_p, cycles);
}
static INLINE void
check_load_stall (SIM_CPU *cpu, int regno)
{
UINT h_gr = CPU_M32R_MISC_PROFILE (cpu)->load_regs;
if (regno != -1
&& (h_gr & (1 << regno)) != 0)
{
CPU_M32R_MISC_PROFILE (cpu)->load_stall += 2;
if (TRACE_INSN_P (cpu))
cgen_trace_printf (cpu, " ; Load stall of 2 cycles.");
}
}
int
m32r2f_model_m32r2_u_exec (SIM_CPU *cpu, const IDESC *idesc,
int unit_num, int referenced,
INT sr, INT sr2, INT dr)
{
check_load_stall (cpu, sr);
check_load_stall (cpu, sr2);
return idesc->timing->units[unit_num].done;
}
int
m32r2f_model_m32r2_u_cmp (SIM_CPU *cpu, const IDESC *idesc,
int unit_num, int referenced,
INT src1, INT src2)
{
check_load_stall (cpu, src1);
check_load_stall (cpu, src2);
return idesc->timing->units[unit_num].done;
}
int
m32r2f_model_m32r2_u_mac (SIM_CPU *cpu, const IDESC *idesc,
int unit_num, int referenced,
INT src1, INT src2)
{
check_load_stall (cpu, src1);
check_load_stall (cpu, src2);
return idesc->timing->units[unit_num].done;
}
int
m32r2f_model_m32r2_u_cti (SIM_CPU *cpu, const IDESC *idesc,
int unit_num, int referenced,
INT sr)
{
PROFILE_DATA *profile = CPU_PROFILE_DATA (cpu);
int taken_p = (referenced & (1 << 1)) != 0;
check_load_stall (cpu, sr);
if (taken_p)
{
CPU_M32R_MISC_PROFILE (cpu)->cti_stall += 2;
PROFILE_MODEL_TAKEN_COUNT (profile) += 1;
}
else
PROFILE_MODEL_UNTAKEN_COUNT (profile) += 1;
return idesc->timing->units[unit_num].done;
}
int
m32r2f_model_m32r2_u_load (SIM_CPU *cpu, const IDESC *idesc,
int unit_num, int referenced,
INT sr, INT dr)
{
CPU_M32R_MISC_PROFILE (cpu)->load_regs_pending |= (1 << dr);
return idesc->timing->units[unit_num].done;
}
int
m32r2f_model_m32r2_u_store (SIM_CPU *cpu, const IDESC *idesc,
int unit_num, int referenced,
INT src1, INT src2)
{
return idesc->timing->units[unit_num].done;
}
#endif /* WITH_PROFILE_MODEL_P */

193
sim/m32r/model.c
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -2280,6 +2280,107 @@ model_m32r_d_unlock (SIM_CPU *current_cpu, void *sem_arg)
#undef FLD
}
static int
model_m32r_d_clrpsw (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_clrpsw.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
INT in_sr = -1;
INT in_dr = -1;
INT out_dr = -1;
cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
}
return cycles;
#undef FLD
}
static int
model_m32r_d_setpsw (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_clrpsw.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
INT in_sr = -1;
INT in_dr = -1;
INT out_dr = -1;
cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
}
return cycles;
#undef FLD
}
static int
model_m32r_d_bset (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_bset.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
INT in_sr = -1;
INT in_dr = -1;
INT out_dr = -1;
in_sr = FLD (in_sr);
referenced |= 1 << 0;
cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
}
return cycles;
#undef FLD
}
static int
model_m32r_d_bclr (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_bset.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
INT in_sr = -1;
INT in_dr = -1;
INT out_dr = -1;
in_sr = FLD (in_sr);
referenced |= 1 << 0;
cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
}
return cycles;
#undef FLD
}
static int
model_m32r_d_btst (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_bset.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
INT in_sr = -1;
INT in_dr = -1;
INT out_dr = -1;
in_sr = FLD (in_sr);
referenced |= 1 << 0;
cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
}
return cycles;
#undef FLD
}
static int
model_test_add (SIM_CPU *current_cpu, void *sem_arg)
{
@ -3864,6 +3965,86 @@ model_test_unlock (SIM_CPU *current_cpu, void *sem_arg)
#undef FLD
}
static int
model_test_clrpsw (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_clrpsw.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_test_setpsw (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_clrpsw.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_test_bset (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_bset.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_test_bclr (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_bset.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_test_btst (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_bset.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
/* We assume UNIT_NONE == 0 because the tables don't always terminate
entries with it. */
@ -3975,6 +4156,11 @@ static const INSN_TIMING m32r_d_timing[] = {
{ M32RBF_INSN_SUBX, model_m32r_d_subx, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
{ M32RBF_INSN_TRAP, model_m32r_d_trap, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
{ M32RBF_INSN_UNLOCK, model_m32r_d_unlock, { { (int) UNIT_M32R_D_U_LOAD, 1, 1 } } },
{ M32RBF_INSN_CLRPSW, model_m32r_d_clrpsw, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
{ M32RBF_INSN_SETPSW, model_m32r_d_setpsw, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
{ M32RBF_INSN_BSET, model_m32r_d_bset, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
{ M32RBF_INSN_BCLR, model_m32r_d_bclr, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
{ M32RBF_INSN_BTST, model_m32r_d_btst, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
};
/* Model timing data for `test'. */
@ -4085,6 +4271,11 @@ static const INSN_TIMING test_timing[] = {
{ M32RBF_INSN_SUBX, model_test_subx, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
{ M32RBF_INSN_TRAP, model_test_trap, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
{ M32RBF_INSN_UNLOCK, model_test_unlock, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
{ M32RBF_INSN_CLRPSW, model_test_clrpsw, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
{ M32RBF_INSN_SETPSW, model_test_setpsw, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
{ M32RBF_INSN_BSET, model_test_bset, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
{ M32RBF_INSN_BCLR, model_test_bclr, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
{ M32RBF_INSN_BTST, model_test_btst, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
};
#endif /* WITH_PROFILE_MODEL_P */

3253
sim/m32r/model2.c Normal file
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File diff suppressed because it is too large Load Diff

174
sim/m32r/modelx.c
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -2315,6 +2315,70 @@ model_m32rx_st_plus (SIM_CPU *current_cpu, void *sem_arg)
#undef FLD
}
static int
model_m32rx_sth_plus (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_st_plus.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
INT in_src1 = 0;
INT in_src2 = 0;
in_src1 = FLD (in_src1);
in_src2 = FLD (in_src2);
referenced |= 1 << 0;
referenced |= 1 << 1;
cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
}
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
INT in_sr = -1;
INT in_dr = -1;
INT out_dr = -1;
in_dr = FLD (in_src2);
out_dr = FLD (out_src2);
cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 1, referenced, in_sr, in_dr, out_dr);
}
return cycles;
#undef FLD
}
static int
model_m32rx_stb_plus (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_st_plus.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
INT in_src1 = 0;
INT in_src2 = 0;
in_src1 = FLD (in_src1);
in_src2 = FLD (in_src2);
referenced |= 1 << 0;
referenced |= 1 << 1;
cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
}
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
INT in_sr = -1;
INT in_dr = -1;
INT out_dr = -1;
in_dr = FLD (in_src2);
out_dr = FLD (out_src2);
cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 1, referenced, in_sr, in_dr, out_dr);
}
return cycles;
#undef FLD
}
static int
model_m32rx_st_minus (SIM_CPU *current_cpu, void *sem_arg)
{
@ -2692,6 +2756,107 @@ model_m32rx_snc (SIM_CPU *current_cpu, void *sem_arg)
#undef FLD
}
static int
model_m32rx_clrpsw (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_clrpsw.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
INT in_sr = -1;
INT in_dr = -1;
INT out_dr = -1;
cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
}
return cycles;
#undef FLD
}
static int
model_m32rx_setpsw (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_clrpsw.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
INT in_sr = -1;
INT in_dr = -1;
INT out_dr = -1;
cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
}
return cycles;
#undef FLD
}
static int
model_m32rx_bset (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_bset.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
INT in_sr = -1;
INT in_dr = -1;
INT out_dr = -1;
in_sr = FLD (in_sr);
referenced |= 1 << 0;
cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
}
return cycles;
#undef FLD
}
static int
model_m32rx_bclr (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_bset.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
INT in_sr = -1;
INT in_dr = -1;
INT out_dr = -1;
in_sr = FLD (in_sr);
referenced |= 1 << 0;
cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
}
return cycles;
#undef FLD
}
static int
model_m32rx_btst (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_bset.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
INT in_sr = -1;
INT in_dr = -1;
INT out_dr = -1;
in_sr = FLD (in_sr);
referenced |= 1 << 0;
cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
}
return cycles;
#undef FLD
}
/* We assume UNIT_NONE == 0 because the tables don't always terminate
entries with it. */
@ -2806,6 +2971,8 @@ static const INSN_TIMING m32rx_timing[] = {
{ M32RXF_INSN_STH, model_m32rx_sth, { { (int) UNIT_M32RX_U_STORE, 1, 1 } } },
{ M32RXF_INSN_STH_D, model_m32rx_sth_d, { { (int) UNIT_M32RX_U_STORE, 1, 2 } } },
{ M32RXF_INSN_ST_PLUS, model_m32rx_st_plus, { { (int) UNIT_M32RX_U_STORE, 1, 1 }, { (int) UNIT_M32RX_U_EXEC, 1, 0 } } },
{ M32RXF_INSN_STH_PLUS, model_m32rx_sth_plus, { { (int) UNIT_M32RX_U_STORE, 1, 1 }, { (int) UNIT_M32RX_U_EXEC, 1, 0 } } },
{ M32RXF_INSN_STB_PLUS, model_m32rx_stb_plus, { { (int) UNIT_M32RX_U_STORE, 1, 1 }, { (int) UNIT_M32RX_U_EXEC, 1, 0 } } },
{ M32RXF_INSN_ST_MINUS, model_m32rx_st_minus, { { (int) UNIT_M32RX_U_STORE, 1, 1 }, { (int) UNIT_M32RX_U_EXEC, 1, 0 } } },
{ M32RXF_INSN_SUB, model_m32rx_sub, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
{ M32RXF_INSN_SUBV, model_m32rx_subv, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
@ -2823,6 +2990,11 @@ static const INSN_TIMING m32rx_timing[] = {
{ M32RXF_INSN_MACLH1, model_m32rx_maclh1, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
{ M32RXF_INSN_SC, model_m32rx_sc, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
{ M32RXF_INSN_SNC, model_m32rx_snc, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
{ M32RXF_INSN_CLRPSW, model_m32rx_clrpsw, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
{ M32RXF_INSN_SETPSW, model_m32rx_setpsw, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
{ M32RXF_INSN_BSET, model_m32rx_bset, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
{ M32RXF_INSN_BCLR, model_m32rx_bclr, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
{ M32RXF_INSN_BTST, model_m32rx_btst, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
};
#endif /* WITH_PROFILE_MODEL_P */

102
sim/m32r/sem-switch.c
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -137,6 +137,11 @@ with this program; if not, write to the Free Software Foundation, Inc.,
{ M32RBF_INSN_SUBX, && case_sem_INSN_SUBX },
{ M32RBF_INSN_TRAP, && case_sem_INSN_TRAP },
{ M32RBF_INSN_UNLOCK, && case_sem_INSN_UNLOCK },
{ M32RBF_INSN_CLRPSW, && case_sem_INSN_CLRPSW },
{ M32RBF_INSN_SETPSW, && case_sem_INSN_SETPSW },
{ M32RBF_INSN_BSET, && case_sem_INSN_BSET },
{ M32RBF_INSN_BCLR, && case_sem_INSN_BCLR },
{ M32RBF_INSN_BTST, && case_sem_INSN_BTST },
{ 0, 0 }
};
int i;
@ -2504,6 +2509,101 @@ if (CPU (h_lock)) {
}
NEXT (vpc);
CASE (sem, INSN_CLRPSW) : /* clrpsw $uimm8 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_clrpsw.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI opval = ANDSI (GET_H_CR (((UINT) 0)), ORSI (INVBI (FLD (f_uimm8)), 65280));
SET_H_CR (((UINT) 0), opval);
TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_SETPSW) : /* setpsw $uimm8 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_clrpsw.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI opval = FLD (f_uimm8);
SET_H_CR (((UINT) 0), opval);
TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_BSET) : /* bset $uimm3,@($slo16,$sr) */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_bset.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
QI opval = ORQI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))), SLLSI (1, SUBSI (7, FLD (f_uimm3))));
SETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16)), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_BCLR) : /* bclr $uimm3,@($slo16,$sr) */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_bset.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
QI opval = ANDQI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))), INVQI (SLLSI (1, SUBSI (7, FLD (f_uimm3)))));
SETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16)), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_BTST) : /* btst $uimm3,$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_bset.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
BI opval = ANDQI (SRLSI (* FLD (i_sr), SUBSI (7, FLD (f_uimm3))), 1);
CPU (h_cond) = opval;
TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
}
#undef FLD
}
NEXT (vpc);
}
ENDSWITCH (sem) /* End of semantic switch. */

112
sim/m32r/sem.c
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -2563,6 +2563,111 @@ if (CPU (h_lock)) {
#undef FLD
}
/* clrpsw: clrpsw $uimm8 */
static SEM_PC
SEM_FN_NAME (m32rbf,clrpsw) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_clrpsw.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI opval = ANDSI (GET_H_CR (((UINT) 0)), ORSI (INVBI (FLD (f_uimm8)), 65280));
SET_H_CR (((UINT) 0), opval);
TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
}
return vpc;
#undef FLD
}
/* setpsw: setpsw $uimm8 */
static SEM_PC
SEM_FN_NAME (m32rbf,setpsw) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_clrpsw.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI opval = FLD (f_uimm8);
SET_H_CR (((UINT) 0), opval);
TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
}
return vpc;
#undef FLD
}
/* bset: bset $uimm3,@($slo16,$sr) */
static SEM_PC
SEM_FN_NAME (m32rbf,bset) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_bset.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
QI opval = ORQI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))), SLLSI (1, SUBSI (7, FLD (f_uimm3))));
SETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16)), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
return vpc;
#undef FLD
}
/* bclr: bclr $uimm3,@($slo16,$sr) */
static SEM_PC
SEM_FN_NAME (m32rbf,bclr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_bset.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
QI opval = ANDQI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))), INVQI (SLLSI (1, SUBSI (7, FLD (f_uimm3)))));
SETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16)), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
return vpc;
#undef FLD
}
/* btst: btst $uimm3,$sr */
static SEM_PC
SEM_FN_NAME (m32rbf,btst) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_bset.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
BI opval = ANDQI (SRLSI (* FLD (i_sr), SUBSI (7, FLD (f_uimm3))), 1);
CPU (h_cond) = opval;
TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
}
return vpc;
#undef FLD
}
/* Table of all semantic fns. */
static const struct sem_fn_desc sem_fns[] = {
@ -2671,6 +2776,11 @@ static const struct sem_fn_desc sem_fns[] = {
{ M32RBF_INSN_SUBX, SEM_FN_NAME (m32rbf,subx) },
{ M32RBF_INSN_TRAP, SEM_FN_NAME (m32rbf,trap) },
{ M32RBF_INSN_UNLOCK, SEM_FN_NAME (m32rbf,unlock) },
{ M32RBF_INSN_CLRPSW, SEM_FN_NAME (m32rbf,clrpsw) },
{ M32RBF_INSN_SETPSW, SEM_FN_NAME (m32rbf,setpsw) },
{ M32RBF_INSN_BSET, SEM_FN_NAME (m32rbf,bset) },
{ M32RBF_INSN_BCLR, SEM_FN_NAME (m32rbf,bclr) },
{ M32RBF_INSN_BTST, SEM_FN_NAME (m32rbf,btst) },
{ 0, 0 }
};

6822
sim/m32r/sem2-switch.c Normal file
View File

File diff suppressed because it is too large Load Diff

382
sim/m32r/semx-switch.c
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -140,6 +140,8 @@ with this program; if not, write to the Free Software Foundation, Inc.,
{ M32RXF_INSN_STH, && case_sem_INSN_STH },
{ M32RXF_INSN_STH_D, && case_sem_INSN_STH_D },
{ M32RXF_INSN_ST_PLUS, && case_sem_INSN_ST_PLUS },
{ M32RXF_INSN_STH_PLUS, && case_sem_INSN_STH_PLUS },
{ M32RXF_INSN_STB_PLUS, && case_sem_INSN_STB_PLUS },
{ M32RXF_INSN_ST_MINUS, && case_sem_INSN_ST_MINUS },
{ M32RXF_INSN_SUB, && case_sem_INSN_SUB },
{ M32RXF_INSN_SUBV, && case_sem_INSN_SUBV },
@ -157,6 +159,11 @@ with this program; if not, write to the Free Software Foundation, Inc.,
{ M32RXF_INSN_MACLH1, && case_sem_INSN_MACLH1 },
{ M32RXF_INSN_SC, && case_sem_INSN_SC },
{ M32RXF_INSN_SNC, && case_sem_INSN_SNC },
{ M32RXF_INSN_CLRPSW, && case_sem_INSN_CLRPSW },
{ M32RXF_INSN_SETPSW, && case_sem_INSN_SETPSW },
{ M32RXF_INSN_BSET, && case_sem_INSN_BSET },
{ M32RXF_INSN_BCLR, && case_sem_INSN_BCLR },
{ M32RXF_INSN_BTST, && case_sem_INSN_BTST },
{ M32RXF_INSN_PAR_ADD, && case_sem_INSN_PAR_ADD },
{ M32RXF_INSN_WRITE_ADD, && case_sem_INSN_WRITE_ADD },
{ M32RXF_INSN_PAR_AND, && case_sem_INSN_PAR_AND },
@ -281,6 +288,10 @@ with this program; if not, write to the Free Software Foundation, Inc.,
{ M32RXF_INSN_WRITE_STH, && case_sem_INSN_WRITE_STH },
{ M32RXF_INSN_PAR_ST_PLUS, && case_sem_INSN_PAR_ST_PLUS },
{ M32RXF_INSN_WRITE_ST_PLUS, && case_sem_INSN_WRITE_ST_PLUS },
{ M32RXF_INSN_PAR_STH_PLUS, && case_sem_INSN_PAR_STH_PLUS },
{ M32RXF_INSN_WRITE_STH_PLUS, && case_sem_INSN_WRITE_STH_PLUS },
{ M32RXF_INSN_PAR_STB_PLUS, && case_sem_INSN_PAR_STB_PLUS },
{ M32RXF_INSN_WRITE_STB_PLUS, && case_sem_INSN_WRITE_STB_PLUS },
{ M32RXF_INSN_PAR_ST_MINUS, && case_sem_INSN_PAR_ST_MINUS },
{ M32RXF_INSN_WRITE_ST_MINUS, && case_sem_INSN_WRITE_ST_MINUS },
{ M32RXF_INSN_PAR_SUB, && case_sem_INSN_PAR_SUB },
@ -309,6 +320,12 @@ with this program; if not, write to the Free Software Foundation, Inc.,
{ M32RXF_INSN_WRITE_SC, && case_sem_INSN_WRITE_SC },
{ M32RXF_INSN_PAR_SNC, && case_sem_INSN_PAR_SNC },
{ M32RXF_INSN_WRITE_SNC, && case_sem_INSN_WRITE_SNC },
{ M32RXF_INSN_PAR_CLRPSW, && case_sem_INSN_PAR_CLRPSW },
{ M32RXF_INSN_WRITE_CLRPSW, && case_sem_INSN_WRITE_CLRPSW },
{ M32RXF_INSN_PAR_SETPSW, && case_sem_INSN_PAR_SETPSW },
{ M32RXF_INSN_WRITE_SETPSW, && case_sem_INSN_WRITE_SETPSW },
{ M32RXF_INSN_PAR_BTST, && case_sem_INSN_PAR_BTST },
{ M32RXF_INSN_WRITE_BTST, && case_sem_INSN_WRITE_BTST },
{ 0, 0 }
};
int i;
@ -2723,6 +2740,62 @@ PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr);
}
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_STH_PLUS) : /* sth $src1,@$src2+ */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_st_plus.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
HI tmp_new_src2;
{
HI opval = * FLD (i_src1);
SETMEMHI (current_cpu, pc, tmp_new_src2, opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
tmp_new_src2 = ADDSI (* FLD (i_src2), 2);
{
SI opval = tmp_new_src2;
* FLD (i_src2) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_STB_PLUS) : /* stb $src1,@$src2+ */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_st_plus.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
QI tmp_new_src2;
{
QI opval = * FLD (i_src1);
SETMEMQI (current_cpu, pc, tmp_new_src2, opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
tmp_new_src2 = ADDSI (* FLD (i_src2), 1);
{
SI opval = tmp_new_src2;
* FLD (i_src2) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
}
#undef FLD
}
NEXT (vpc);
@ -3109,6 +3182,101 @@ if (ZEXTBISI (CPU (h_cond)))
if (ZEXTBISI (NOTBI (CPU (h_cond))))
SEM_SKIP_INSN (current_cpu, sem_arg, vpc);
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_CLRPSW) : /* clrpsw $uimm8 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_clrpsw.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI opval = ANDSI (GET_H_CR (((UINT) 0)), ORSI (INVBI (FLD (f_uimm8)), 65280));
SET_H_CR (((UINT) 0), opval);
TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_SETPSW) : /* setpsw $uimm8 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_clrpsw.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI opval = FLD (f_uimm8);
SET_H_CR (((UINT) 0), opval);
TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_BSET) : /* bset $uimm3,@($slo16,$sr) */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_bset.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
QI opval = ORQI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))), SLLSI (1, SUBSI (7, FLD (f_uimm3))));
SETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16)), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_BCLR) : /* bclr $uimm3,@($slo16,$sr) */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_bset.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
QI opval = ANDQI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))), INVQI (SLLSI (1, SUBSI (7, FLD (f_uimm3)))));
SETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16)), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_BTST) : /* btst $uimm3,$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_bset.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
BI opval = ANDQI (SRLSI (* FLD (i_sr), SUBSI (7, FLD (f_uimm3))), 1);
CPU (h_cond) = opval;
TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
}
#undef FLD
}
NEXT (vpc);
@ -5651,6 +5819,104 @@ CASE (sem, INSN_WRITE_ST_PLUS) : /* st $src1,@+$src2 */
SETMEMSI (current_cpu, pc, OPRND (h_memory_SI_new_src2_idx), OPRND (h_memory_SI_new_src2));
* FLD (i_src2) = OPRND (src2);
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_STH_PLUS) : /* sth $src1,@$src2+ */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_st_plus.f
#define OPRND(f) par_exec->operands.sfmt_sth_plus.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
HI tmp_new_src2;
{
HI opval = * FLD (i_src1);
OPRND (h_memory_HI_new_src2_idx) = tmp_new_src2;
OPRND (h_memory_HI_new_src2) = opval;
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
tmp_new_src2 = ADDSI (* FLD (i_src2), 2);
{
SI opval = tmp_new_src2;
OPRND (src2) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
}
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_STH_PLUS) : /* sth $src1,@$src2+ */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_st_plus.f
#define OPRND(f) par_exec->operands.sfmt_sth_plus.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
SETMEMHI (current_cpu, pc, OPRND (h_memory_HI_new_src2_idx), OPRND (h_memory_HI_new_src2));
* FLD (i_src2) = OPRND (src2);
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_STB_PLUS) : /* stb $src1,@$src2+ */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_st_plus.f
#define OPRND(f) par_exec->operands.sfmt_stb_plus.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
QI tmp_new_src2;
{
QI opval = * FLD (i_src1);
OPRND (h_memory_QI_new_src2_idx) = tmp_new_src2;
OPRND (h_memory_QI_new_src2) = opval;
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
tmp_new_src2 = ADDSI (* FLD (i_src2), 1);
{
SI opval = tmp_new_src2;
OPRND (src2) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
}
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_STB_PLUS) : /* stb $src1,@$src2+ */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_st_plus.f
#define OPRND(f) par_exec->operands.sfmt_stb_plus.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
SETMEMQI (current_cpu, pc, OPRND (h_memory_QI_new_src2_idx), OPRND (h_memory_QI_new_src2));
* FLD (i_src2) = OPRND (src2);
#undef OPRND
#undef FLD
}
@ -6258,6 +6524,120 @@ CASE (sem, INSN_WRITE_SNC) : /* snc */
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_CLRPSW) : /* clrpsw $uimm8 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_clrpsw.f
#define OPRND(f) par_exec->operands.sfmt_clrpsw.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI opval = ANDSI (GET_H_CR (((UINT) 0)), ORSI (INVBI (FLD (f_uimm8)), 65280));
OPRND (h_cr_USI_0) = opval;
TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
}
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_CLRPSW) : /* clrpsw $uimm8 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_clrpsw.f
#define OPRND(f) par_exec->operands.sfmt_clrpsw.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
SET_H_CR (((UINT) 0), OPRND (h_cr_USI_0));
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_SETPSW) : /* setpsw $uimm8 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_clrpsw.f
#define OPRND(f) par_exec->operands.sfmt_setpsw.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI opval = FLD (f_uimm8);
OPRND (h_cr_USI_0) = opval;
TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
}
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_SETPSW) : /* setpsw $uimm8 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_clrpsw.f
#define OPRND(f) par_exec->operands.sfmt_setpsw.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
SET_H_CR (((UINT) 0), OPRND (h_cr_USI_0));
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_BTST) : /* btst $uimm3,$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_bset.f
#define OPRND(f) par_exec->operands.sfmt_btst.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
BI opval = ANDQI (SRLSI (* FLD (i_sr), SUBSI (7, FLD (f_uimm3))), 1);
OPRND (condbit) = opval;
TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
}
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_BTST) : /* btst $uimm3,$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_bset.f
#define OPRND(f) par_exec->operands.sfmt_btst.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
CPU (h_cond) = OPRND (condbit);
#undef OPRND
#undef FLD
}

35
sim/m32r/sim-if.c
View File

@ -1,20 +1,22 @@
/* Main simulator entry points specific to the M32R.
Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
Copyright (C) 1996, 1997, 1998, 1999, 2003 Free Software Foundation, Inc.
Contributed by Cygnus Support.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This file is part of GDB, the GNU debugger.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#include "sim-main.h"
#include "sim-options.h"
@ -240,6 +242,11 @@ print_m32r_misc_cpu (SIM_CPU *cpu, int verbose)
PROFILE_LABEL_WIDTH, "Parallel insns:",
sim_add_commas (buf, sizeof (buf),
CPU_M32R_MISC_PROFILE (cpu)->parallel_count));
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_m32r2)
sim_io_printf (sd, " %-*s %s\n\n",
PROFILE_LABEL_WIDTH, "Parallel insns:",
sim_add_commas (buf, sizeof (buf),
CPU_M32R_MISC_PROFILE (cpu)->parallel_count));
}
}
@ -270,12 +277,12 @@ sim_do_command (sd, cmd)
sim_io_eprintf (sd, "Too many arguments in `%s'\n", cmd);
else if (strcasecmp (argv[2], "bbpsw") == 0)
{
val = a_m32r_h_cr_get (STATE_CPU (sd, 0), H_CR_BBPSW);
val = m32rbf_h_cr_get (STATE_CPU (sd, 0), H_CR_BBPSW);
sim_io_printf (sd, "bbpsw 0x%x %d\n", val, val);
}
else if (strcasecmp (argv[2], "bbpc") == 0)
{
val = a_m32r_h_cr_get (STATE_CPU (sd, 0), H_CR_BBPC);
val = m32rbf_h_cr_get (STATE_CPU (sd, 0), H_CR_BBPC);
sim_io_printf (sd, "bbpc 0x%x %d\n", val, val);
}
else

5
sim/m32r/sim-main.h
View File

@ -58,6 +58,11 @@ struct _sim_cpu {
#if defined (WANT_CPU_M32RBF)
M32RBF_CPU_DATA cpu_data;
#endif
#if defined (WANT_CPU_M32RXF)
M32RXF_CPU_DATA cpu_data;
#elif defined (WANT_CPU_M32R2F)
M32R2F_CPU_DATA cpu_data;
#endif
};
/* The sim_state struct. */

91
sim/m32r/traps.c
View File

@ -1,30 +1,31 @@
/* m32r exception, interrupt, and trap (EIT) support
Copyright (C) 1998 Free Software Foundation, Inc.
Copyright (C) 1998, 2003 Free Software Foundation, Inc.
Contributed by Cygnus Solutions.
This file is part of GDB, the GNU debugger.
This file is part of GDB, the GNU debugger.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#include "sim-main.h"
#include "targ-vals.h"
#define TRAP_FLUSH_CACHE 12
/* The semantic code invokes this for invalid (unrecognized) instructions. */
void
sim_engine_invalid_insn (SIM_CPU *current_cpu, IADDR cia)
SEM_PC
sim_engine_invalid_insn (SIM_CPU *current_cpu, IADDR cia, SEM_PC pc)
{
SIM_DESC sd = CPU_STATE (current_cpu);
@ -46,6 +47,8 @@ sim_engine_invalid_insn (SIM_CPU *current_cpu, IADDR cia)
else
#endif
sim_engine_halt (sd, current_cpu, NULL, cia, sim_stopped, SIM_SIGILL);
return pc;
}
/* Process an address exception. */
@ -57,12 +60,30 @@ m32r_core_signal (SIM_DESC sd, SIM_CPU *current_cpu, sim_cia cia,
{
if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT)
{
a_m32r_h_cr_set (current_cpu, H_CR_BBPC,
a_m32r_h_cr_get (current_cpu, H_CR_BPC));
a_m32r_h_bpsw_set (current_cpu, a_m32r_h_psw_get (current_cpu));
/* sm not changed */
a_m32r_h_psw_set (current_cpu, a_m32r_h_psw_get (current_cpu) & 0x80);
a_m32r_h_cr_set (current_cpu, H_CR_BPC, cia);
m32rbf_h_cr_set (current_cpu, H_CR_BBPC,
m32rbf_h_cr_get (current_cpu, H_CR_BPC));
switch (MACH_NUM (CPU_MACH (current_cpu)))
{
case MACH_M32R:
m32rbf_h_bpsw_set (current_cpu, m32rbf_h_psw_get (current_cpu));
/* sm not changed. */
m32rbf_h_psw_set (current_cpu, m32rbf_h_psw_get (current_cpu) & 0x80);
break;
case MACH_M32RX:
m32rxf_h_bpsw_set (current_cpu, m32rxf_h_psw_get (current_cpu));
/* sm not changed. */
m32rxf_h_psw_set (current_cpu, m32rxf_h_psw_get (current_cpu) & 0x80);
break;
case MACH_M32R2:
m32r2f_h_bpsw_set (current_cpu, m32r2f_h_psw_get (current_cpu));
/* sm not changed. */
m32r2f_h_psw_set (current_cpu, m32r2f_h_psw_get (current_cpu) & 0x80);
break;
default:
abort ();
}
m32rbf_h_cr_set (current_cpu, H_CR_BPC, cia);
sim_engine_restart (CPU_STATE (current_cpu), current_cpu, NULL,
EIT_ADDR_EXCP_ADDR);
@ -119,8 +140,10 @@ m32r_trap (SIM_CPU *current_cpu, PCADDR pc, int num)
if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT)
{
/* The new pc is the trap vector entry.
We assume there's a branch there to some handler. */
USI new_pc = EIT_TRAP_BASE_ADDR + num * 4;
We assume there's a branch there to some handler.
Use cr5 as EVB (EIT Vector Base) register. */
/* USI new_pc = EIT_TRAP_BASE_ADDR + num * 4; */
USI new_pc = m32rbf_h_cr_get (current_cpu, 5) + 0x40 + num * 4;
return new_pc;
}
@ -131,10 +154,10 @@ m32r_trap (SIM_CPU *current_cpu, PCADDR pc, int num)
CB_SYSCALL s;
CB_SYSCALL_INIT (&s);
s.func = a_m32r_h_gr_get (current_cpu, 0);
s.arg1 = a_m32r_h_gr_get (current_cpu, 1);
s.arg2 = a_m32r_h_gr_get (current_cpu, 2);
s.arg3 = a_m32r_h_gr_get (current_cpu, 3);
s.func = m32rbf_h_gr_get (current_cpu, 0);
s.arg1 = m32rbf_h_gr_get (current_cpu, 1);
s.arg2 = m32rbf_h_gr_get (current_cpu, 2);
s.arg3 = m32rbf_h_gr_get (current_cpu, 3);
if (s.func == TARGET_SYS_exit)
{
@ -146,9 +169,9 @@ m32r_trap (SIM_CPU *current_cpu, PCADDR pc, int num)
s.read_mem = syscall_read_mem;
s.write_mem = syscall_write_mem;
cb_syscall (cb, &s);
a_m32r_h_gr_set (current_cpu, 2, s.errcode);
a_m32r_h_gr_set (current_cpu, 0, s.result);
a_m32r_h_gr_set (current_cpu, 1, s.result2);
m32rbf_h_gr_set (current_cpu, 2, s.errcode);
m32rbf_h_gr_set (current_cpu, 0, s.result);
m32rbf_h_gr_set (current_cpu, 1, s.result2);
break;
}
@ -157,9 +180,15 @@ m32r_trap (SIM_CPU *current_cpu, PCADDR pc, int num)
sim_stopped, SIM_SIGTRAP);
break;
case TRAP_FLUSH_CACHE:
/* Do nothing. */
break;
default :
{
USI new_pc = EIT_TRAP_BASE_ADDR + num * 4;
/* USI new_pc = EIT_TRAP_BASE_ADDR + num * 4; */
/* Use cr5 as EVB (EIT Vector Base) register. */
USI new_pc = m32rbf_h_cr_get (current_cpu, 5) + 0x40 + num * 4;
return new_pc;
}
}