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2008-03-08 Paul Brook <paul@codesourcery.com>
bfd/ * elf32-arm.c (insert_thumb_branch): Rewrite. (elf32_thumb_to_arm_stub): Use new insert_thumb_branch. ld/testsuite/ * ld-arm/arm-elf.exp (armeabitests): Add thumb2-b-interwork. * ld-arm/thumb2-b-interwork.d: New test. * ld-arm/thumb2-b-interwork.s: New test.
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Paul Brook
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@ -1,3 +1,8 @@
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2008-03-08 Paul Brook <paul@codesourcery.com>
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* elf32-arm.c (insert_thumb_branch): Rewrite.
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(elf32_thumb_to_arm_stub): Use new insert_thumb_branch.
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2008-03-07 Paul Brook <paul@codesourcery.com>
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* elf32-arm.c (elf32_arm_howto_table_1): Fix bitmasks for MOVW and
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@ -4070,58 +4070,29 @@ bfd_elf32_arm_set_target_relocs (struct bfd *output_bfd,
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elf_arm_tdata (output_bfd)->no_enum_size_warning = no_enum_warn;
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}
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/* The thumb form of a long branch is a bit finicky, because the offset
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encoding is split over two fields, each in it's own instruction. They
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can occur in any order. So given a thumb form of long branch, and an
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offset, insert the offset into the thumb branch and return finished
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instruction.
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/* Replace the target offset of a Thumb bl or b.w instruction. */
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It takes two thumb instructions to encode the target address. Each has
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11 bits to invest. The upper 11 bits are stored in one (identified by
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H-0.. see below), the lower 11 bits are stored in the other (identified
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by H-1).
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Combine together and shifted left by 1 (it's a half word address) and
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there you have it.
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Op: 1111 = F,
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H-0, upper address-0 = 000
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Op: 1111 = F,
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H-1, lower address-0 = 800
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They can be ordered either way, but the arm tools I've seen always put
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the lower one first. It probably doesn't matter. krk@cygnus.com
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XXX: Actually the order does matter. The second instruction (H-1)
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moves the computed address into the PC, so it must be the second one
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in the sequence. The problem, however is that whilst little endian code
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stores the instructions in HI then LOW order, big endian code does the
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reverse. nickc@cygnus.com. */
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#define LOW_HI_ORDER 0xF800F000
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#define HI_LOW_ORDER 0xF000F800
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static insn32
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insert_thumb_branch (insn32 br_insn, int rel_off)
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static void
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insert_thumb_branch (bfd *abfd, long int offset, bfd_byte *insn)
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{
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unsigned int low_bits;
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unsigned int high_bits;
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bfd_vma upper;
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bfd_vma lower;
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int reloc_sign;
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BFD_ASSERT ((rel_off & 1) != 1);
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BFD_ASSERT ((offset & 1) == 0);
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rel_off >>= 1; /* Half word aligned address. */
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low_bits = rel_off & 0x000007FF; /* The bottom 11 bits. */
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high_bits = (rel_off >> 11) & 0x000007FF; /* The top 11 bits. */
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if ((br_insn & LOW_HI_ORDER) == LOW_HI_ORDER)
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br_insn = LOW_HI_ORDER | (low_bits << 16) | high_bits;
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else if ((br_insn & HI_LOW_ORDER) == HI_LOW_ORDER)
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br_insn = HI_LOW_ORDER | (high_bits << 16) | low_bits;
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else
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/* FIXME: abort is probably not the right call. krk@cygnus.com */
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abort (); /* Error - not a valid branch instruction form. */
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return br_insn;
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upper = bfd_get_16 (abfd, insn);
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lower = bfd_get_16 (abfd, insn + 2);
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reloc_sign = (offset < 0) ? 1 : 0;
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upper = (upper & ~(bfd_vma) 0x7ff)
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| ((offset >> 12) & 0x3ff)
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| (reloc_sign << 10);
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lower = (lower & ~(bfd_vma) 0x2fff)
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| (((!((offset >> 23) & 1)) ^ reloc_sign) << 13)
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| (((!((offset >> 22) & 1)) ^ reloc_sign) << 11)
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| ((offset >> 1) & 0x7ff);
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bfd_put_16 (abfd, upper, insn);
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bfd_put_16 (abfd, lower, insn + 2);
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}
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@ -4170,7 +4141,6 @@ elf32_thumb_to_arm_stub (struct bfd_link_info * info,
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{
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asection * s = 0;
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bfd_vma my_offset;
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unsigned long int tmp;
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long int ret_offset;
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struct elf_link_hash_entry * myh;
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struct elf32_arm_link_hash_table * globals;
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@ -4251,12 +4221,7 @@ elf32_thumb_to_arm_stub (struct bfd_link_info * info,
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/* Biassing for PC-relative addressing. */
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- 8;
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tmp = bfd_get_32 (input_bfd, hit_data
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- input_section->vma);
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bfd_put_32 (output_bfd,
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(bfd_vma) insert_thumb_branch (tmp, ret_offset),
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hit_data - input_section->vma);
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insert_thumb_branch (input_bfd, ret_offset, hit_data - input_section->vma);
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return TRUE;
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}
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@ -1,3 +1,9 @@
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2008-03-08 Paul Brook <paul@codesourcery.com>
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* ld-arm/arm-elf.exp (armeabitests): Add thumb2-b-interwork.
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* ld-arm/thumb2-b-interwork.d: New test.
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* ld-arm/thumb2-b-interwork.s: New test.
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2008-03-07 Paul Brook <paul@codesourcery.com>
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* ld-arm/arm-elf.exp (armelftests): Add movw-merge and arm-app-movw.
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@ -209,6 +209,9 @@ set armeabitests {
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{"Thumb-2 BL" "-Ttext 0x1000 --section-start .foo=0x1001000" "" {thumb2-bl.s}
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{{objdump -dr thumb2-bl.d}}
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"thumb2-bl"}
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{"Thumb-2 Interworked branch" "-T arm.ld" "" {thumb2-b-interwork.s}
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{{objdump -dr thumb2-b-interwork.d}}
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"thumb2-b-interwork"}
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}
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run_ld_link_tests $armeabitests
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19
ld/testsuite/ld-arm/thumb2-b-interwork.d
Normal file
19
ld/testsuite/ld-arm/thumb2-b-interwork.d
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@ -0,0 +1,19 @@
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.*thumb2-b-interwork: file format elf32-.*arm
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Disassembly of section .text:
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00008000 <_start>:
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8000: f000 b802 b.w 8008 <__bar_from_thumb>
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00008004 <bar>:
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8004: e12fff1e bx lr
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Disassembly of section .glue_7t:
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00008008 <__bar_from_thumb>:
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8008: 4778 bx pc
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800a: 46c0 nop \(mov r8, r8\)
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0000800c <__bar_change_to_arm>:
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800c: eafffffc b 8004 <bar>
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20
ld/testsuite/ld-arm/thumb2-b-interwork.s
Normal file
20
ld/testsuite/ld-arm/thumb2-b-interwork.s
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@ Test to ensure that a Thumb-2 B.W can branch to an ARM funtion.
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.arch armv7-a
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.global _start
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.syntax unified
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.text
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.thumb_func
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_start:
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b.w bar
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@ Put this in a separate section to force the assembler to generate a reloc
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.arm
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.section .after, "xa"
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.global bar
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.type bar, %function
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bar:
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bx lr
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