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Updated ARC assembler from arccores.com

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This commit is contained in:
Nick Clifton 2001-01-11 21:20:20 +00:00
parent 8805103910
commit 0d2bcfafbf
108 changed files with 7925 additions and 2456 deletions
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13
bfd/ChangeLog
View File

@ -1,3 +1,16 @@
2001-01-11 Peter Targett <peter.targett@arccores.com>
* bfd-in2.h (bfd_architecture): Add bfd_mach_arc_5,
bfd_mach_arc_6, bfd_mach_arc_7, bfd_mach_arc_8 for ARC variants.
* cpu-arc.c (arch_info_struct): Add entries for variants.
(bfd_arc_arch) Set default to bfd_mach_arc_5.
(arc_get_mach) Don't assume machine names prefixed arc- before
testing.
* elf32-arc.c (arc_elf_object_p): Set machine number based on new
selections.
(arc_elf_final_write_processing) Likewise.
(ELF_MACHINE_CODE) Use EM_ARC.
2001-01-10 Nick Clifton <nickc@redhat.com>
* coff-arm.c (LOCAL_LABEL_PREFIX): Change definition to "".

7
bfd/archures.c
View File

@ -222,8 +222,11 @@ DESCRIPTION
.#define bfd_mach_v850 0
.#define bfd_mach_v850e 'E'
.#define bfd_mach_v850ea 'A'
. bfd_arch_arc, {* Argonaut RISC Core *}
.#define bfd_mach_arc_base 0
. bfd_arch_arc, {* ARC Cores *}
.#define bfd_mach_arc_5 0
.#define bfd_mach_arc_6 1
.#define bfd_mach_arc_7 2
.#define bfd_mach_arc_8 3
. bfd_arch_m32r, {* Mitsubishi M32R/D *}
.#define bfd_mach_m32r 0 {* backwards compatibility *}
.#define bfd_mach_m32rx 'x'

21
bfd/bfd-in2.h
View File

@ -813,13 +813,13 @@ bfd_make_readable PARAMS ((bfd *abfd));
/* Byte swapping macros for user section data. */
#define bfd_put_8(abfd, val, ptr) \
((void) (*((unsigned char *)(ptr)) = (unsigned char)(val)))
((void) (*((unsigned char *) (ptr)) = (unsigned char) (val)))
#define bfd_put_signed_8 \
bfd_put_8
#define bfd_get_8(abfd, ptr) \
(*(unsigned char *)(ptr))
(*(unsigned char *) (ptr))
#define bfd_get_signed_8(abfd, ptr) \
((*(unsigned char *)(ptr) ^ 0x80) - 0x80)
((*(unsigned char *) (ptr) ^ 0x80) - 0x80)
#define bfd_put_16(abfd, val, ptr) \
BFD_SEND(abfd, bfd_putx16, ((val),(ptr)))
@ -1495,8 +1495,11 @@ enum bfd_architecture
#define bfd_mach_v850 0
#define bfd_mach_v850e 'E'
#define bfd_mach_v850ea 'A'
bfd_arch_arc, /* Argonaut RISC Core */
#define bfd_mach_arc_base 0
bfd_arch_arc, /* ARC Cores */
#define bfd_mach_arc_5 0
#define bfd_mach_arc_6 1
#define bfd_mach_arc_7 2
#define bfd_mach_arc_8 3
bfd_arch_m32r, /* Mitsubishi M32R/D */
#define bfd_mach_m32r 0 /* backwards compatibility */
#define bfd_mach_m32rx 'x'
@ -2218,7 +2221,7 @@ be zero and is not stored in the instruction. */
BFD_RELOC_THUMB_PCREL_BRANCH12,
BFD_RELOC_THUMB_PCREL_BRANCH23,
/* Argonaut RISC Core (ARC) relocs.
/* ARC Cores relocs.
ARC 22 bit pc-relative branch. The lowest two bits must be zero and are
not stored in the instruction. The high 20 bits are installed in bits 26
through 7 of the instruction. */
@ -2407,13 +2410,13 @@ significant 9 bits of the opcode. */
/* This is an extended address 23-bit reloc for the tms320c54x. */
BFD_RELOC_TIC54X_23,
/* This is a 16-bit reloc for the tms320c54x, where the least
significant 16 bits of a 23-bit extended address are placed into
/* This is a 16-bit reloc for the tms320c54x, where the least
significant 16 bits of a 23-bit extended address are placed into
the opcode. */
BFD_RELOC_TIC54X_16_OF_23,
/* This is a reloc for the tms320c54x, where the most
significant 7 bits of a 23-bit extended address are placed into
significant 7 bits of a 23-bit extended address are placed into
the opcode. */
BFD_RELOC_TIC54X_MS7_OF_23,

27
bfd/cpu-arc.c
View File

@ -24,31 +24,31 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#define ARC(mach, print_name, default_p, next) \
{ \
32, /* 32 bits in a word */ \
32, /* 32 bits in an address */ \
8, /* 8 bits in a byte */ \
32, /* 32 bits in a word */ \
32, /* 32 bits in an address */ \
8, /* 8 bits in a byte */ \
bfd_arch_arc, \
mach, \
"arc", \
print_name, \
4, /* section alignment power */ \
4, /* section alignment power */ \
default_p, \
bfd_default_compatible, \
bfd_default_scan, \
next, \
}
#if 0 /* ??? Not currently needed, but keep in for future reference. */
static const bfd_arch_info_type arch_info_struct[] =
{
ARC (bfd_mach_arc_foo, "arc-foo", false, &arch_info_struct[1]),
ARC (bfd_mach_arc_bar, "arc-bar", false, 0),
ARC ( bfd_mach_arc_5, "arc5", false, &arch_info_struct[1] ),
ARC ( bfd_mach_arc_6, "arc6", false, &arch_info_struct[2] ),
ARC ( bfd_mach_arc_7, "arc7", false, &arch_info_struct[3] ),
ARC ( bfd_mach_arc_8, "arc8", false, NULL ),
};
#endif
const bfd_arch_info_type bfd_arc_arch =
ARC (bfd_mach_arc_base, "arc-base", true, 0 /*&arch_info_struct[0]*/);
ARC ( bfd_mach_arc_5, "arc", true, &arch_info_struct[0] );
/* Utility routines. */
/* Given cpu type NAME, return its bfd_mach_arc_xxx value.
@ -61,10 +61,7 @@ arc_get_mach (name)
const bfd_arch_info_type *p;
for (p = &bfd_arc_arch; p != NULL; p = p->next)
{
/* +4: skip over "arc-" */
if (strcmp (name, p->printable_name + 4) == 0)
return p->mach;
}
if (strcmp (name, p->printable_name) == 0)
return p->mach;
return -1;
}

221
bfd/elf32-arc.c
View File

@ -1,22 +1,22 @@
/* ARC-specific support for 32-bit ELF
Copyright (C) 1994, 1995, 1997, 1999 Free Software Foundation, Inc.
Copyright (C) 1994, 1995, 1997, 1999, 2000 Free Software Foundation, Inc.
Contributed by Doug Evans (dje@cygnus.com).
This file is part of BFD, the Binary File Descriptor library.
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#include "bfd.h"
#include "sysdep.h"
@ -25,77 +25,80 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#include "elf/arc.h"
static reloc_howto_type *bfd_elf32_bfd_reloc_type_lookup
PARAMS ((bfd *abfd, bfd_reloc_code_real_type code));
PARAMS ((bfd *abfd, bfd_reloc_code_real_type code));
static void arc_info_to_howto_rel
PARAMS ((bfd *, arelent *, Elf32_Internal_Rel *));
static boolean arc_elf_object_p PARAMS ((bfd *));
static void arc_elf_final_write_processing PARAMS ((bfd *, boolean));
static boolean arc_elf_object_p
PARAMS ((bfd *));
static void arc_elf_final_write_processing
PARAMS ((bfd *, boolean));
/* Try to minimize the amount of space occupied by relocation tables
on the ROM (not that the ROM won't be swamped by other ELF overhead). */
#define USE_REL
static reloc_howto_type elf_arc_howto_table[] =
{
/* This reloc does nothing. */
HOWTO (R_ARC_NONE, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
false, /* pc_relative */
0, /* bitpos */
complain_overflow_bitfield, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_ARC_NONE", /* name */
false, /* partial_inplace */
0, /* src_mask */
0, /* dst_mask */
false), /* pcrel_offset */
HOWTO (R_ARC_NONE, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
false, /* pc_relative */
0, /* bitpos */
complain_overflow_bitfield, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_ARC_NONE", /* name */
false, /* partial_inplace */
0, /* src_mask */
0, /* dst_mask */
false), /* pcrel_offset */
/* A standard 32 bit relocation. */
HOWTO (R_ARC_32, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
false, /* pc_relative */
0, /* bitpos */
complain_overflow_bitfield, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_ARC_32", /* name */
false, /* partial_inplace */
0xffffffff, /* src_mask */
0xffffffff, /* dst_mask */
false), /* pcrel_offset */
HOWTO (R_ARC_32, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
false, /* pc_relative */
0, /* bitpos */
complain_overflow_bitfield, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_ARC_32", /* name */
false, /* partial_inplace */
0xffffffff, /* src_mask */
0xffffffff, /* dst_mask */
false), /* pcrel_offset */
/* A 26 bit absolute branch, right shifted by 2. */
HOWTO (R_ARC_B26, /* type */
2, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
26, /* bitsize */
false, /* pc_relative */
0, /* bitpos */
complain_overflow_bitfield, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_ARC_B26", /* name */
false, /* partial_inplace */
0x00ffffff, /* src_mask */
0x00ffffff, /* dst_mask */
false), /* pcrel_offset */
HOWTO (R_ARC_B26, /* type */
2, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
26, /* bitsize */
false, /* pc_relative */
0, /* bitpos */
complain_overflow_bitfield, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_ARC_B26", /* name */
false, /* partial_inplace */
0x00ffffff, /* src_mask */
0x00ffffff, /* dst_mask */
false), /* pcrel_offset */
/* A relative 22 bit branch; bits 21-2 are stored in bits 26-7. */
HOWTO (R_ARC_B22_PCREL, /* type */
2, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
22, /* bitsize */
true, /* pc_relative */
7, /* bitpos */
complain_overflow_signed, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_ARC_B22_PCREL", /* name */
false, /* partial_inplace */
0x07ffff80, /* src_mask */
0x07ffff80, /* dst_mask */
true), /* pcrel_offset */
HOWTO (R_ARC_B22_PCREL, /* type */
2, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
22, /* bitsize */
true, /* pc_relative */
7, /* bitpos */
complain_overflow_signed, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_ARC_B22_PCREL", /* name */
false, /* partial_inplace */
0x07ffff80, /* src_mask */
0x07ffff80, /* dst_mask */
true), /* pcrel_offset */
};
@ -123,14 +126,11 @@ bfd_elf32_bfd_reloc_type_lookup (abfd, code)
{
unsigned int i;
for (i = 0;
i < sizeof (arc_reloc_map) / sizeof (struct arc_reloc_map);
i++)
for (i = 0; i < sizeof (arc_reloc_map) / sizeof (struct arc_reloc_map); i++)
{
if (arc_reloc_map[i].bfd_reloc_val == code)
return &elf_arc_howto_table[arc_reloc_map[i].elf_reloc_val];
}
return NULL;
}
@ -155,21 +155,30 @@ static boolean
arc_elf_object_p (abfd)
bfd *abfd;
{
int mach;
unsigned long arch = elf_elfheader (abfd)->e_flags & EF_ARC_MACH;
int mach = bfd_mach_arc_5;
switch (arch)
if (elf_elfheader(abfd)->e_machine == EM_ARC)
{
case E_ARC_MACH_BASE:
mach = bfd_mach_arc_base;
break;
default:
/* Unknown cpu type. ??? What to do? */
return false;
}
unsigned long arch = elf_elfheader (abfd)->e_flags & EF_ARC_MACH;
(void) bfd_default_set_arch_mach (abfd, bfd_arch_arc, mach);
return true;
switch (arch)
{
default:
case E_ARC_MACH_ARC5:
mach = bfd_mach_arc_5;
break;
case E_ARC_MACH_ARC6:
mach = bfd_mach_arc_6;
break;
case E_ARC_MACH_ARC7:
mach = bfd_mach_arc_7;
break;
case E_ARC_MACH_ARC8:
mach = bfd_mach_arc_8;
break;
}
}
return bfd_default_set_arch_mach (abfd, bfd_arch_arc, mach);
}
/* The final processing done just before writing out an ARC ELF object file.
@ -180,34 +189,40 @@ arc_elf_final_write_processing (abfd, linker)
bfd *abfd;
boolean linker ATTRIBUTE_UNUSED;
{
int mach;
unsigned long val;
switch (mach = bfd_get_mach (abfd))
switch (bfd_get_mach (abfd))
{
case bfd_mach_arc_base:
val = E_ARC_MACH_BASE;
break;
default:
return;
case bfd_mach_arc_5:
val = E_ARC_MACH_ARC5;
break;
case bfd_mach_arc_6:
val = E_ARC_MACH_ARC6;
break;
case bfd_mach_arc_7:
val = E_ARC_MACH_ARC7;
break;
case bfd_mach_arc_8:
val = E_ARC_MACH_ARC8;
break;
}
elf_elfheader (abfd)->e_machine = EM_ARC;
elf_elfheader (abfd)->e_flags &=~ EF_ARC_MACH;
elf_elfheader (abfd)->e_flags |= val;
}
#define TARGET_LITTLE_SYM bfd_elf32_littlearc_vec
#define TARGET_LITTLE_NAME "elf32-littlearc"
#define TARGET_BIG_SYM bfd_elf32_bigarc_vec
#define TARGET_BIG_NAME "elf32-bigarc"
#define ELF_ARCH bfd_arch_arc
#define ELF_MACHINE_CODE EM_CYGNUS_ARC
#define ELF_MAXPAGESIZE 0x1000
#define TARGET_LITTLE_SYM bfd_elf32_littlearc_vec
#define TARGET_LITTLE_NAME "elf32-littlearc"
#define TARGET_BIG_SYM bfd_elf32_bigarc_vec
#define TARGET_BIG_NAME "elf32-bigarc"
#define ELF_ARCH bfd_arch_arc
#define ELF_MACHINE_CODE EM_ARC
#define ELF_MAXPAGESIZE 0x1000
#define elf_info_to_howto 0
#define elf_info_to_howto_rel arc_info_to_howto_rel
#define elf_backend_object_p arc_elf_object_p
#define elf_backend_final_write_processing \
arc_elf_final_write_processing
#define elf_info_to_howto 0
#define elf_info_to_howto_rel arc_info_to_howto_rel
#define elf_backend_object_p arc_elf_object_p
#define elf_backend_final_write_processing arc_elf_final_write_processing
#include "elf32-target.h"

156
bfd/po/bfd.pot
View File

@ -6,7 +6,7 @@
msgid ""
msgstr ""
"Project-Id-Version: PACKAGE VERSION\n"
"POT-Creation-Date: 2000-12-21 10:38-0800\n"
"POT-Creation-Date: 2001-01-11 11:54-0800\n"
"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
"Language-Team: LANGUAGE <LL@li.org>\n"
@ -375,7 +375,7 @@ msgstr ""
msgid "uncertain calling convention for non-COFF symbol"
msgstr ""
#: cofflink.c:526 elflink.h:1649
#: cofflink.c:526 elflink.h:1648
#, c-format
msgid "Warning: type of symbol `%s' changed from %d to %d in %s"
msgstr ""
@ -1276,7 +1276,7 @@ msgstr ""
msgid "%s: unsupported relocation type %s"
msgstr ""
#: elfcode.h:1076
#: elfcode.h:1084
#, c-format
msgid "%s: version count (%ld) does not match symbol count (%ld)"
msgstr ""
@ -1286,37 +1286,37 @@ msgstr ""
msgid "%s: Section %s is already to large to put hole of %ld bytes in"
msgstr ""
#: elflink.h:1466
#: elflink.h:1465
#, c-format
msgid "%s: %s: invalid version %u (max %d)"
msgstr ""
#: elflink.h:1507
#: elflink.h:1506
#, c-format
msgid "%s: %s: invalid needed version %d"
msgstr ""
#: elflink.h:1627
#: elflink.h:1626
#, c-format
msgid "Warning: size of symbol `%s' changed from %lu to %lu in %s"
msgstr ""
#: elflink.h:1873
#: elflink.h:1872
#, c-format
msgid "%s: warning: unexpected redefinition of `%s'"
msgstr ""
#: elflink.h:3660
#: elflink.h:3659
#, c-format
msgid "warning: type and size of dynamic symbol `%s' are not defined"
msgstr ""
#: elflink.h:3932
#: elflink.h:3931
#, c-format
msgid "%s: undefined versioned symbol name %s"
msgstr ""
#: elflink.h:5181
#: elflink.h:5180
#, c-format
msgid "%s: could not find output section %s for input section %s"
msgstr ""
@ -1416,26 +1416,26 @@ msgstr ""
msgid "%s: address 0x%s out of range for Intex Hex file"
msgstr ""
#: libbfd.c:484
#: libbfd.c:471
#, c-format
msgid "not mapping: data=%lx mapped=%d\n"
msgstr ""
#: libbfd.c:487
#: libbfd.c:474
msgid "not mapping: env var not set\n"
msgstr ""
#: libbfd.c:1383
#: libbfd.c:1370
#, c-format
msgid "%s: compiled for a big endian system and target is little endian"
msgstr ""
#: libbfd.c:1385
#: libbfd.c:1372
#, c-format
msgid "%s: compiled for a little endian system and target is big endian"
msgstr ""
#: linker.c:2679
#: linker.c:2678
#, c-format
msgid "Attempt to do relocateable link with %s input and %s output"
msgstr ""
@ -1451,39 +1451,39 @@ msgid "Unhandled OSF/1 core file section type %d\n"
msgstr ""
#. XXX code yet to be written.
#: peicode.h:809
#: peicode.h:807
#, c-format
msgid "%s: Unhandled import type; %x"
msgstr ""
#: peicode.h:814
#: peicode.h:812
#, c-format
msgid "%s: Unrecognised import type; %x"
msgstr ""
#: peicode.h:828
#: peicode.h:826
#, c-format
msgid "%s: Unrecognised import name type; %x"
msgstr ""
#: peicode.h:1185
#: peicode.h:1183
#, c-format
msgid "%s: Unrecognised machine type (0x%x) in Import Library Format archive"
msgstr ""
#: peicode.h:1197
#: peicode.h:1195
#, c-format
msgid ""
"%s: Recognised but unhandled machine type (0x%x) in Import Library Format "
"archive"
msgstr ""
#: peicode.h:1214
#: peicode.h:1212
#, c-format
msgid "%s: size field is zero in Import Library Format header"
msgstr ""
#: peicode.h:1242
#: peicode.h:1240
#, c-format
msgid "%s: string not null terminated in ILF object file."
msgstr ""
@ -1787,7 +1787,7 @@ msgid ""
"Characteristics 0x%x\n"
msgstr ""
#: pe-mips.c:657
#: pe-mips.c:653
#, c-format
msgid "%s: `ld -r' not supported with PE MIPS objects\n"
msgstr ""
@ -1797,17 +1797,17 @@ msgstr ""
#. mem = pointer to memory we're fixing up
#. val = VMA of what we need to refer to
#.
#: pe-mips.c:794
#: pe-mips.c:789
#, c-format
msgid "%s: unimplemented %s\n"
msgstr ""
#: pe-mips.c:820
#: pe-mips.c:815
#, c-format
msgid "%s: jump too far away\n"
msgstr ""
#: pe-mips.c:847
#: pe-mips.c:842
#, c-format
msgid "%s: bad pair/reflo after refhi\n"
msgstr ""
@ -1860,7 +1860,7 @@ msgstr ""
msgid "Partition[%d] length = 0x%.8lx (%ld)\n"
msgstr ""
#: som.c:5365
#: som.c:5355
msgid "som_sizeof_headers unimplemented"
msgstr ""
@ -1873,149 +1873,149 @@ msgstr ""
msgid "Unsupported .stab relocation"
msgstr ""
#: vms-gsd.c:357
#: vms-gsd.c:354
#, c-format
msgid "bfd_make_section (%s) failed"
msgstr ""
#: vms-gsd.c:371
#: vms-gsd.c:368
#, c-format
msgid "bfd_set_section_flags (%s, %x) failed"
msgstr ""
#: vms-gsd.c:407
#: vms-gsd.c:404
#, c-format
msgid "Size mismatch section %s=%lx, %s=%lx"
msgstr ""
#: vms-gsd.c:702
#: vms-gsd.c:699
#, c-format
msgid "unknown gsd/egsd subtype %d"
msgstr ""
#: vms-hdr.c:408
#: vms-hdr.c:403
msgid "Object module NOT error-free !\n"
msgstr ""
#: vms-misc.c:545
#: vms-misc.c:539
#, c-format
msgid "Stack overflow (%d) in _bfd_vms_push"
msgstr ""
#: vms-misc.c:564
#: vms-misc.c:557
msgid "Stack underflow in _bfd_vms_pop"
msgstr ""
#: vms-misc.c:935
#: vms-misc.c:915
msgid "_bfd_vms_output_counted called with zero bytes"
msgstr ""
#: vms-misc.c:940
#: vms-misc.c:920
msgid "_bfd_vms_output_counted called with too many bytes"
msgstr ""
#: vms-misc.c:1073
#: vms-misc.c:1051
#, c-format
msgid "Symbol %s replaced by %s\n"
msgstr ""
#: vms-misc.c:1137
#: vms-misc.c:1113
#, c-format
msgid "failed to enter %s"
msgstr ""
#: vms-tir.c:69
#: vms-tir.c:68
msgid "No Mem !"
msgstr ""
#: vms-tir.c:309
#: vms-tir.c:302
msgid "Bad section index in ETIR_S_C_STA_PQ"
msgstr ""
#: vms-tir.c:324
#: vms-tir.c:317
#, c-format
msgid "Unsupported STA cmd %d"
msgstr ""
#: vms-tir.c:329 vms-tir.c:1287
#: vms-tir.c:322 vms-tir.c:1274
#, c-format
msgid "Reserved STA cmd %d"
msgstr ""
#: vms-tir.c:436
#: vms-tir.c:428
#, c-format
msgid "ETIR_S_C_STO_GBL: no symbol \"%s\""
msgstr ""
#: vms-tir.c:457
#: vms-tir.c:449
#, c-format
msgid "ETIR_S_C_STO_CA: no symbol \"%s\""
msgstr ""
#: vms-tir.c:470
#: vms-tir.c:462
msgid "ETIR_S_C_STO_RB/AB: Not supported"
msgstr ""
#: vms-tir.c:528
#: vms-tir.c:520
msgid "ETIR_S_C_STO_LP_PSB: Not supported"
msgstr ""
#: vms-tir.c:534
#: vms-tir.c:526
msgid "ETIR_S_C_STO_HINT_GBL: not implemented"
msgstr ""
#: vms-tir.c:540
#: vms-tir.c:532
msgid "ETIR_S_C_STO_HINT_PS: not implemented"
msgstr ""
#: vms-tir.c:544 vms-tir.c:1460
#: vms-tir.c:536 vms-tir.c:1446
#, c-format
msgid "Reserved STO cmd %d"
msgstr ""
#: vms-tir.c:657
#: vms-tir.c:649
msgid "ETIR_S_C_OPR_INSV: Not supported"
msgstr ""
#: vms-tir.c:675
#: vms-tir.c:667
msgid "ETIR_S_C_OPR_USH: Not supported"
msgstr ""
#: vms-tir.c:681
#: vms-tir.c:673
msgid "ETIR_S_C_OPR_ROT: Not supported"
msgstr ""
#: vms-tir.c:700
#: vms-tir.c:692
msgid "ETIR_S_C_OPR_REDEF: Not supported"
msgstr ""
#: vms-tir.c:706
#: vms-tir.c:698
msgid "ETIR_S_C_OPR_DFLIT: Not supported"
msgstr ""
#: vms-tir.c:710 vms-tir.c:1656
#: vms-tir.c:702 vms-tir.c:1641
#, c-format
msgid "Reserved OPR cmd %d"
msgstr ""
#: vms-tir.c:779 vms-tir.c:1726
#: vms-tir.c:770 vms-tir.c:1710
#, c-format
msgid "Reserved CTL cmd %d"
msgstr ""
#: vms-tir.c:808
#: vms-tir.c:798
msgid "ETIR_S_C_STC_LP: not supported"
msgstr ""
#: vms-tir.c:826
#: vms-tir.c:816
msgid "ETIR_S_C_STC_GBL: not supported"
msgstr ""
#: vms-tir.c:834
#: vms-tir.c:824
msgid "ETIR_S_C_STC_GCA: not supported"
msgstr ""
#: vms-tir.c:843
#: vms-tir.c:833
msgid "ETIR_S_C_STC_PS: not supported"
msgstr ""
@ -2024,11 +2024,11 @@ msgstr ""
#. * arg: -
#. *
#.
#: vms-tir.c:1187
#: vms-tir.c:1174
msgid "Stack-from-image not implemented"
msgstr ""
#: vms-tir.c:1207
#: vms-tir.c:1194
msgid "Stack-entry-mask not fully implemented"
msgstr ""
@ -2041,76 +2041,76 @@ msgstr ""
#. * compare argument descriptor with symbol argument (ARG$V_PASSMECH)
#. * and stack TRUE (args match) or FALSE (args dont match) value
#.
#: vms-tir.c:1223
#: vms-tir.c:1210
msgid "PASSMECH not fully implemented"
msgstr ""
#: vms-tir.c:1243
#: vms-tir.c:1230
msgid "Stack-local-symbol not fully implemented"
msgstr ""
#: vms-tir.c:1258
#: vms-tir.c:1245
msgid "Stack-literal not fully implemented"
msgstr ""
#: vms-tir.c:1280
#: vms-tir.c:1267
msgid "Stack-local-symbol-entry-point-mask not fully implemented"
msgstr ""
#: vms-tir.c:1456
#: vms-tir.c:1442
#, c-format
msgid "Unimplemented STO cmd %d"
msgstr ""
#: vms-tir.c:1596
#: vms-tir.c:1581
msgid "TIR_S_C_OPR_ASH incomplete"
msgstr ""
#: vms-tir.c:1610
#: vms-tir.c:1595
msgid "TIR_S_C_OPR_USH incomplete"
msgstr ""
#: vms-tir.c:1624
#: vms-tir.c:1609
msgid "TIR_S_C_OPR_ROT incomplete"
msgstr ""
#.
#. * redefine symbol to current location
#.
#: vms-tir.c:1645
#: vms-tir.c:1630
msgid "TIR_S_C_OPR_REDEF not supported"
msgstr ""
#.
#. * define a literal
#.
#: vms-tir.c:1652
#: vms-tir.c:1637
msgid "TIR_S_C_OPR_DFLIT not supported"
msgstr ""
#: vms-tir.c:1707
#: vms-tir.c:1691
msgid "TIR_S_C_CTL_DFLOC not fully implemented"
msgstr ""
#: vms-tir.c:1715
#: vms-tir.c:1699
msgid "TIR_S_C_CTL_STLOC not fully implemented"
msgstr ""
#: vms-tir.c:1723
#: vms-tir.c:1707
msgid "TIR_S_C_CTL_STKDL not fully implemented"
msgstr ""
#: vms-tir.c:1778
#: vms-tir.c:1761
#, c-format
msgid "Obj code %d not found"
msgstr ""
#: vms-tir.c:2127
#: vms-tir.c:2102
#, c-format
msgid "SEC_RELOC with no relocs in section %s"
msgstr ""
#: vms-tir.c:2401
#: vms-tir.c:2376
#, c-format
msgid "Unhandled relocation %s"
msgstr ""

2
bfd/reloc.c
View File

@ -2336,7 +2336,7 @@ ENUMDOC
ENUM
BFD_RELOC_ARC_B22_PCREL
ENUMDOC
Argonaut RISC Core (ARC) relocs.
ARC Cores relocs.
ARC 22 bit pc-relative branch. The lowest two bits must be zero and are
not stored in the instruction. The high 20 bits are installed in bits 26
through 7 of the instruction.

5
binutils/ChangeLog
View File

@ -1,3 +1,8 @@
2001-01-11 Peter Targett <peter.targett@arccores.com>
* readelf.c (dump_relocations): Include selection with EM_ARC.
(get_machine_name) Update name to "ARC".
2001-01-09 Nick Clifton <nickc@redhat.com>
* Makefile.am: Add rule to build objdump.o from objdump.c and

2
binutils/po/binutils.pot
View File

@ -6,7 +6,7 @@
msgid ""
msgstr ""
"Project-Id-Version: PACKAGE VERSION\n"
"POT-Creation-Date: 2001-01-09 12:08-0800\n"
"POT-Creation-Date: 2001-01-11 12:02-0800\n"
"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
"Language-Team: LANGUAGE <LL@li.org>\n"

28
gas/ChangeLog
View File

@ -1,3 +1,31 @@
2001-01-11 Peter Targett <peter.targett@arccores.com>
* as.h (TC_ARC): Ensure struc-symbol.h included.
* as.c (dwarf2dbg.h): Include to remove implicit declaration
warnings.
* struc-symbol.h (SYMBOLS_NEED_BACKPOINTERS): Define.
(TARGET_SYMBOL_FIELDS) added.
* doc/Makefile.am (CPU_DOCS): Added c-arc.texi.
* doc/c-arc.texi: New file.
Some sections to be expanded.
* doc/as.texinfo: Update command-line options.
Removed outdated text for ARC dependant features, instead include
text from above file.
* config/obj-elf.h (ELF_TARGET_SYMBOL_FIELDS): Define local flag.
(TARGET_SYMBOL_FIELDS): Alias to previous definition.
(targ-cpu.h) header.
* config/tc-arc.h:
* config/tc-arc.c: New updated configuration for
ARC, including selection of core variants, and extensibility of
instructions, registers etc. through directives.
* config/tc-arc.c (arc_extinst): Minor corrections for
error messages.
(arc_common) Likewise. Make alignment argument optional for local
symbols also, with default of zero.
2001-01-11 Stephane Carrez <Stephane.Carrez@worldnet.fr>
* config/tc-m68hc11.c (md_estimate_size_before_relax): Fix

4
gas/as.h
View File

@ -622,6 +622,10 @@ void eh_frame_convert_frag PARAMS ((fragS *));
/* this one starts the chain of target dependant headers */
#include "targ-env.h"
#ifdef TC_ARC
#include "struc-symbol.h"
#endif
#include "write.h"
#include "frags.h"
#include "hash.h"

8
gas/config/obj-elf.h
View File

@ -85,6 +85,14 @@ struct elf_obj_sy
#define OBJ_SYMFIELD_TYPE struct elf_obj_sy
/* Symbol fields used by the ELF back end. */
#define ELF_TARGET_SYMBOL_FIELDS int local:1;
/* Don't change this; change ELF_TARGET_SYMBOL_FIELDS instead. */
#define TARGET_SYMBOL_FIELDS ELF_TARGET_SYMBOL_FIELDS
/* #include "targ-cpu.h" */
#ifndef FALSE
#define FALSE 0
#define TRUE !FALSE

1274
gas/config/tc-arc.c
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File diff suppressed because it is too large Load Diff

23
gas/config/tc-arc.h
View File

@ -1,5 +1,5 @@
/* tc-arc.h - Macros and type defines for the ARC.
Copyright (C) 1994, 1995, 1997, 1999, 2000 Free Software Foundation, Inc.
Copyright (C) 1994, 1995, 1997 Free Software Foundation, Inc.
Contributed by Doug Evans (dje@cygnus.com).
This file is part of GAS, the GNU Assembler.
@ -17,7 +17,7 @@
You should have received a copy of the GNU General Public License
along with GAS; see the file COPYING. If not, write to the Free
Software Foundation, 59 Temple Place - Suite 330, Boston, MA
02111-1307, USA. */
02111-1307, USA. */
#define TC_ARC 1
@ -27,6 +27,9 @@
#define TARGET_ARCH bfd_arch_arc
#define DIFF_EXPR_OK
#define REGISTER_PREFIX '%'
#ifdef LITTLE_ENDIAN
#undef LITTLE_ENDIAN
#endif
@ -36,6 +39,7 @@
#endif
#define LITTLE_ENDIAN 1234
#define BIG_ENDIAN 4321
/* The endianness of the target format may change based on command
@ -62,18 +66,3 @@ arc_parse_cons_expression (EXP, NBYTES)
extern void arc_cons_fix_new ();
#define TC_CONS_FIX_NEW(FRAG, WHERE, NBYTES, EXP) \
arc_cons_fix_new (FRAG, WHERE, NBYTES, EXP)
#if 0
/* Extra stuff that we need to keep track of for each symbol. */
struct arc_tc_sy
{
/* The real name, if the symbol was renamed. */
char *real_name;
};
#define TC_SYMFIELD_TYPE struct arc_tc_sy
/* Finish up the symbol. */
extern int arc_frob_symbol PARAMS ((symbolS *));
#define tc_frob_symbol(sym, punt) punt = arc_frob_symbol (sym)
#endif

1
gas/doc/Makefile.am
View File

@ -17,6 +17,7 @@ asconfig.texi: $(CONFIG).texi
CPU_DOCS = \
c-a29k.texi \
c-arc.texi \
c-arm.texi \
c-d10v.texi \
c-h8300.texi \

1
gas/doc/Makefile.in
View File

@ -127,6 +127,7 @@ info_TEXINFOS = as.texinfo gasp.texi
CPU_DOCS = \
c-a29k.texi \
c-arc.texi \
c-arm.texi \
c-d10v.texi \
c-h8300.texi \

93
gas/doc/as.texinfo
View File

@ -208,7 +208,8 @@ Here is a brief summary of how to invoke @code{@value{AS}}. For details,
@c am29k has no machine-dependent assembler options
@end ifset
@ifset ARC
[ -mbig-endian | -mlittle-endian ]
[ -marc[5|6|7|8] ]
[ -EB | -EL ]
@end ifset
@ifset ARM
[ -m[arm]1 | -m[arm]2 | -m[arm]250 | -m[arm]3 | -m[arm]6 | -m[arm]60 |
@ -416,17 +417,10 @@ The following options are available when @value{AS} is configured for
an ARC processor.
@table @code
@cindex ARC endianness
@cindex endianness, ARC
@cindex big endian output, ARC
@item -mbig-endian
Generate ``big endian'' format output.
@cindex little endian output, ARC
@item -mlittle-endian
Generate ``little endian'' format output.
@item -marc[5|6|7|8]
This option selects the core processor variant.
@item -EB | -EL
Select either big-endian (-EB) or little-endian (-EL) output.
@end table
@end ifset
@ -5302,80 +5296,7 @@ subject, see the hardware manufacturer's manual.
@c in both conditional blocks.
@ifset ARC
@ifset GENERIC
@page
@node ARC-Dependent
@chapter ARC Dependent Features
@end ifset
@ifclear GENERIC
@node Machine Dependencies
@chapter ARC Dependent Features
@end ifclear
@cindex ARC support
@menu
* ARC-Opts:: Options
* ARC-Float:: Floating Point
* ARC-Directives:: Sparc Machine Directives
@end menu
@node ARC-Opts
@section Options
@cindex options for ARC
@cindex ARC options
@cindex architectures, ARC
@cindex ARC architectures
The ARC chip family includes several successive levels (or other
variants) of chip, using the same core instruction set, but including
a few additional instructions at each level.
By default, @code{@value{AS}} assumes the core instruction set (ARC
base). The @code{.cpu} pseudo-op is intended to be used to select
the variant.
@table @code
@cindex @code{-mbig-endian} option (ARC)
@cindex @code{-mlittle-endian} option (ARC)
@cindex ARC big-endian output
@cindex ARC little-endian output
@cindex big-endian output, ARC
@cindex little-endian output, ARC
@item -mbig-endian
@itemx -mlittle-endian
Any @sc{arc} configuration of @code{@value{AS}} can select big-endian or
little-endian output at run time (unlike most other @sc{gnu} development
tools, which must be configured for one or the other). Use
@samp{-mbig-endian} to select big-endian output, and @samp{-mlittle-endian}
for little-endian.
@end table
@node ARC-Float
@section Floating Point
@cindex floating point, ARC (@sc{ieee})
@cindex ARC floating point (@sc{ieee})
The ARC cpu family currently does not have hardware floating point
support. Software floating point support is provided by @code{GCC}
and uses @sc{ieee} floating-point numbers.
@node ARC-Directives
@section ARC Machine Directives
@cindex ARC machine directives
@cindex machine directives, ARC
The ARC version of @code{@value{AS}} supports the following additional
machine directives:
@table @code
@item .cpu
@cindex @code{cpu} directive, SPARC
This must be followed by the desired cpu.
The ARC is intended to be customizable, @code{.cpu} is used to
select the desired variant [though currently there are none].
@end table
@include c-arc.texi
@end ifset
@ifset A29K

1309
gas/po/gas.pot
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File diff suppressed because it is too large Load Diff

10
gas/struc-symbol.h
View File

@ -22,6 +22,12 @@
#ifndef __struc_symbol_h__
#define __struc_symbol_h__
#ifdef BFD_ASSEMBLER
/* The BFD code wants to walk the list in both directions. */
#undef SYMBOLS_NEED_BACKPOINTERS
#define SYMBOLS_NEED_BACKPOINTERS
#endif
/* The information we keep for a symbol. Note that the symbol table
holds pointers both to this and to local_symbol structures. See
below. */
@ -89,6 +95,10 @@ struct symbol
#ifdef TC_SYMFIELD_TYPE
TC_SYMFIELD_TYPE sy_tc;
#endif
#ifdef TARGET_SYMBOL_FIELDS
TARGET_SYMBOL_FIELDS
#endif
};
#ifdef BFD_ASSEMBLER

50
gas/testsuite/ChangeLog
View File

@ -1,3 +1,53 @@
2001-01-11 Peter Targett <peter.targett@arccores.com>
* gas/arc/alias.*: Removed.
* gas/arc/branch.*: Likewise.
* gas/arc/insn3.*: Likewise.
* gas/arc/math.*: Likewise.
* gas/arc/sshift.*: Likewise.
* gas/arc/arc.exp: Simplified test process for base case
instruction set by adding run_dump_test cases for all base
instructions.
* gas/arc/adc.s, gas/arc/adc.d: New test cases and dump.
* gas/arc/add.s, gas/arc/add.d: Likewise.
* gas/arc/and.s, gas/arc/and.d: Likewise.
* gas/arc/asl.s, gas/arc/asl.d: Likewise.
* gas/arc/asr.s, gas/arc/asr.d: Likewise.
* gas/arc/b.s, gas/arc/b.d: Likewise.
* gas/arc/bic.s, gas/arc/bic.d: Likewise.
* gas/arc/bl.s, gas/arc/bl.d: Likewise.
* gas/arc/brk.s, gas/arc/brk.d: Likewise.
* gas/arc/extb.s, gas/arc/extb.d: Likewise.
* gas/arc/extw.s, gas/arc/extw.d: Likewise.
* gas/arc/flag.s, gas/arc/flag.d: Likewise.
* gas/arc/j.s, gas/arc/j.d: Likewise.
* gas/arc/jl.s, gas/arc/jl.d: Likewise.
* gas/arc/ld.s, gas/arc/ld.d: Likewise.
* gas/arc/ld2.s, gas/arc/ld2.d: Likewise.
* gas/arc/lp.s, gas/arc/lp.d: Likewise.
* gas/arc/lsr.s, gas/arc/lsr.d: Likewise.
* gas/arc/mov.s, gas/arc/mov.d: Likewise.
* gas/arc/nop.s, gas/arc/nop.d: Likewise.
* gas/arc/or.s, gas/arc/or.d: Likewise.
* gas/arc/rlc.s, gas/arc/rlc.d: Likewise.
* gas/arc/ror.s, gas/arc/ror.d: Likewise.
* gas/arc/rrc.s, gas/arc/rrc.d: Likewise.
* gas/arc/sbc.s, gas/arc/sbc.d: Likewise.
* gas/arc/sexb.s, gas/arc/sexb.d: Likewise.
* gas/arc/sexw.s, gas/arc/sexw.d: Likewise.
* gas/arc/sleep.s, gas/arc/sleep.d: Likewise.
* gas/arc/add.s, gas/arc/add.d: Likewise.
* gas/arc/st.s, gas/arc/st.d: Likewise.
* gas/arc/sub.s, gas/arc/sub.d: Likewise.
* gas/arc/swi.s, gas/arc/swi.d: Likewise.
* gas/arc/xor.s, gas/arc/xor.d: Likewise.
* gas/arc/warn.s: Removed warning test case for setting of flags
followed by conditional branch, an arc5 only feature.
* gas/ieee-fp/x930509a.exp: Skip test if target also arc*-*-*.
* gas/vtable/vtable.exp: Skip tests if target also arc*-*-*.
2001-01-11 Stephane Carrez <Stephane.Carrez@worldnet.fr>
* gas/m68hc11/opers12.s: Add more tests for index post byte.

85
gas/testsuite/gas/arc/adc.d Normal file
View File

@ -0,0 +1,85 @@
#as: -EL
#objdump: -dr -EL
.*: +file format elf32-.*arc
Disassembly of section .text:
00000000 <.text>:
0: 00 84 00 48 48008400 adc r0,r1,r2
4: 00 b8 4d 4b 4b4db800 adc gp,fp,sp
8: 00 3e af 4b 4baf3e00 adc ilink1,ilink2,blink
c: 00 f8 1d 4f 4f1df800 adc r56,r59,lp_count
10: 00 fe 00 48 4800fe00 adc r0,r1,0
14: 00 84 1f 48 481f8400 adc r0,0,r2
18: 00 84 e0 4f 4fe08400 adc 0,r1,r2
1c: ff ff 00 48 4800ffff adc r0,r1,-1
20: ff 85 1f 48 481f85ff adc r0,-1,r2
24: 00 84 e0 4f 4fe08400 adc 0,r1,r2
28: ff fe 00 48 4800feff adc r0,r1,255
2c: ff 84 1f 48 481f84ff adc r0,255,r2
30: 00 84 e0 4f 4fe08400 adc 0,r1,r2
34: 00 ff 00 48 4800ff00 adc r0,r1,-256
38: 00 85 1f 48 481f8500 adc r0,-256,r2
3c: 00 84 e0 4f 4fe08400 adc 0,r1,r2
40: 00 fc 00 48 4800fc00 adc r0,r1,0x100
44: 00 01 00 00
48: 00 04 1f 48 481f0400 adc r0,0xffff_feff,r2
4c: ff fe ff ff
50: ff fc 1f 48 481ffcff adc r0,255,0x100
54: 00 01 00 00
58: ff 7e 1f 48 481f7eff adc r0,0x100,255
5c: 00 01 00 00
60: 00 fc 00 48 4800fc00 adc r0,r1,0
64: 00 00 00 00
64: R_ARC_32 foo
68: 00 84 00 48 48008400 adc r0,r1,r2
6c: 00 0a 62 48 48620a00 adc r3,r4,r5
70: 01 90 c3 48 48c39001 adc.z r6,r7,r8
74: 01 16 25 49 49251601 adc.z r9,r10,r11
78: 02 9c 86 49 49869c02 adc.nz r12,r13,r14
7c: 02 22 e8 49 49e82202 adc.nz r15,r16,r17
80: 03 a8 49 4a 4a49a803 adc.p r18,r19,r20
84: 03 2e ab 4a 4aab2e03 adc.p r21,r22,r23
88: 04 b4 0c 4b 4b0cb404 adc.n r24,r25,gp
8c: 04 3a 6e 4b 4b6e3a04 adc.n fp,sp,ilink1
90: 05 c0 cf 4b 4bcfc005 adc.c ilink2,blink,r32
94: 05 46 31 4c 4c314605 adc.c r33,r34,r35
98: 05 cc 92 4c 4c92cc05 adc.c r36,r37,r38
9c: 06 52 f4 4c 4cf45206 adc.nc r39,r40,r41
a0: 06 d8 55 4d 4d55d806 adc.nc r42,r43,r44
a4: 06 5e b7 4d 4db75e06 adc.nc r45,r46,r47
a8: 07 e4 18 4e 4e18e407 adc.v r48,r49,r50
ac: 07 6a 1a 4f 4f1a6a07 adc.v r56,r52,r53
b0: 08 f0 1b 4f 4f1bf008 adc.nv r56,r55,r56
b4: 08 76 1d 4f 4f1d7608 adc.nv r56,r58,r59
b8: 09 00 9e 4f 4f9e0009 adc.gt lp_count,lp_count,r0
bc: 0a 7c 00 48 48007c0a adc.ge r0,r0,0
c0: 00 00 00 00
c4: 0b 02 3f 48 483f020b adc.lt r1,1,r1
c8: 01 00 00 00
cc: 0d 06 7f 48 487f060d adc.hi r3,3,r3
d0: 03 00 00 00
d4: 0e 08 df 4f 4fdf080e adc.ls 0,4,r4
d8: 04 00 00 00
dc: 0f fc c2 4f 4fc2fc0f adc.pnz 0,r5,5
e0: 05 00 00 00
e4: 00 85 00 48 48008500 adc.f r0,r1,r2
e8: 01 fa 00 48 4800fa01 adc.f r0,r1,1
ec: 01 84 1e 48 481e8401 adc.f r0,1,r2
f0: 00 85 e0 4f 4fe08500 adc.f 0,r1,r2
f4: 00 fd 00 48 4800fd00 adc.f r0,r1,0x200
f8: 00 02 00 00
fc: 00 05 1f 48 481f0500 adc.f r0,0x200,r2
100: 00 02 00 00
104: 01 85 00 48 48008501 adc.z.f r0,r1,r2
108: 02 fd 00 48 4800fd02 adc.nz.f r0,r1,0
10c: 00 00 00 00
110: 0b 05 1f 48 481f050b adc.lt.f r0,0,r2
114: 00 00 00 00
118: 09 85 c0 4f 4fc08509 adc.gt.f 0,r1,r2
11c: 00 00 00 00 00000000
120: 0c fd 00 48 4800fd0c adc.le.f r0,r1,0x200
124: 00 02 00 00
128: 0a 05 1f 48 481f050a adc.ge.f r0,0x200,r2
12c: 00 02 00 00

68
gas/testsuite/gas/arc/adc.s Normal file
View File

@ -0,0 +1,68 @@
# adc test
adc r0,r1,r2
adc r26,fp,sp
adc ilink1,ilink2,blink
adc r56,r59,lp_count
adc r0,r1,0
adc r0,0,r2
adc 0,r1,r2
adc r0,r1,-1
adc r0,-1,r2
adc -1,r1,r2
adc r0,r1,255
adc r0,255,r2
adc 255,r1,r2
adc r0,r1,-256
adc r0,-256,r2
adc -256,r1,r2
adc r0,r1,256
adc r0,-257,r2
adc r0,255,256
adc r0,256,255
adc r0,r1,foo
adc.al r0,r1,r2
adc.ra r3,r4,r5
adc.eq r6,r7,r8
adc.z r9,r10,r11
adc.ne r12,r13,r14
adc.nz r15,r16,r17
adc.pl r18,r19,r20
adc.p r21,r22,r23
adc.mi r24,r25,r26
adc.n r27,r28,r29
adc.cs r30,r31,r32
adc.c r33,r34,r35
adc.lo r36,r37,r38
adc.cc r39,r40,r41
adc.nc r42,r43,r44
adc.hs r45,r46,r47
adc.vs r48,r49,r50
adc.v r56,r52,r53
adc.vc r56,r55,r56
adc.nv r56,r58,r59
adc.gt r60,r60,r0
adc.ge r0,r0,0
adc.lt r1,1,r1
adc.hi r3,3,r3
adc.ls 4,4,r4
adc.pnz 5,r5,5
adc.f r0,r1,r2
adc.f r0,r1,1
adc.f r0,1,r2
adc.f 0,r1,r2
adc.f r0,r1,512
adc.f r0,512,r2
adc.eq.f r0,r1,r2
adc.ne.f r0,r1,0
adc.lt.f r0,0,r2
adc.gt.f 0,r1,r2
adc.le.f r0,r1,512
adc.ge.f r0,512,r2

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#as: -EL
#objdump: -dr -EL
.*: +file format elf32-.*arc
Disassembly of section .text:
00000000 <.text>:
0: 00 84 00 40 40008400 add r0,r1,r2
4: 00 b8 4d 43 434db800 add gp,fp,sp
8: 00 3e af 43 43af3e00 add ilink1,ilink2,blink
c: 00 f8 1d 47 471df800 add r56,r59,lp_count
10: 00 fe 00 40 4000fe00 add r0,r1,0
14: 00 84 1f 40 401f8400 add r0,0,r2
18: 00 84 e0 47 47e08400 add 0,r1,r2
1c: ff ff 00 40 4000ffff add r0,r1,-1
20: ff 85 1f 40 401f85ff add r0,-1,r2
24: 00 84 e0 47 47e08400 add 0,r1,r2
28: ff fe 00 40 4000feff add r0,r1,255
2c: ff 84 1f 40 401f84ff add r0,255,r2
30: 00 84 e0 47 47e08400 add 0,r1,r2
34: 00 ff 00 40 4000ff00 add r0,r1,-256
38: 00 85 1f 40 401f8500 add r0,-256,r2
3c: 00 84 e0 47 47e08400 add 0,r1,r2
40: 00 fc 00 40 4000fc00 add r0,r1,0x100
44: 00 01 00 00
48: 00 04 1f 40 401f0400 add r0,0xffff_feff,r2
4c: ff fe ff ff
50: ff fc 1f 40 401ffcff add r0,255,0x100
54: 00 01 00 00
58: ff 7e 1f 40 401f7eff add r0,0x100,255
5c: 00 01 00 00
60: 00 fc 00 40 4000fc00 add r0,r1,0
64: 00 00 00 00
64: R_ARC_32 foo
68: 00 84 00 40 40008400 add r0,r1,r2
6c: 00 0a 62 40 40620a00 add r3,r4,r5
70: 01 90 c3 40 40c39001 add.z r6,r7,r8
74: 01 16 25 41 41251601 add.z r9,r10,r11
78: 02 9c 86 41 41869c02 add.nz r12,r13,r14
7c: 02 22 e8 41 41e82202 add.nz r15,r16,r17
80: 03 a8 49 42 4249a803 add.p r18,r19,r20
84: 03 2e ab 42 42ab2e03 add.p r21,r22,r23
88: 04 b4 0c 43 430cb404 add.n r24,r25,gp
8c: 04 3a 6e 43 436e3a04 add.n fp,sp,ilink1
90: 05 c0 cf 43 43cfc005 add.c ilink2,blink,r32
94: 05 46 31 44 44314605 add.c r33,r34,r35
98: 05 cc 92 44 4492cc05 add.c r36,r37,r38
9c: 06 52 f4 44 44f45206 add.nc r39,r40,r41
a0: 06 d8 55 45 4555d806 add.nc r42,r43,r44
a4: 06 5e b7 45 45b75e06 add.nc r45,r46,r47
a8: 07 e4 18 46 4618e407 add.v r48,r49,r50
ac: 07 6a 1a 47 471a6a07 add.v r56,r52,r53
b0: 08 f0 1b 47 471bf008 add.nv r56,r55,r56
b4: 08 76 1d 47 471d7608 add.nv r56,r58,r59
b8: 09 00 9e 47 479e0009 add.gt lp_count,lp_count,r0
bc: 0a 7c 00 40 40007c0a add.ge r0,r0,0
c0: 00 00 00 00
c4: 0b 02 3f 40 403f020b add.lt r1,1,r1
c8: 01 00 00 00
cc: 0d 06 7f 40 407f060d add.hi r3,3,r3
d0: 03 00 00 00
d4: 0e 08 df 47 47df080e add.ls 0,4,r4
d8: 04 00 00 00
dc: 0f fc c2 47 47c2fc0f add.pnz 0,r5,5
e0: 05 00 00 00
e4: 00 85 00 40 40008500 add.f r0,r1,r2
e8: 01 fa 00 40 4000fa01 add.f r0,r1,1
ec: 01 84 1e 40 401e8401 add.f r0,1,r2
f0: 00 85 e0 47 47e08500 add.f 0,r1,r2
f4: 00 fd 00 40 4000fd00 add.f r0,r1,0x200
f8: 00 02 00 00
fc: 00 05 1f 40 401f0500 add.f r0,0x200,r2
100: 00 02 00 00
104: 01 85 00 40 40008501 add.z.f r0,r1,r2
108: 02 fd 00 40 4000fd02 add.nz.f r0,r1,0
10c: 00 00 00 00
110: 0b 05 1f 40 401f050b add.lt.f r0,0,r2
114: 00 00 00 00
118: 09 85 c0 47 47c08509 add.gt.f 0,r1,r2
11c: 00 00 00 00 00000000
120: 0c fd 00 40 4000fd0c add.le.f r0,r1,0x200
124: 00 02 00 00
128: 0a 05 1f 40 401f050a add.ge.f r0,0x200,r2
12c: 00 02 00 00

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# add test
add r0,r1,r2
add r26,fp,sp
add ilink1,ilink2,blink
add r56,r59,lp_count
add r0,r1,0
add r0,0,r2
add 0,r1,r2
add r0,r1,-1
add r0,-1,r2
add -1,r1,r2
add r0,r1,255
add r0,255,r2
add 255,r1,r2
add r0,r1,-256
add r0,-256,r2
add -256,r1,r2
add r0,r1,256
add r0,-257,r2
add r0,255,256
add r0,256,255
add r0,r1,foo
add.al r0,r1,r2
add.ra r3,r4,r5
add.eq r6,r7,r8
add.z r9,r10,r11
add.ne r12,r13,r14
add.nz r15,r16,r17
add.pl r18,r19,r20
add.p r21,r22,r23
add.mi r24,r25,r26
add.n r27,r28,r29
add.cs r30,r31,r32
add.c r33,r34,r35
add.lo r36,r37,r38
add.cc r39,r40,r41
add.nc r42,r43,r44
add.hs r45,r46,r47
add.vs r48,r49,r50
add.v r56,r52,r53
add.vc r56,r55,r56
add.nv r56,r58,r59
add.gt r60,r60,r0
add.ge r0,r0,0
add.lt r1,1,r1
add.hi r3,3,r3
add.ls 4,4,r4
add.pnz 5,r5,5
add.f r0,r1,r2
add.f r0,r1,1
add.f r0,1,r2
add.f 0,r1,r2
add.f r0,r1,512
add.f r0,512,r2
add.eq.f r0,r1,r2
add.ne.f r0,r1,0
add.lt.f r0,0,r2
add.gt.f 0,r1,r2
add.le.f r0,r1,512
add.ge.f r0,512,r2

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#as: -EL
#objdump: -dr -EL
.*: +file format elf32-.*arc
Disassembly of section .text:
00000000 <.text>:
0: 00 84 00 60 60008400 and r0,r1,r2
4: 00 b8 4d 63 634db800 and gp,fp,sp
8: 00 3e af 63 63af3e00 and ilink1,ilink2,blink
c: 00 f8 1d 67 671df800 and r56,r59,lp_count
10: 00 fe 00 60 6000fe00 and r0,r1,0
14: 00 84 1f 60 601f8400 and r0,0,r2
18: 00 84 e0 67 67e08400 and 0,r1,r2
1c: ff ff 00 60 6000ffff and r0,r1,-1
20: ff 85 1f 60 601f85ff and r0,-1,r2
24: 00 84 e0 67 67e08400 and 0,r1,r2
28: ff fe 00 60 6000feff and r0,r1,255
2c: ff 84 1f 60 601f84ff and r0,255,r2
30: 00 84 e0 67 67e08400 and 0,r1,r2
34: 00 ff 00 60 6000ff00 and r0,r1,-256
38: 00 85 1f 60 601f8500 and r0,-256,r2
3c: 00 84 e0 67 67e08400 and 0,r1,r2
40: 00 fc 00 60 6000fc00 and r0,r1,0x100
44: 00 01 00 00
48: 00 04 1f 60 601f0400 and r0,0xffff_feff,r2
4c: ff fe ff ff
50: ff fc 1f 60 601ffcff and r0,255,0x100
54: 00 01 00 00
58: ff 7e 1f 60 601f7eff and r0,0x100,255
5c: 00 01 00 00
60: 00 fc 00 60 6000fc00 and r0,r1,0
64: 00 00 00 00
64: R_ARC_32 foo
68: 00 84 00 60 60008400 and r0,r1,r2
6c: 00 0a 62 60 60620a00 and r3,r4,r5
70: 01 90 c3 60 60c39001 and.z r6,r7,r8
74: 01 16 25 61 61251601 and.z r9,r10,r11
78: 02 9c 86 61 61869c02 and.nz r12,r13,r14
7c: 02 22 e8 61 61e82202 and.nz r15,r16,r17
80: 03 a8 49 62 6249a803 and.p r18,r19,r20
84: 03 2e ab 62 62ab2e03 and.p r21,r22,r23
88: 04 b4 0c 63 630cb404 and.n r24,r25,gp
8c: 04 3a 6e 63 636e3a04 and.n fp,sp,ilink1
90: 05 c0 cf 63 63cfc005 and.c ilink2,blink,r32
94: 05 46 31 64 64314605 and.c r33,r34,r35
98: 05 cc 92 64 6492cc05 and.c r36,r37,r38
9c: 06 52 f4 64 64f45206 and.nc r39,r40,r41
a0: 06 d8 55 65 6555d806 and.nc r42,r43,r44
a4: 06 5e b7 65 65b75e06 and.nc r45,r46,r47
a8: 07 e4 18 66 6618e407 and.v r48,r49,r50
ac: 07 6a 1a 67 671a6a07 and.v r56,r52,r53
b0: 08 f0 1b 67 671bf008 and.nv r56,r55,r56
b4: 08 76 1d 67 671d7608 and.nv r56,r58,r59
b8: 09 00 9e 67 679e0009 and.gt lp_count,lp_count,r0
bc: 0a 7c 00 60 60007c0a and.ge r0,r0,0
c0: 00 00 00 00
c4: 0b 02 3f 60 603f020b and.lt r1,1,r1
c8: 01 00 00 00
cc: 0d 06 7f 60 607f060d and.hi r3,3,r3
d0: 03 00 00 00
d4: 0e 08 df 67 67df080e and.ls 0,4,r4
d8: 04 00 00 00
dc: 0f fc c2 67 67c2fc0f and.pnz 0,r5,5
e0: 05 00 00 00
e4: 00 85 00 60 60008500 and.f r0,r1,r2
e8: 01 fa 00 60 6000fa01 and.f r0,r1,1
ec: 01 84 1e 60 601e8401 and.f r0,1,r2
f0: 00 85 e0 67 67e08500 and.f 0,r1,r2
f4: 00 fd 00 60 6000fd00 and.f r0,r1,0x200
f8: 00 02 00 00
fc: 00 05 1f 60 601f0500 and.f r0,0x200,r2
100: 00 02 00 00
104: 01 85 00 60 60008501 and.z.f r0,r1,r2
108: 02 fd 00 60 6000fd02 and.nz.f r0,r1,0
10c: 00 00 00 00
110: 0b 05 1f 60 601f050b and.lt.f r0,0,r2
114: 00 00 00 00
118: 09 85 c0 67 67c08509 and.gt.f 0,r1,r2
11c: 00 00 00 00 00000000
120: 0c fd 00 60 6000fd0c and.le.f r0,r1,0x200
124: 00 02 00 00
128: 0a 05 1f 60 601f050a and.ge.f r0,0x200,r2
12c: 00 02 00 00

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# and test
and r0,r1,r2
and r26,fp,sp
and ilink1,ilink2,blink
and r56,r59,lp_count
and r0,r1,0
and r0,0,r2
and 0,r1,r2
and r0,r1,-1
and r0,-1,r2
and -1,r1,r2
and r0,r1,255
and r0,255,r2
and 255,r1,r2
and r0,r1,-256
and r0,-256,r2
and -256,r1,r2
and r0,r1,256
and r0,-257,r2
and r0,255,256
and r0,256,255
and r0,r1,foo
and.al r0,r1,r2
and.ra r3,r4,r5
and.eq r6,r7,r8
and.z r9,r10,r11
and.ne r12,r13,r14
and.nz r15,r16,r17
and.pl r18,r19,r20
and.p r21,r22,r23
and.mi r24,r25,r26
and.n r27,r28,r29
and.cs r30,r31,r32
and.c r33,r34,r35
and.lo r36,r37,r38
and.cc r39,r40,r41
and.nc r42,r43,r44
and.hs r45,r46,r47
and.vs r48,r49,r50
and.v r56,r52,r53
and.vc r56,r55,r56
and.nv r56,r58,r59
and.gt r60,r60,r0
and.ge r0,r0,0
and.lt r1,1,r1
and.hi r3,3,r3
and.ls 4,4,r4
and.pnz 5,r5,5
and.f r0,r1,r2
and.f r0,r1,1
and.f r0,1,r2
and.f 0,r1,r2
and.f r0,r1,512
and.f r0,512,r2
and.eq.f r0,r1,r2
and.ne.f r0,r1,0
and.lt.f r0,0,r2
and.gt.f 0,r1,r2
and.le.f r0,r1,512
and.ge.f r0,512,r2

151
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# ARC gas testsuite
# Test an insn from a template .s/.d.
# The best way to create the .d file is to run the tests without it, let
# dejagnu crash, run as.new on the just built .s file, run objdump -dr on
# the result of that, copy the result into the .d file, and edit in the
# necessary patterns (@OC@, etc.). Sounds complicated but it's easy. The
# catch is that we assume a working assembler is used to build it. That's
# obviously not entirely kosher, but once the .d file is created one can
# verify it's contents over time.
#
# Template patterns:
# @OC@ - placeholder for the opcode
# @IC+?@ - place holder for the insn code
# @I3+??@ - place holder for the operation code of code 3 insns.
proc test_template_insn { cpu tmpl opcode icode } {
global srcdir subdir objdir
# Change @OC@ in the template file to $opcode
set in_fd [open $srcdir/$subdir/$tmpl.s r]
set out_fd [open $objdir/$opcode.s w]
# FIXME: check return codes
puts $out_fd "\t.cpu $cpu\n"
while { [gets $in_fd line] >= 0 } {
regsub "@OC@" $line $opcode line
puts $out_fd $line
}
close $in_fd
close $out_fd
# Create output template.
set in_fd [open $srcdir/$subdir/$tmpl.d r]
set out_fd [open $objdir/$opcode.d w]
# FIXME: check return codes
while { [gets $in_fd line] >= 0 } {
regsub "@OC@" $line $opcode line
#send_user "$line\n"
if [string match "*@IC+?@*" $line] {
# Insert the opcode. It occupies the top 5 bits.
regexp "^(.*)@IC\\+(.)@(.*)$" $line junk leftpart n rightpart
set n [expr ($icode << 3) + $n]
set n [format "%02x" $n]
puts $out_fd "$leftpart$n$rightpart"
} elseif [string match "*@I3+??@*" $line] {
# Insert insn 3 code (register C field)
# b15=8/0, b8=1/0 (their respective hex values in the objdump)
regexp "^(.*)@I3\\+(.)(.)@(.*)$" $line junk leftpart b15 b8 rightpart
set n [expr ($icode << 1) + ($b15 << 4) + ($b8 << 0)]
set n [format "%02x" $n]
puts $out_fd "$leftpart$n$rightpart"
} else {
puts $out_fd $line
}
}
close $in_fd
close $out_fd
# Finally, run the test.
run_dump_test $objdir/$opcode
# "make clean" won't delete these, so for now we must.
catch "exec rm -f $objdir/$opcode.s $objdir/$opcode.d"
}
# Run the tests.
# ARC base instruction set (to arc8)
if [istarget arc*-*-*] then {
run_dump_test ld
run_dump_test ld2
run_dump_test st
test_template_insn base math adc 9
test_template_insn base math add 8
test_template_insn base math and 12
test_template_insn base math bic 14
test_template_insn base math or 13
test_template_insn base math sbc 11
test_template_insn base math sub 10
test_template_insn base math xor 15
test_template_insn base alias mov 12
test_template_insn base alias rlc 9
test_template_insn base alias asl 8
# `lsl' gets dumped as `asl' so this must be tested elsewhere.
# test_template_insn base alias lsl 8
test_template_insn base sshift asr 1
test_template_insn base sshift lsr 2
test_template_insn base sshift ror 3
test_template_insn base sshift rrc 4
test_template_insn base branch b 4
test_template_insn base branch bl 5
test_template_insn base branch lp 6
run_dump_test "j"
test_template_insn base insn3 sexb 5
test_template_insn base insn3 sexw 6
test_template_insn base insn3 extb 7
test_template_insn base insn3 extw 8
run_dump_test "flag"
# run_dump_test "nop"
run_dump_test "ld"
run_dump_test "st"
# Specially encoded/single operand instructions
run_dump_test flag
run_dump_test brk
run_dump_test sleep
run_dump_test swi
run_dump_test asr
run_dump_test lsr
run_dump_test ror
run_dump_test rrc
run_dump_test sexb
run_dump_test sexw
run_dump_test extb
run_dump_test extw
run_dump_test b
run_dump_test bl
run_dump_test lp
run_dump_test j
run_dump_test jl
run_dump_test add
run_dump_test asl
# FIXME: ??? `lsl' gets dumped as `asl'
# run_dump_test lsl
run_dump_test adc
run_dump_test rlc
run_dump_test sub
run_dump_test sbc
run_dump_test and
run_dump_test mov
run_dump_test or
run_dump_test bic
run_dump_test xor
run_dump_test nop
}
# ARC library extensions
if [istarget arc*-*-*] then {
# *TODO*
}

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#as: -EL
#objdump: -dr -EL
.*: +file format elf32-.*arc
Disassembly of section .text:
00000000 <.text>:
0: 00 82 00 40 40008200 asl r0,r1
4: 00 38 6e 43 436e3800 asl fp,sp
8: 00 fe 1f 40 401ffe00 asl r0,0
c: ff ff 3f 40 403fffff asl r1,-1
10: 00 04 e1 47 47e10400 asl 0,r2
14: 00 86 e1 47 47e18600 asl 0,r3
18: ff fe 9f 40 409ffeff asl r4,255
1c: 00 8a e2 47 47e28a00 asl 0,r5
20: 00 ff df 40 40dfff00 asl r6,-256
24: 00 8e e3 47 47e38e00 asl 0,r7
28: 00 7c 1f 41 411f7c00 asl r8,0x100
2c: 00 01 00 00
30: 00 7c 3f 41 413f7c00 asl r9,0xffff_feff
34: ff fe ff ff
38: 00 7c 7f 41 417f7c00 asl r11,0x4242_4242
3c: 42 42 42 42
40: 00 7c ff 47 47ff7c00 asl 0,0x100
44: 00 01 00 00
48: 00 7c 1f 40 401f7c00 asl r0,0
4c: 00 00 00 00
4c: R_ARC_32 foo
50: 00 82 00 40 40008200 asl r0,r1
54: 00 08 62 40 40620800 asl r3,r4
58: 01 8e c3 40 40c38e01 asl.z r6,r7
5c: 01 14 25 41 41251401 asl.z r9,r10
60: 02 9a 86 41 41869a02 asl.nz r12,r13
64: 02 20 e8 41 41e82002 asl.nz r15,r16
68: 03 a6 49 42 4249a603 asl.p r18,r19
6c: 03 2c ab 42 42ab2c03 asl.p r21,r22
70: 04 b2 0c 43 430cb204 asl.n r24,r25
74: 04 38 6e 43 436e3804 asl.n fp,sp
78: 05 be cf 43 43cfbe05 asl.c ilink2,blink
7c: 05 44 31 44 44314405 asl.c r33,r34
80: 05 ca 92 44 4492ca05 asl.c r36,r37
84: 06 50 f4 44 44f45006 asl.nc r39,r40
88: 06 d6 55 45 4555d606 asl.nc r42,r43
8c: 06 5c b7 45 45b75c06 asl.nc r45,r46
90: 07 e2 18 46 4618e207 asl.v r48,r49
94: 07 64 39 46 46396407 asl.v r49,r50
98: 08 ee 3b 46 463bee08 asl.nv r49,r55
9c: 08 74 3d 46 463d7408 asl.nv r49,r58
a0: 09 78 9e 47 479e7809 asl.gt lp_count,lp_count
a4: 0a 7c 1f 40 401f7c0a asl.ge r0,0
a8: 00 00 00 00
ac: 0c 7c df 47 47df7c0c asl.le 0,2
b0: 02 00 00 00
b4: 0d 86 61 40 4061860d asl.hi r3,r3
b8: 0e 08 82 40 4082080e asl.ls r4,r4
bc: 0f 8a a2 40 40a28a0f asl.pnz r5,r5
c0: 00 83 00 40 40008300 asl.f r0,r1
c4: 01 fa 5e 40 405efa01 asl.f r2,1
c8: 00 87 e1 47 47e18700 asl.f 0,r3
cc: 00 09 e2 47 47e20900 asl.f 0,r4
d0: 00 7d bf 40 40bf7d00 asl.f r5,0x200
d4: 00 02 00 00
d8: 00 7d df 47 47df7d00 asl.f 0,0x200
dc: 00 02 00 00
e0: 01 83 00 40 40008301 asl.z.f r0,r1
e4: 02 7d 3f 40 403f7d02 asl.nz.f r1,0
e8: 00 00 00 00

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# asl test
asl r0,r1
asl fp,sp
asl r0,0
asl r1,-1
asl 0,r2
asl -1,r3
asl r4,255
asl 255,r5
asl r6,-256
asl -256,r7
asl r8,256
asl r9,-257
asl r11,0x42424242
asl 255,256
asl r0,foo
asl.al r0,r1
asl.ra r3,r4
asl.eq r6,r7
asl.z r9,r10
asl.ne r12,r13
asl.nz r15,r16
asl.pl r18,r19
asl.p r21,r22
asl.mi r24,r25
asl.n r27,r28
asl.cs r30,r31
asl.c r33,r34
asl.lo r36,r37
asl.cc r39,r40
asl.nc r42,r43
asl.hs r45,r46
asl.vs r48,r49
asl.v r49,r50
asl.vc r49,r55
asl.nv r49,r58
asl.gt r60,r60
asl.ge r0,0
asl.le 2,2
asl.hi r3,r3
asl.ls r4,r4
asl.pnz r5,r5
asl.f r0,r1
asl.f r2,1
asl.f 1,r3
asl.f 0,r4
asl.f r5,512
asl.f 512,512
asl.eq.f r0,r1
asl.ne.f r1,0

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#as: -EL
#objdump: -dr -EL
.*: +file format elf32-.*arc
Disassembly of section .text:
00000000 <.text>:
0: 00 82 00 18 18008200 asr r0,r1
4: 00 02 6e 1b 1b6e0200 asr fp,sp
8: 00 82 1f 18 181f8200 asr r0,0
c: ff 83 3f 18 183f83ff asr r1,-1
10: 00 02 e1 1f 1fe10200 asr 0,r2
14: 00 82 e1 1f 1fe18200 asr 0,r3
18: ff 82 9f 18 189f82ff asr r4,255
1c: 00 82 e2 1f 1fe28200 asr 0,r5
20: 00 83 df 18 18df8300 asr r6,-256
24: 00 82 e3 1f 1fe38200 asr 0,r7
28: 00 02 1f 19 191f0200 asr r8,0x100
2c: 00 01 00 00
30: 00 02 3f 19 193f0200 asr r9,0xffff_feff
34: ff fe ff ff
38: 00 02 7f 19 197f0200 asr r11,0x4242_4242
3c: 42 42 42 42
40: 00 02 ff 1f 1fff0200 asr 0,0x100
44: 00 01 00 00
48: 00 02 1f 18 181f0200 asr r0,0
4c: 00 00 00 00
4c: R_ARC_32 foo
50: 01 82 45 19 19458201 asr.z r10,r11
54: 02 82 86 19 19868202 asr.nz r12,r13
58: 0b 02 df 19 19df020b asr.lt r14,0
5c: 00 00 00 00
60: 09 02 ff 19 19ff0209 asr.gt r15,0x200
64: 00 02 00 00
68: 00 83 00 18 18008300 asr.f r0,r1
6c: 01 82 5e 18 185e8201 asr.f r2,1
70: 00 03 e2 1f 1fe20300 asr.f 0,r4
74: 00 03 bf 18 18bf0300 asr.f r5,0x200
78: 00 02 00 00
7c: 00 03 df 1f 1fdf0300 asr.f 0,0x200
80: 00 02 00 00
84: 01 83 00 18 18008301 asr.z.f r0,r1
88: 02 03 3f 18 183f0302 asr.nz.f r1,0
8c: 00 00 00 00
90: 0b 03 c1 1f 1fc1030b asr.lt.f 0,r2
94: 00 00 00 00 00000000
98: 0c 03 1f 18 181f030c asr.le.f r0,0x200
9c: 00 02 00 00
a0: 04 03 df 1f 1fdf0304 asr.n.f 0,0x200
a4: 00 02 00 00

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# asr test
asr r0,r1
asr fp,sp
asr r0,0
asr r1,-1
asr 0,r2
asr -1,r3
asr r4,255
asr 255,r5
asr r6,-256
asr -256,r7
asr r8,256
asr r9,-257
asr r11,0x42424242
asr 255,256
asr r0,foo
asr.eq r10,r11
asr.ne r12,r13
asr.lt r14,0
asr.gt r15,512
asr.f r0,r1
asr.f r2,1
asr.f 0,r4
asr.f r5,512
asr.f 512,512
asr.eq.f r0,r1
asr.ne.f r1,0
asr.lt.f 0,r2
asr.le.f r0,512
asr.n.f 512,512

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#as: -EL
#objdump: -dr -EL
.*: +file format elf32-.*arc
Disassembly of section .text:
00000000 <text_label>:
0: 80 ff ff 27 27ffff80 b 0 <text_label>
4: 00 ff ff 27 27ffff00 b 0 <text_label>
8: 80 fe ff 27 27fffe80 b 0 <text_label>
c: 01 fe ff 27 27fffe01 bz 0 <text_label>
10: 81 fd ff 27 27fffd81 bz 0 <text_label>
14: 02 fd ff 27 27fffd02 bnz 0 <text_label>
18: 82 fc ff 27 27fffc82 bnz 0 <text_label>
1c: 03 fc ff 27 27fffc03 bp 0 <text_label>
20: 83 fb ff 27 27fffb83 bp 0 <text_label>
24: 04 fb ff 27 27fffb04 bn 0 <text_label>
28: 84 fa ff 27 27fffa84 bn 0 <text_label>
2c: 05 fa ff 27 27fffa05 bc 0 <text_label>
30: 85 f9 ff 27 27fff985 bc 0 <text_label>
34: 05 f9 ff 27 27fff905 bc 0 <text_label>
38: 86 f8 ff 27 27fff886 bnc 0 <text_label>
3c: 06 f8 ff 27 27fff806 bnc 0 <text_label>
40: 86 f7 ff 27 27fff786 bnc 0 <text_label>
44: 07 f7 ff 27 27fff707 bv 0 <text_label>
48: 87 f6 ff 27 27fff687 bv 0 <text_label>
4c: 08 f6 ff 27 27fff608 bnv 0 <text_label>
50: 88 f5 ff 27 27fff588 bnv 0 <text_label>
54: 09 f5 ff 27 27fff509 bgt 0 <text_label>
58: 8a f4 ff 27 27fff48a bge 0 <text_label>
5c: 0b f4 ff 27 27fff40b blt 0 <text_label>
60: 8c f3 ff 27 27fff38c ble 0 <text_label>
64: 0d f3 ff 27 27fff30d bhi 0 <text_label>
68: 8e f2 ff 27 27fff28e bls 0 <text_label>
6c: 0f f2 ff 27 27fff20f bpnz 0 <text_label>
70: a0 f1 ff 27 27fff1a0 b.d 0 <text_label>
74: 00 f1 ff 27 27fff100 b 0 <text_label>
78: c0 f0 ff 27 27fff0c0 b.jd 0 <text_label>
7c: 21 f0 ff 27 27fff021 bz.d 0 <text_label>
80: 82 ef ff 27 27ffef82 bnz 0 <text_label>
84: 46 ef ff 27 27ffef46 bnc.jd 0 <text_label>

40
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# b test
text_label:
b text_label
bal text_label
bra text_label
beq text_label
bz text_label
bne text_label
bnz text_label
bpl text_label
bp text_label
bmi text_label
bn text_label
bcs text_label
bc text_label
blo text_label
bcc text_label
bnc text_label
bhs text_label
bvs text_label
bv text_label
bvc text_label
bnv text_label
bgt text_label
bge text_label
blt text_label
ble text_label
bhi text_label
bls text_label
bpnz text_label
b.d text_label
b.nd text_label
b.jd text_label
beq.d text_label
bne.nd text_label
bcc.jd text_label

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#as: -EL
#objdump: -dr -EL
.*: +file format elf32-.*arc
Disassembly of section .text:
00000000 <.text>:
0: 00 84 00 70 70008400 bic r0,r1,r2
4: 00 b8 4d 73 734db800 bic gp,fp,sp
8: 00 3e af 73 73af3e00 bic ilink1,ilink2,blink
c: 00 f8 1d 77 771df800 bic r56,r59,lp_count
10: 00 fe 00 70 7000fe00 bic r0,r1,0
14: 00 84 1f 70 701f8400 bic r0,0,r2
18: 00 84 e0 77 77e08400 bic 0,r1,r2
1c: ff ff 00 70 7000ffff bic r0,r1,-1
20: ff 85 1f 70 701f85ff bic r0,-1,r2
24: 00 84 e0 77 77e08400 bic 0,r1,r2
28: ff fe 00 70 7000feff bic r0,r1,255
2c: ff 84 1f 70 701f84ff bic r0,255,r2
30: 00 84 e0 77 77e08400 bic 0,r1,r2
34: 00 ff 00 70 7000ff00 bic r0,r1,-256
38: 00 85 1f 70 701f8500 bic r0,-256,r2
3c: 00 84 e0 77 77e08400 bic 0,r1,r2
40: 00 fc 00 70 7000fc00 bic r0,r1,0x100
44: 00 01 00 00
48: 00 04 1f 70 701f0400 bic r0,0xffff_feff,r2
4c: ff fe ff ff
50: ff fc 1f 70 701ffcff bic r0,255,0x100
54: 00 01 00 00
58: ff 7e 1f 70 701f7eff bic r0,0x100,255
5c: 00 01 00 00
60: 00 fc 00 70 7000fc00 bic r0,r1,0
64: 00 00 00 00
64: R_ARC_32 foo
68: 00 84 00 70 70008400 bic r0,r1,r2
6c: 00 0a 62 70 70620a00 bic r3,r4,r5
70: 01 90 c3 70 70c39001 bic.z r6,r7,r8
74: 01 16 25 71 71251601 bic.z r9,r10,r11
78: 02 9c 86 71 71869c02 bic.nz r12,r13,r14
7c: 02 22 e8 71 71e82202 bic.nz r15,r16,r17
80: 03 a8 49 72 7249a803 bic.p r18,r19,r20
84: 03 2e ab 72 72ab2e03 bic.p r21,r22,r23
88: 04 b4 0c 73 730cb404 bic.n r24,r25,gp
8c: 04 3a 6e 73 736e3a04 bic.n fp,sp,ilink1
90: 05 c0 cf 73 73cfc005 bic.c ilink2,blink,r32
94: 05 46 31 74 74314605 bic.c r33,r34,r35
98: 05 cc 92 74 7492cc05 bic.c r36,r37,r38
9c: 06 52 f4 74 74f45206 bic.nc r39,r40,r41
a0: 06 d8 55 75 7555d806 bic.nc r42,r43,r44
a4: 06 5e b7 75 75b75e06 bic.nc r45,r46,r47
a8: 07 e4 18 76 7618e407 bic.v r48,r49,r50
ac: 07 6a 1a 77 771a6a07 bic.v r56,r52,r53
b0: 08 f0 1b 77 771bf008 bic.nv r56,r55,r56
b4: 08 76 1d 77 771d7608 bic.nv r56,r58,r59
b8: 09 00 9e 77 779e0009 bic.gt lp_count,lp_count,r0
bc: 0a 7c 00 70 70007c0a bic.ge r0,r0,0
c0: 00 00 00 00
c4: 0b 02 3f 70 703f020b bic.lt r1,1,r1
c8: 01 00 00 00
cc: 0d 06 7f 70 707f060d bic.hi r3,3,r3
d0: 03 00 00 00
d4: 0e 08 df 77 77df080e bic.ls 0,4,r4
d8: 04 00 00 00
dc: 0f fc c2 77 77c2fc0f bic.pnz 0,r5,5
e0: 05 00 00 00
e4: 00 85 00 70 70008500 bic.f r0,r1,r2
e8: 01 fa 00 70 7000fa01 bic.f r0,r1,1
ec: 01 84 1e 70 701e8401 bic.f r0,1,r2
f0: 00 85 e0 77 77e08500 bic.f 0,r1,r2
f4: 00 fd 00 70 7000fd00 bic.f r0,r1,0x200
f8: 00 02 00 00
fc: 00 05 1f 70 701f0500 bic.f r0,0x200,r2
100: 00 02 00 00
104: 01 85 00 70 70008501 bic.z.f r0,r1,r2
108: 02 fd 00 70 7000fd02 bic.nz.f r0,r1,0
10c: 00 00 00 00
110: 0b 05 1f 70 701f050b bic.lt.f r0,0,r2
114: 00 00 00 00
118: 09 85 c0 77 77c08509 bic.gt.f 0,r1,r2
11c: 00 00 00 00 00000000
120: 0c fd 00 70 7000fd0c bic.le.f r0,r1,0x200
124: 00 02 00 00
128: 0a 05 1f 70 701f050a bic.ge.f r0,0x200,r2
12c: 00 02 00 00

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# bic test
bic r0,r1,r2
bic r26,fp,sp
bic ilink1,ilink2,blink
bic r56,r59,lp_count
bic r0,r1,0
bic r0,0,r2
bic 0,r1,r2
bic r0,r1,-1
bic r0,-1,r2
bic -1,r1,r2
bic r0,r1,255
bic r0,255,r2
bic 255,r1,r2
bic r0,r1,-256
bic r0,-256,r2
bic -256,r1,r2
bic r0,r1,256
bic r0,-257,r2
bic r0,255,256
bic r0,256,255
bic r0,r1,foo
bic.al r0,r1,r2
bic.ra r3,r4,r5
bic.eq r6,r7,r8
bic.z r9,r10,r11
bic.ne r12,r13,r14
bic.nz r15,r16,r17
bic.pl r18,r19,r20
bic.p r21,r22,r23
bic.mi r24,r25,r26
bic.n r27,r28,r29
bic.cs r30,r31,r32
bic.c r33,r34,r35
bic.lo r36,r37,r38
bic.cc r39,r40,r41
bic.nc r42,r43,r44
bic.hs r45,r46,r47
bic.vs r48,r49,r50
bic.v r56,r52,r53
bic.vc r56,r55,r56
bic.nv r56,r58,r59
bic.gt r60,r60,r0
bic.ge r0,r0,0
bic.lt r1,1,r1
bic.hi r3,3,r3
bic.ls 4,4,r4
bic.pnz 5,r5,5
bic.f r0,r1,r2
bic.f r0,r1,1
bic.f r0,1,r2
bic.f 0,r1,r2
bic.f r0,r1,512
bic.f r0,512,r2
bic.eq.f r0,r1,r2
bic.ne.f r0,r1,0
bic.lt.f r0,0,r2
bic.gt.f 0,r1,r2
bic.le.f r0,r1,512
bic.ge.f r0,512,r2

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#as: -EL
#objdump: -dr -EL
.*: +file format elf32-.*arc
Disassembly of section .text:
00000000 <text_label>:
0: 80 ff ff 2f 2fffff80 bl 0 <text_label>
4: 00 ff ff 2f 2fffff00 bl 0 <text_label>
8: 80 fe ff 2f 2ffffe80 bl 0 <text_label>
c: 01 fe ff 2f 2ffffe01 blz 0 <text_label>
10: 81 fd ff 2f 2ffffd81 blz 0 <text_label>
14: 02 fd ff 2f 2ffffd02 blnz 0 <text_label>
18: 82 fc ff 2f 2ffffc82 blnz 0 <text_label>
1c: 03 fc ff 2f 2ffffc03 blp 0 <text_label>
20: 83 fb ff 2f 2ffffb83 blp 0 <text_label>
24: 04 fb ff 2f 2ffffb04 bln 0 <text_label>
28: 84 fa ff 2f 2ffffa84 bln 0 <text_label>
2c: 05 fa ff 2f 2ffffa05 blc 0 <text_label>
30: 85 f9 ff 2f 2ffff985 blc 0 <text_label>
34: 05 f9 ff 2f 2ffff905 blc 0 <text_label>
38: 86 f8 ff 2f 2ffff886 blnc 0 <text_label>
3c: 06 f8 ff 2f 2ffff806 blnc 0 <text_label>
40: 86 f7 ff 2f 2ffff786 blnc 0 <text_label>
44: 07 f7 ff 2f 2ffff707 blv 0 <text_label>
48: 87 f6 ff 2f 2ffff687 blv 0 <text_label>
4c: 08 f6 ff 2f 2ffff608 blnv 0 <text_label>
50: 88 f5 ff 2f 2ffff588 blnv 0 <text_label>
54: 09 f5 ff 2f 2ffff509 blgt 0 <text_label>
58: 8a f4 ff 2f 2ffff48a blge 0 <text_label>
5c: 0b f4 ff 2f 2ffff40b bllt 0 <text_label>
60: 8c f3 ff 2f 2ffff38c blle 0 <text_label>
64: 0d f3 ff 2f 2ffff30d blhi 0 <text_label>
68: 8e f2 ff 2f 2ffff28e blls 0 <text_label>
6c: 0f f2 ff 2f 2ffff20f blpnz 0 <text_label>
70: a0 f1 ff 2f 2ffff1a0 bl.d 0 <text_label>
74: 00 f1 ff 2f 2ffff100 bl 0 <text_label>
78: c0 f0 ff 2f 2ffff0c0 bl.jd 0 <text_label>
7c: 21 f0 ff 2f 2ffff021 blz.d 0 <text_label>
80: 82 ef ff 2f 2fffef82 blnz 0 <text_label>
84: 46 ef ff 2f 2fffef46 blnc.jd 0 <text_label>

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# bl test
text_label:
bl text_label
blal text_label
blra text_label
bleq text_label
blz text_label
blne text_label
blnz text_label
blpl text_label
blp text_label
blmi text_label
bln text_label
blcs text_label
blc text_label
bllo text_label
blcc text_label
blnc text_label
blhs text_label
blvs text_label
blv text_label
blvc text_label
blnv text_label
blgt text_label
blge text_label
bllt text_label
blle text_label
blhi text_label
blls text_label
blpnz text_label
bl.d text_label
bl.nd text_label
bl.jd text_label
bleq.d text_label
blne.nd text_label
blcc.jd text_label

11
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#as: -EL -marc7
#objdump: -dr -EL
.*: +file format elf32-.*arc
Disassembly of section .text:
00000000 <main>:
0: 00 84 00 40 40008400 add r0,r1,r2
4: 00 fe ff 1f 1ffffe00 brk
8: 00 0a 62 50 50620a00 sub r3,r4,r5

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# brk test
main:
add r0,r1,r2
brk
sub r3,r4,r5

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#as: -EL
#objdump: -dr -EL
.*: +file format elf32-.*arc
Disassembly of section .text:
00000000 <.text>:
0: 00 8e 00 18 18008e00 extb r0,r1
4: 00 0e 6e 1b 1b6e0e00 extb fp,sp
8: 00 8e 1f 18 181f8e00 extb r0,0
c: ff 8f 3f 18 183f8fff extb r1,-1
10: 00 0e e1 1f 1fe10e00 extb 0,r2
14: 00 8e e1 1f 1fe18e00 extb 0,r3
18: ff 8e 9f 18 189f8eff extb r4,255
1c: 00 8e e2 1f 1fe28e00 extb 0,r5
20: 00 8f df 18 18df8f00 extb r6,-256
24: 00 8e e3 1f 1fe38e00 extb 0,r7
28: 00 0e 1f 19 191f0e00 extb r8,0x100
2c: 00 01 00 00
30: 00 0e 3f 19 193f0e00 extb r9,0xffff_feff
34: ff fe ff ff
38: 00 0e 7f 19 197f0e00 extb r11,0x4242_4242
3c: 42 42 42 42
40: 00 0e ff 1f 1fff0e00 extb 0,0x100
44: 00 01 00 00
48: 00 0e 1f 18 181f0e00 extb r0,0
4c: 00 00 00 00
4c: R_ARC_32 foo
50: 01 8e 45 19 19458e01 extb.z r10,r11
54: 02 8e 86 19 19868e02 extb.nz r12,r13
58: 0b 0e df 19 19df0e0b extb.lt r14,0
5c: 00 00 00 00
60: 09 0e ff 19 19ff0e09 extb.gt r15,0x200
64: 00 02 00 00
68: 00 8f 00 18 18008f00 extb.f r0,r1
6c: 01 8e 5e 18 185e8e01 extb.f r2,1
70: 00 0f e2 1f 1fe20f00 extb.f 0,r4
74: 00 0f bf 18 18bf0f00 extb.f r5,0x200
78: 00 02 00 00
7c: 00 0f df 1f 1fdf0f00 extb.f 0,0x200
80: 00 02 00 00
84: 01 8f 00 18 18008f01 extb.z.f r0,r1
88: 02 0f 3f 18 183f0f02 extb.nz.f r1,0
8c: 00 00 00 00
90: 0b 0f c1 1f 1fc10f0b extb.lt.f 0,r2
94: 00 00 00 00 00000000
98: 0c 0f 1f 18 181f0f0c extb.le.f r0,0x200
9c: 00 02 00 00
a0: 04 0f df 1f 1fdf0f04 extb.n.f 0,0x200
a4: 00 02 00 00

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# extb test
extb r0,r1
extb fp,sp
extb r0,0
extb r1,-1
extb 0,r2
extb -1,r3
extb r4,255
extb 255,r5
extb r6,-256
extb -256,r7
extb r8,256
extb r9,-257
extb r11,0x42424242
extb 255,256
extb r0,foo
extb.eq r10,r11
extb.ne r12,r13
extb.lt r14,0
extb.gt r15,512
extb.f r0,r1
extb.f r2,1
extb.f 0,r4
extb.f r5,512
extb.f 512,512
extb.eq.f r0,r1
extb.ne.f r1,0
extb.lt.f 0,r2
extb.le.f r0,512
extb.n.f 512,512

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#as: -EL
#objdump: -dr -EL
.*: +file format elf32-.*arc
Disassembly of section .text:
00000000 <.text>:
0: 00 90 00 18 18009000 extw r0,r1
4: 00 10 6e 1b 1b6e1000 extw fp,sp
8: 00 90 1f 18 181f9000 extw r0,0
c: ff 91 3f 18 183f91ff extw r1,-1
10: 00 10 e1 1f 1fe11000 extw 0,r2
14: 00 90 e1 1f 1fe19000 extw 0,r3
18: ff 90 9f 18 189f90ff extw r4,255
1c: 00 90 e2 1f 1fe29000 extw 0,r5
20: 00 91 df 18 18df9100 extw r6,-256
24: 00 90 e3 1f 1fe39000 extw 0,r7
28: 00 10 1f 19 191f1000 extw r8,0x100
2c: 00 01 00 00
30: 00 10 3f 19 193f1000 extw r9,0xffff_feff
34: ff fe ff ff
38: 00 10 7f 19 197f1000 extw r11,0x4242_4242
3c: 42 42 42 42
40: 00 10 ff 1f 1fff1000 extw 0,0x100
44: 00 01 00 00
48: 00 10 1f 18 181f1000 extw r0,0
4c: 00 00 00 00
4c: R_ARC_32 foo
50: 01 90 45 19 19459001 extw.z r10,r11
54: 02 90 86 19 19869002 extw.nz r12,r13
58: 0b 10 df 19 19df100b extw.lt r14,0
5c: 00 00 00 00
60: 09 10 ff 19 19ff1009 extw.gt r15,0x200
64: 00 02 00 00
68: 00 91 00 18 18009100 extw.f r0,r1
6c: 01 90 5e 18 185e9001 extw.f r2,1
70: 00 11 e2 1f 1fe21100 extw.f 0,r4
74: 00 11 bf 18 18bf1100 extw.f r5,0x200
78: 00 02 00 00
7c: 00 11 df 1f 1fdf1100 extw.f 0,0x200
80: 00 02 00 00
84: 01 91 00 18 18009101 extw.z.f r0,r1
88: 02 11 3f 18 183f1102 extw.nz.f r1,0
8c: 00 00 00 00
90: 0b 11 c1 1f 1fc1110b extw.lt.f 0,r2
94: 00 00 00 00 00000000
98: 0c 11 1f 18 181f110c extw.le.f r0,0x200
9c: 00 02 00 00
a0: 04 11 df 1f 1fdf1104 extw.n.f 0,0x200
a4: 00 02 00 00

38
gas/testsuite/gas/arc/extw.s Normal file
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@ -0,0 +1,38 @@
# extw test
extw r0,r1
extw fp,sp
extw r0,0
extw r1,-1
extw 0,r2
extw -1,r3
extw r4,255
extw 255,r5
extw r6,-256
extw -256,r7
extw r8,256
extw r9,-257
extw r11,0x42424242
extw 255,256
extw r0,foo
extw.eq r10,r11
extw.ne r12,r13
extw.lt r14,0
extw.gt r15,512
extw.f r0,r1
extw.f r2,1
extw.f 0,r4
extw.f r5,512
extw.f 512,512
extw.eq.f r0,r1
extw.ne.f r1,0
extw.lt.f 0,r2
extw.le.f r0,512
extw.n.f 512,512

59
gas/testsuite/gas/arc/flag.d
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@ -1,29 +1,38 @@
#objdump: -dr
#name: flag
# Test the flag macro.
#as: -EL
#objdump: -dr -EL
.*: +file format elf32-.*arc
No symbols in "a.out".
Disassembly of section .text:
00000000 1fa00000 flag r0
00000004 1fbf8001 flag 1
00000008 1fbf8002 flag 2
0000000c 1fbf8004 flag 4
00000010 1fbf8008 flag 8
00000014 1fbf8010 flag 16
00000018 1fbf8020 flag 32
0000001c 1fbf8040 flag 64
00000020 1fbf8080 flag 128
00000024 1fbf0000 flag -2147483647
0000002c 1fa0000b flag.lt r0
00000030 1fbf0009 flag.gt 1
00000038 1fbf0009 flag.gt 2
00000040 1fbf0009 flag.gt 4
00000048 1fbf0009 flag.gt 8
00000050 1fbf0009 flag.gt 16
00000058 1fbf0009 flag.gt 32
00000060 1fbf0009 flag.gt 64
00000068 1fbf0009 flag.gt 128
00000070 1fbf000a flag.ge -2147483647
00000000 <.text>:
0: 00 00 a0 1f 1fa00000 flag r0
4: 01 80 bf 1f 1fbf8001 flag 1
8: 02 80 bf 1f 1fbf8002 flag 2
c: 04 80 bf 1f 1fbf8004 flag 4
10: 08 80 bf 1f 1fbf8008 flag 8
14: 10 80 bf 1f 1fbf8010 flag 16
18: 20 80 bf 1f 1fbf8020 flag 32
1c: 40 80 bf 1f 1fbf8040 flag 64
20: 80 80 bf 1f 1fbf8080 flag 128
24: 00 00 bf 1f 1fbf0000 flag 0x8000_0001
28: 01 00 00 80
2c: 0b 00 a0 1f 1fa0000b flag.lt r0
30: 09 00 bf 1f 1fbf0009 flag.gt 1
34: 01 00 00 00
38: 09 00 bf 1f 1fbf0009 flag.gt 2
3c: 02 00 00 00
40: 09 00 bf 1f 1fbf0009 flag.gt 4
44: 04 00 00 00
48: 09 00 bf 1f 1fbf0009 flag.gt 8
4c: 08 00 00 00
50: 09 00 bf 1f 1fbf0009 flag.gt 16
54: 10 00 00 00
58: 09 00 bf 1f 1fbf0009 flag.gt 32
5c: 20 00 00 00
60: 09 00 bf 1f 1fbf0009 flag.gt 64
64: 40 00 00 00
68: 09 00 bf 1f 1fbf0009 flag.gt 128
6c: 80 00 00 00
70: 0a 00 bf 1f 1fbf000a flag.ge 0x8000_0001
74: 01 00 00 80

194
gas/testsuite/gas/arc/j.d
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@ -1,75 +1,127 @@
#objdump: -dr
#name: j
# Test the j insn.
#as: -EL
#objdump: -dr -EL
.*: +file format elf32-.*arc
Disassembly of section .text:
00000000 <text_label> 38000000 j r0
00000004 <text_label\+4> 38000020 j.d r0
00000008 <text_label\+8> 38000040 j.jd r0
0000000c <text_label\+c> 38000000 j r0
00000010 <text_label\+10> 38008000 j r1
00000014 <text_label\+14> 38008020 j.d r1
00000018 <text_label\+18> 38008040 j.jd r1
0000001c <text_label\+1c> 38008000 j r1
00000020 <text_label\+20> 381f0000 j 0
RELOC: 00000024 R_ARC_32 .text
00000028 <text_label\+28> 381f0000 j 0
RELOC: 0000002c R_ARC_32 .text
00000030 <text_label\+30> 381f0000 j 0
RELOC: 00000034 R_ARC_32 .text
00000038 <text_label\+38> 381f0001 jeq 0
RELOC: 0000003c R_ARC_32 .text
00000040 <text_label\+40> 381f0001 jeq 0
RELOC: 00000044 R_ARC_32 .text
00000048 <text_label\+48> 381f0002 jne 0
RELOC: 0000004c R_ARC_32 .text
00000050 <text_label\+50> 381f0002 jne 0
RELOC: 00000054 R_ARC_32 .text
00000058 <text_label\+58> 381f0003 jp 0
RELOC: 0000005c R_ARC_32 .text
00000060 <text_label\+60> 381f0003 jp 0
RELOC: 00000064 R_ARC_32 .text
00000068 <text_label\+68> 381f0004 jn 0
RELOC: 0000006c R_ARC_32 .text
00000070 <text_label\+70> 381f0004 jn 0
RELOC: 00000074 R_ARC_32 .text
00000078 <text_label\+78> 381f0005 jc 0
RELOC: 0000007c R_ARC_32 .text
00000080 <text_label\+80> 381f0005 jc 0
RELOC: 00000084 R_ARC_32 .text
00000088 <text_label\+88> 381f0005 jc 0
RELOC: 0000008c R_ARC_32 .text
00000090 <text_label\+90> 381f0006 jnc 0
RELOC: 00000094 R_ARC_32 .text
00000098 <text_label\+98> 381f0006 jnc 0
RELOC: 0000009c R_ARC_32 .text
000000a0 <text_label\+a0> 381f0006 jnc 0
RELOC: 000000a4 R_ARC_32 .text
000000a8 <text_label\+a8> 381f0007 jv 0
RELOC: 000000ac R_ARC_32 .text
000000b0 <text_label\+b0> 381f0007 jv 0
RELOC: 000000b4 R_ARC_32 .text
000000b8 <text_label\+b8> 381f0008 jnv 0
RELOC: 000000bc R_ARC_32 .text
000000c0 <text_label\+c0> 381f0008 jnv 0
RELOC: 000000c4 R_ARC_32 .text
000000c8 <text_label\+c8> 381f0009 jgt 0
RELOC: 000000cc R_ARC_32 .text
000000d0 <text_label\+d0> 381f000a jge 0
RELOC: 000000d4 R_ARC_32 .text
000000d8 <text_label\+d8> 381f000b jlt 0
RELOC: 000000dc R_ARC_32 .text
000000e0 <text_label\+e0> 381f000c jle 0
RELOC: 000000e4 R_ARC_32 .text
000000e8 <text_label\+e8> 381f000d jhi 0
RELOC: 000000ec R_ARC_32 .text
000000f0 <text_label\+f0> 381f000e jls 0
RELOC: 000000f4 R_ARC_32 .text
000000f8 <text_label\+f8> 381f000f jpnz 0
RELOC: 000000fc R_ARC_32 .text
00000100 <text_label\+100> 381f0000 j 0
RELOC: 00000104 R_ARC_32 external_text_label
00000108 <text_label\+108> 381f0000 j 0
00000000 <text_label>:
0: 00 00 1f 38 381f0000 j 0 <text_label>
4: 00 00 00 00
4: R_ARC_B26 .text
8: 00 00 1f 38 381f0000 j 0 <text_label>
c: 00 00 00 00
c: R_ARC_B26 .text
10: 00 00 1f 38 381f0000 j 0 <text_label>
14: 00 00 00 00
14: R_ARC_B26 .text
18: 01 00 1f 38 381f0001 jz 0 <text_label>
1c: 00 00 00 00
1c: R_ARC_B26 .text
20: 01 00 1f 38 381f0001 jz 0 <text_label>
24: 00 00 00 00
24: R_ARC_B26 .text
28: 02 00 1f 38 381f0002 jnz 0 <text_label>
2c: 00 00 00 00
2c: R_ARC_B26 .text
30: 02 00 1f 38 381f0002 jnz 0 <text_label>
34: 00 00 00 00
34: R_ARC_B26 .text
38: 03 00 1f 38 381f0003 jp 0 <text_label>
3c: 00 00 00 00
3c: R_ARC_B26 .text
40: 03 00 1f 38 381f0003 jp 0 <text_label>
44: 00 00 00 00
44: R_ARC_B26 .text
48: 04 00 1f 38 381f0004 jn 0 <text_label>
4c: 00 00 00 00
4c: R_ARC_B26 .text
50: 04 00 1f 38 381f0004 jn 0 <text_label>
54: 00 00 00 00
54: R_ARC_B26 .text
58: 05 00 1f 38 381f0005 jc 0 <text_label>
5c: 00 00 00 00
5c: R_ARC_B26 .text
60: 05 00 1f 38 381f0005 jc 0 <text_label>
64: 00 00 00 00
64: R_ARC_B26 .text
68: 05 00 1f 38 381f0005 jc 0 <text_label>
6c: 00 00 00 00
6c: R_ARC_B26 .text
70: 06 00 1f 38 381f0006 jnc 0 <text_label>
74: 00 00 00 00
74: R_ARC_B26 .text
78: 06 00 1f 38 381f0006 jnc 0 <text_label>
7c: 00 00 00 00
7c: R_ARC_B26 .text
80: 06 00 1f 38 381f0006 jnc 0 <text_label>
84: 00 00 00 00
84: R_ARC_B26 .text
88: 07 00 1f 38 381f0007 jv 0 <text_label>
8c: 00 00 00 00
8c: R_ARC_B26 .text
90: 07 00 1f 38 381f0007 jv 0 <text_label>
94: 00 00 00 00
94: R_ARC_B26 .text
98: 08 00 1f 38 381f0008 jnv 0 <text_label>
9c: 00 00 00 00
9c: R_ARC_B26 .text
a0: 08 00 1f 38 381f0008 jnv 0 <text_label>
a4: 00 00 00 00
a4: R_ARC_B26 .text
a8: 09 00 1f 38 381f0009 jgt 0 <text_label>
ac: 00 00 00 00
ac: R_ARC_B26 .text
b0: 0a 00 1f 38 381f000a jge 0 <text_label>
b4: 00 00 00 00
b4: R_ARC_B26 .text
b8: 0b 00 1f 38 381f000b jlt 0 <text_label>
bc: 00 00 00 00
bc: R_ARC_B26 .text
c0: 0c 00 1f 38 381f000c jle 0 <text_label>
c4: 00 00 00 00
c4: R_ARC_B26 .text
c8: 0d 00 1f 38 381f000d jhi 0 <text_label>
cc: 00 00 00 00
cc: R_ARC_B26 .text
d0: 0e 00 1f 38 381f000e jls 0 <text_label>
d4: 00 00 00 00
d4: R_ARC_B26 .text
d8: 0f 00 1f 38 381f000f jpnz 0 <text_label>
dc: 00 00 00 00
dc: R_ARC_B26 .text
e0: 00 00 1f 38 381f0000 j 0 <text_label>
e4: 00 00 00 00
e4: R_ARC_B26 external_text_label
e8: 00 00 1f 38 381f0000 j 0 <text_label>
ec: 00 00 00 00

9
gas/testsuite/gas/arc/j.s
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@ -1,15 +1,6 @@
# j test
text_label:
j r0
j.d r0
j.jd r0
j.nd r0
j.f [r1]
j.d.f [r1]
j.jd.f [r1]
j.nd.f [r1]
j text_label
jal text_label

25
gas/testsuite/gas/arc/jl.d Normal file
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@ -0,0 +1,25 @@
#as: -EL -marc6
#objdump: -dr -EL
.*: +file format elf32-.*arc
Disassembly of section .text:
00000000 <text_label>:
0: 40 02 1f 38 381f0240 jl 0 <text_label>
4: 00 00 00 00
4: R_ARC_B26 .text
8: 40 03 1f 38 381f0340 jl.f 0 <text_label>
c: 00 00 00 00
c: R_ARC_B26 .text
10: 02 82 00 38 38008202 jlnz \[r1\]
14: 40 02 1f 38 381f0240 jl 0 <text_label>
18: 00 00 00 00
18: R_ARC_B26 .text
1c: 40 03 1f 38 381f0340 jl.f 0 <text_label>
20: 00 00 00 00
20: R_ARC_B26 .text

9
gas/testsuite/gas/arc/jl.s Normal file
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@ -0,0 +1,9 @@
# jl test
text_label:
jl text_label
jl.f text_label
jlnz.nd [r1]
jlal text_label
jlal.f text_label

35
gas/testsuite/gas/arc/ld.d
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@ -1,30 +1,13 @@
#objdump: -dr
#name: ld/lr
# Test the ld/lr insn.
#as: -EL
#objdump: -dr -EL
.*: +file format elf32-.*arc
Disassembly of section .text:
00000000 08008000 ld r0,\[r1\]
00000004 00418800 ld r2,\[r3,r4\]
00000008 08a30001 ld r5,\[r6,1\]
0000000c 08e401ff ld r7,\[r8,-1\]
00000010 092500ff ld r9,\[r10,255\]
00000014 09660100 ld r11,\[r12,-256\]
00000018 01a77c00 ld r13,\[r14,256\]
00000020 01e87c00 ld r15,\[r16,-257\]
00000028 023f3800 ld r17,\[305419896,sp\]
00000030 0a7f0000 ld r19,\[0\]
RELOC: 00000034 R_ARC_32 foo
00000038 0a9f0000 ld r20,\[4\]
RELOC: 0000003c R_ARC_32 foo
00000040 081f8400 ldb r0,\[0\]
00000044 081f8800 ldw r0,\[0\]
00000048 081f8200 ld.x r0,\[0\]
0000004c 081f9000 ld.a r0,\[0\]
00000050 081fc000 ld.di r0,\[0\]
00000054 08005600 ldb.x.a.di r0,\[r0\]
00000058 0800a000 lr r0,\[r1\]
0000005c 085fa000 lr r2,\[status\]
00000060 087f2000 lr r3,\[305419896\]
00000000 <.text>:
0: 00 84 00 00 00008400 ld r0,\[r1,r2\]
4: 02 84 00 00 00008402 ldb r0,\[r1,r2\]
8: 08 88 21 00 00218808 ld.a r1,\[r3,r4\]
c: 05 06 21 00 00210605 ldw.x r1,\[r2,r3\]
10: 0d 88 41 00 0041880d ldw.x.a r2,\[r3,r4\]

29
gas/testsuite/gas/arc/ld.s
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@ -1,24 +1,7 @@
# ld/lr test
# ld test
ld r0,[r1]
ld r2,[r3,r4]
ld r5,[r6,1]
ld r7,[r8,-1]
ld r9,[r10,255]
ld r11,[r12,-256]
ld r13,[r14,256]
ld r15,[r16,-257]
ld r17,[0x12345678,r28]
ld r19,[foo]
ld r20,[foo+4]
ldb r0,[0]
ldw r0,[0]
ld.x r0,[0]
ld.a r0,[0]
ld.di r0,[0]
ldb.x.a.di r0,[r0]
lr r0,[r1]
lr r2,[status]
lr r3,[0x12345678]
ld r0,[r1,r2]
ldb r0,[r1,r2]
ld.a r1,[r3,r4]
ldw.x r1,[r2,r3]
ldw.x.a r2,[r3,r4]

21
gas/testsuite/gas/arc/ld2.d Normal file
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@ -0,0 +1,21 @@
#as: -EL
#objdump: -dr -EL
.*: +file format elf32-.*arc
Disassembly of section .text:
00000000 <.text>:
0: 00 80 00 08 08008000 ld r0,\[r1\]
4: 01 00 a3 08 08a30001 ld r5,\[r6,1\]
8: 00 00 7f 0a 0a7f0000 ld r19,\[0\]
c: 00 00 00 00
c: R_ARC_32 foo
10: 0a 10 81 08 0881100a ld.a r4,\[r2,10\]
14: 00 00 3f 08 083f0000 ld r1,\[0x384\]
18: 84 03 00 00
1c: 0f 84 41 08 0841840f ldb r2,\[r3,15\]
20: fe 09 62 08 086209fe ldw r3,\[r4,-2\]
24: 00 20 21 08 08212000 lr r1,\[r2\]
28: 14 a0 3f 08 083fa014 lr r1,\[0x14\]
2c: 00 a0 1f 08 081fa000 lr r0,\[status\]

13
gas/testsuite/gas/arc/ld2.s Normal file
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@ -0,0 +1,13 @@
# ld/lr test
ld r0,[r1]
ld r5,[r6,1]
ld r19,[foo]
ld.a r4,[r2,10]
ld r1,[900]
ldb r2,[r3,15]
ldw r3,[r4,-2]
lr r1,[r2]
lr r1,[20]
lr r0,[status]

76
gas/testsuite/gas/arc/lp.d Normal file
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#as: -EL
#objdump: -dr -EL
.*: +file format elf32-.*arc
Disassembly of section .text:
00000000 <text_label>:
0: 80 ff ff 37 37ffff80 lp 0 <text_label>
4: 00 ff ff 37 37ffff00 lp 0 <text_label>
8: 80 fe ff 37 37fffe80 lp 0 <text_label>
c: 01 fe ff 37 37fffe01 lpz 0 <text_label>
10: 81 fd ff 37 37fffd81 lpz 0 <text_label>
14: 02 fd ff 37 37fffd02 lpnz 0 <text_label>
18: 82 fc ff 37 37fffc82 lpnz 0 <text_label>
1c: 03 fc ff 37 37fffc03 lpp 0 <text_label>
20: 83 fb ff 37 37fffb83 lpp 0 <text_label>
24: 04 fb ff 37 37fffb04 lpn 0 <text_label>
28: 84 fa ff 37 37fffa84 lpn 0 <text_label>
2c: 05 fa ff 37 37fffa05 lpc 0 <text_label>
30: 85 f9 ff 37 37fff985 lpc 0 <text_label>
34: 05 f9 ff 37 37fff905 lpc 0 <text_label>
38: 86 f8 ff 37 37fff886 lpnc 0 <text_label>
3c: 06 f8 ff 37 37fff806 lpnc 0 <text_label>
40: 86 f7 ff 37 37fff786 lpnc 0 <text_label>
44: 07 f7 ff 37 37fff707 lpv 0 <text_label>
48: 87 f6 ff 37 37fff687 lpv 0 <text_label>
4c: 08 f6 ff 37 37fff608 lpnv 0 <text_label>
50: 88 f5 ff 37 37fff588 lpnv 0 <text_label>
54: 09 f5 ff 37 37fff509 lpgt 0 <text_label>
58: 8a f4 ff 37 37fff48a lpge 0 <text_label>
5c: 0b f4 ff 37 37fff40b lplt 0 <text_label>
60: 8c f3 ff 37 37fff38c lple 0 <text_label>
64: 0d f3 ff 37 37fff30d lphi 0 <text_label>
68: 8e f2 ff 37 37fff28e lpls 0 <text_label>
6c: 0f f2 ff 37 37fff20f lppnz 0 <text_label>
70: a0 f1 ff 37 37fff1a0 lp.d 0 <text_label>
74: 00 f1 ff 37 37fff100 lp 0 <text_label>
78: c0 f0 ff 37 37fff0c0 lp.jd 0 <text_label>
7c: 21 f0 ff 37 37fff021 lpz.d 0 <text_label>
80: 82 ef ff 37 37ffef82 lpnz 0 <text_label>
84: 46 ef ff 37 37ffef46 lpnc.jd 0 <text_label>

40
gas/testsuite/gas/arc/lp.s Normal file
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# lp test
text_label:
lp text_label
lpal text_label
lpra text_label
lpeq text_label
lpz text_label
lpne text_label
lpnz text_label
lppl text_label
lpp text_label
lpmi text_label
lpn text_label
lpcs text_label
lpc text_label
lplo text_label
lpcc text_label
lpnc text_label
lphs text_label
lpvs text_label
lpv text_label
lpvc text_label
lpnv text_label
lpgt text_label
lpge text_label
lplt text_label
lple text_label
lphi text_label
lpls text_label
lppnz text_label
lp.d text_label
lp.nd text_label
lp.jd text_label
lpeq.d text_label
lpne.nd text_label
lpcc.jd text_label

51
gas/testsuite/gas/arc/lsr.d Normal file
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@ -0,0 +1,51 @@
#as: -EL
#objdump: -dr -EL
.*: +file format elf32-.*arc
Disassembly of section .text:
00000000 <.text>:
0: 00 84 00 18 18008400 lsr r0,r1
4: 00 04 6e 1b 1b6e0400 lsr fp,sp
8: 00 84 1f 18 181f8400 lsr r0,0
c: ff 85 3f 18 183f85ff lsr r1,-1
10: 00 04 e1 1f 1fe10400 lsr 0,r2
14: 00 84 e1 1f 1fe18400 lsr 0,r3
18: ff 84 9f 18 189f84ff lsr r4,255
1c: 00 84 e2 1f 1fe28400 lsr 0,r5
20: 00 85 df 18 18df8500 lsr r6,-256
24: 00 84 e3 1f 1fe38400 lsr 0,r7
28: 00 04 1f 19 191f0400 lsr r8,0x100
2c: 00 01 00 00
30: 00 04 3f 19 193f0400 lsr r9,0xffff_feff
34: ff fe ff ff
38: 00 04 7f 19 197f0400 lsr r11,0x4242_4242
3c: 42 42 42 42
40: 00 04 ff 1f 1fff0400 lsr 0,0x100
44: 00 01 00 00
48: 00 04 1f 18 181f0400 lsr r0,0
4c: 00 00 00 00
4c: R_ARC_32 foo
50: 01 84 45 19 19458401 lsr.z r10,r11
54: 02 84 86 19 19868402 lsr.nz r12,r13
58: 0b 04 df 19 19df040b lsr.lt r14,0
5c: 00 00 00 00
60: 09 04 ff 19 19ff0409 lsr.gt r15,0x200
64: 00 02 00 00
68: 00 85 00 18 18008500 lsr.f r0,r1
6c: 01 84 5e 18 185e8401 lsr.f r2,1
70: 00 05 e2 1f 1fe20500 lsr.f 0,r4
74: 00 05 bf 18 18bf0500 lsr.f r5,0x200
78: 00 02 00 00
7c: 00 05 df 1f 1fdf0500 lsr.f 0,0x200
80: 00 02 00 00
84: 01 85 00 18 18008501 lsr.z.f r0,r1
88: 02 05 3f 18 183f0502 lsr.nz.f r1,0
8c: 00 00 00 00
90: 0b 05 c1 1f 1fc1050b lsr.lt.f 0,r2
94: 00 00 00 00 00000000
98: 0c 05 1f 18 181f050c lsr.le.f r0,0x200
9c: 00 02 00 00
a0: 04 05 df 1f 1fdf0504 lsr.n.f 0,0x200
a4: 00 02 00 00

38
gas/testsuite/gas/arc/lsr.s Normal file
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@ -0,0 +1,38 @@
# lsr test
lsr r0,r1
lsr fp,sp
lsr r0,0
lsr r1,-1
lsr 0,r2
lsr -1,r3
lsr r4,255
lsr 255,r5
lsr r6,-256
lsr -256,r7
lsr r8,256
lsr r9,-257
lsr r11,0x42424242
lsr 255,256
lsr r0,foo
lsr.eq r10,r11
lsr.ne r12,r13
lsr.lt r14,0
lsr.gt r15,512
lsr.f r0,r1
lsr.f r2,1
lsr.f 0,r4
lsr.f r5,512
lsr.f 512,512
lsr.eq.f r0,r1
lsr.ne.f r1,0
lsr.lt.f 0,r2
lsr.le.f r0,512
lsr.n.f 512,512

68
gas/testsuite/gas/arc/mov.d Normal file
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@ -0,0 +1,68 @@
#as: -EL
#objdump: -dr -EL
.*: +file format elf32-.*arc
Disassembly of section .text:
00000000 <.text>:
0: 00 82 00 60 60008200 mov r0,r1
4: 00 38 6e 63 636e3800 mov fp,sp
8: 00 fe 1f 60 601ffe00 mov r0,0
c: ff ff 3f 60 603fffff mov r1,-1
10: 00 04 e1 67 67e10400 mov 0,r2
14: 00 86 e1 67 67e18600 mov 0,r3
18: ff fe 9f 60 609ffeff mov r4,255
1c: 00 8a e2 67 67e28a00 mov 0,r5
20: 00 ff df 60 60dfff00 mov r6,-256
24: 00 8e e3 67 67e38e00 mov 0,r7
28: 00 7c 1f 61 611f7c00 mov r8,0x100
2c: 00 01 00 00
30: 00 7c 3f 61 613f7c00 mov r9,0xffff_feff
34: ff fe ff ff
38: 00 7c 7f 61 617f7c00 mov r11,0x4242_4242
3c: 42 42 42 42
40: 00 7c ff 67 67ff7c00 mov 0,0x100
44: 00 01 00 00
48: 00 7c 1f 60 601f7c00 mov r0,0
4c: 00 00 00 00
4c: R_ARC_32 foo
50: 00 82 00 60 60008200 mov r0,r1
54: 00 08 62 60 60620800 mov r3,r4
58: 01 8e c3 60 60c38e01 mov.z r6,r7
5c: 01 14 25 61 61251401 mov.z r9,r10
60: 02 9a 86 61 61869a02 mov.nz r12,r13
64: 02 20 e8 61 61e82002 mov.nz r15,r16
68: 03 a6 49 62 6249a603 mov.p r18,r19
6c: 03 2c ab 62 62ab2c03 mov.p r21,r22
70: 04 b2 0c 63 630cb204 mov.n r24,r25
74: 04 38 6e 63 636e3804 mov.n fp,sp
78: 05 be cf 63 63cfbe05 mov.c ilink2,blink
7c: 05 44 31 64 64314405 mov.c r33,r34
80: 05 ca 92 64 6492ca05 mov.c r36,r37
84: 06 50 f4 64 64f45006 mov.nc r39,r40
88: 06 d6 55 65 6555d606 mov.nc r42,r43
8c: 06 5c b7 65 65b75c06 mov.nc r45,r46
90: 07 e2 18 66 6618e207 mov.v r48,r49
94: 07 64 39 66 66396407 mov.v r49,r50
98: 08 ee 3b 66 663bee08 mov.nv r49,r55
9c: 08 74 3d 66 663d7408 mov.nv r49,r58
a0: 09 78 9e 67 679e7809 mov.gt lp_count,lp_count
a4: 0a 7c 1f 60 601f7c0a mov.ge r0,0
a8: 00 00 00 00
ac: 0c 7c df 67 67df7c0c mov.le 0,2
b0: 02 00 00 00
b4: 0d 86 61 60 6061860d mov.hi r3,r3
b8: 0e 08 82 60 6082080e mov.ls r4,r4
bc: 0f 8a a2 60 60a28a0f mov.pnz r5,r5
c0: 00 83 00 60 60008300 mov.f r0,r1
c4: 01 fa 5e 60 605efa01 mov.f r2,1
c8: 00 87 e1 67 67e18700 mov.f 0,r3
cc: 00 09 e2 67 67e20900 mov.f 0,r4
d0: 00 7d bf 60 60bf7d00 mov.f r5,0x200
d4: 00 02 00 00
d8: 00 7d df 67 67df7d00 mov.f 0,0x200
dc: 00 02 00 00
e0: 01 83 00 60 60008301 mov.z.f r0,r1
e4: 02 7d 3f 60 603f7d02 mov.nz.f r1,0
e8: 00 00 00 00

58
gas/testsuite/gas/arc/mov.s Normal file
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# mov test
mov r0,r1
mov fp,sp
mov r0,0
mov r1,-1
mov 0,r2
mov -1,r3
mov r4,255
mov 255,r5
mov r6,-256
mov -256,r7
mov r8,256
mov r9,-257
mov r11,0x42424242
mov 255,256
mov r0,foo
mov.al r0,r1
mov.ra r3,r4
mov.eq r6,r7
mov.z r9,r10
mov.ne r12,r13
mov.nz r15,r16
mov.pl r18,r19
mov.p r21,r22
mov.mi r24,r25
mov.n r27,r28
mov.cs r30,r31
mov.c r33,r34
mov.lo r36,r37
mov.cc r39,r40
mov.nc r42,r43
mov.hs r45,r46
mov.vs r48,r49
mov.v r49,r50
mov.vc r49,r55
mov.nv r49,r58
mov.gt r60,r60
mov.ge r0,0
mov.le 2,2
mov.hi r3,r3
mov.ls r4,r4
mov.pnz r5,r5
mov.f r0,r1
mov.f r2,1
mov.f 1,r3
mov.f 0,r4
mov.f r5,512
mov.f 512,512
mov.eq.f r0,r1
mov.ne.f r1,0

9
gas/testsuite/gas/arc/nop.d Normal file
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#as: -EL
#objdump: -dr -EL
.*: +file format elf32-.*arc
Disassembly of section .text:
00000000 <.text>:
0: ff ff ff 7f 7fffffff nop

3
gas/testsuite/gas/arc/nop.s Normal file
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# nop test
nop

85
gas/testsuite/gas/arc/or.d Normal file
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#as: -EL
#objdump: -dr -EL
.*: +file format elf32-.*arc
Disassembly of section .text:
00000000 <.text>:
0: 00 84 00 68 68008400 or r0,r1,r2
4: 00 b8 4d 6b 6b4db800 or gp,fp,sp
8: 00 3e af 6b 6baf3e00 or ilink1,ilink2,blink
c: 00 f8 1d 6f 6f1df800 or r56,r59,lp_count
10: 00 fe 00 68 6800fe00 or r0,r1,0
14: 00 84 1f 68 681f8400 or r0,0,r2
18: 00 84 e0 6f 6fe08400 or 0,r1,r2
1c: ff ff 00 68 6800ffff or r0,r1,-1
20: ff 85 1f 68 681f85ff or r0,-1,r2
24: 00 84 e0 6f 6fe08400 or 0,r1,r2
28: ff fe 00 68 6800feff or r0,r1,255
2c: ff 84 1f 68 681f84ff or r0,255,r2
30: 00 84 e0 6f 6fe08400 or 0,r1,r2
34: 00 ff 00 68 6800ff00 or r0,r1,-256
38: 00 85 1f 68 681f8500 or r0,-256,r2
3c: 00 84 e0 6f 6fe08400 or 0,r1,r2
40: 00 fc 00 68 6800fc00 or r0,r1,0x100
44: 00 01 00 00
48: 00 04 1f 68 681f0400 or r0,0xffff_feff,r2
4c: ff fe ff ff
50: ff fc 1f 68 681ffcff or r0,255,0x100
54: 00 01 00 00
58: ff 7e 1f 68 681f7eff or r0,0x100,255
5c: 00 01 00 00
60: 00 fc 00 68 6800fc00 or r0,r1,0
64: 00 00 00 00
64: R_ARC_32 foo
68: 00 84 00 68 68008400 or r0,r1,r2
6c: 00 0a 62 68 68620a00 or r3,r4,r5
70: 01 90 c3 68 68c39001 or.z r6,r7,r8
74: 01 16 25 69 69251601 or.z r9,r10,r11
78: 02 9c 86 69 69869c02 or.nz r12,r13,r14
7c: 02 22 e8 69 69e82202 or.nz r15,r16,r17
80: 03 a8 49 6a 6a49a803 or.p r18,r19,r20
84: 03 2e ab 6a 6aab2e03 or.p r21,r22,r23
88: 04 b4 0c 6b 6b0cb404 or.n r24,r25,gp
8c: 04 3a 6e 6b 6b6e3a04 or.n fp,sp,ilink1
90: 05 c0 cf 6b 6bcfc005 or.c ilink2,blink,r32
94: 05 46 31 6c 6c314605 or.c r33,r34,r35
98: 05 cc 92 6c 6c92cc05 or.c r36,r37,r38
9c: 06 52 f4 6c 6cf45206 or.nc r39,r40,r41
a0: 06 d8 55 6d 6d55d806 or.nc r42,r43,r44
a4: 06 5e b7 6d 6db75e06 or.nc r45,r46,r47
a8: 07 e4 18 6e 6e18e407 or.v r48,r49,r50
ac: 07 6a 1a 6f 6f1a6a07 or.v r56,r52,r53
b0: 08 f0 1b 6f 6f1bf008 or.nv r56,r55,r56
b4: 08 76 1d 6f 6f1d7608 or.nv r56,r58,r59
b8: 09 00 9e 6f 6f9e0009 or.gt lp_count,lp_count,r0
bc: 0a 7c 00 68 68007c0a or.ge r0,r0,0
c0: 00 00 00 00
c4: 0b 02 3f 68 683f020b or.lt r1,1,r1
c8: 01 00 00 00
cc: 0d 06 7f 68 687f060d or.hi r3,3,r3
d0: 03 00 00 00
d4: 0e 08 df 6f 6fdf080e or.ls 0,4,r4
d8: 04 00 00 00
dc: 0f fc c2 6f 6fc2fc0f or.pnz 0,r5,5
e0: 05 00 00 00
e4: 00 85 00 68 68008500 or.f r0,r1,r2
e8: 01 fa 00 68 6800fa01 or.f r0,r1,1
ec: 01 84 1e 68 681e8401 or.f r0,1,r2
f0: 00 85 e0 6f 6fe08500 or.f 0,r1,r2
f4: 00 fd 00 68 6800fd00 or.f r0,r1,0x200
f8: 00 02 00 00
fc: 00 05 1f 68 681f0500 or.f r0,0x200,r2
100: 00 02 00 00
104: 01 85 00 68 68008501 or.z.f r0,r1,r2
108: 02 fd 00 68 6800fd02 or.nz.f r0,r1,0
10c: 00 00 00 00
110: 0b 05 1f 68 681f050b or.lt.f r0,0,r2
114: 00 00 00 00
118: 09 85 c0 6f 6fc08509 or.gt.f 0,r1,r2
11c: 00 00 00 00 00000000
120: 0c fd 00 68 6800fd0c or.le.f r0,r1,0x200
124: 00 02 00 00
128: 0a 05 1f 68 681f050a or.ge.f r0,0x200,r2
12c: 00 02 00 00

68
gas/testsuite/gas/arc/or.s Normal file
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# or test
or r0,r1,r2
or r26,fp,sp
or ilink1,ilink2,blink
or r56,r59,lp_count
or r0,r1,0
or r0,0,r2
or 0,r1,r2
or r0,r1,-1
or r0,-1,r2
or -1,r1,r2
or r0,r1,255
or r0,255,r2
or 255,r1,r2
or r0,r1,-256
or r0,-256,r2
or -256,r1,r2
or r0,r1,256
or r0,-257,r2
or r0,255,256
or r0,256,255
or r0,r1,foo
or.al r0,r1,r2
or.ra r3,r4,r5
or.eq r6,r7,r8
or.z r9,r10,r11
or.ne r12,r13,r14
or.nz r15,r16,r17
or.pl r18,r19,r20
or.p r21,r22,r23
or.mi r24,r25,r26
or.n r27,r28,r29
or.cs r30,r31,r32
or.c r33,r34,r35
or.lo r36,r37,r38
or.cc r39,r40,r41
or.nc r42,r43,r44
or.hs r45,r46,r47
or.vs r48,r49,r50
or.v r56,r52,r53
or.vc r56,r55,r56
or.nv r56,r58,r59
or.gt r60,r60,r0
or.ge r0,r0,0
or.lt r1,1,r1
or.hi r3,3,r3
or.ls 4,4,r4
or.pnz 5,r5,5
or.f r0,r1,r2
or.f r0,r1,1
or.f r0,1,r2
or.f 0,r1,r2
or.f r0,r1,512
or.f r0,512,r2
or.eq.f r0,r1,r2
or.ne.f r0,r1,0
or.lt.f r0,0,r2
or.gt.f 0,r1,r2
or.le.f r0,r1,512
or.ge.f r0,512,r2

68
gas/testsuite/gas/arc/rlc.d Normal file
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#as: -EL
#objdump: -dr -EL
.*: +file format elf32-.*arc
Disassembly of section .text:
00000000 <.text>:
0: 00 82 00 48 48008200 rlc r0,r1
4: 00 38 6e 4b 4b6e3800 rlc fp,sp
8: 00 fe 1f 48 481ffe00 rlc r0,0
c: ff ff 3f 48 483fffff rlc r1,-1
10: 00 04 e1 4f 4fe10400 rlc 0,r2
14: 00 86 e1 4f 4fe18600 rlc 0,r3
18: ff fe 9f 48 489ffeff rlc r4,255
1c: 00 8a e2 4f 4fe28a00 rlc 0,r5
20: 00 ff df 48 48dfff00 rlc r6,-256
24: 00 8e e3 4f 4fe38e00 rlc 0,r7
28: 00 7c 1f 49 491f7c00 rlc r8,0x100
2c: 00 01 00 00
30: 00 7c 3f 49 493f7c00 rlc r9,0xffff_feff
34: ff fe ff ff
38: 00 7c 7f 49 497f7c00 rlc r11,0x4242_4242
3c: 42 42 42 42
40: 00 7c ff 4f 4fff7c00 rlc 0,0x100
44: 00 01 00 00
48: 00 7c 1f 48 481f7c00 rlc r0,0
4c: 00 00 00 00
4c: R_ARC_32 foo
50: 00 82 00 48 48008200 rlc r0,r1
54: 00 08 62 48 48620800 rlc r3,r4
58: 01 8e c3 48 48c38e01 rlc.z r6,r7
5c: 01 14 25 49 49251401 rlc.z r9,r10
60: 02 9a 86 49 49869a02 rlc.nz r12,r13
64: 02 20 e8 49 49e82002 rlc.nz r15,r16
68: 03 a6 49 4a 4a49a603 rlc.p r18,r19
6c: 03 2c ab 4a 4aab2c03 rlc.p r21,r22
70: 04 b2 0c 4b 4b0cb204 rlc.n r24,r25
74: 04 38 6e 4b 4b6e3804 rlc.n fp,sp
78: 05 be cf 4b 4bcfbe05 rlc.c ilink2,blink
7c: 05 44 31 4c 4c314405 rlc.c r33,r34
80: 05 ca 92 4c 4c92ca05 rlc.c r36,r37
84: 06 50 f4 4c 4cf45006 rlc.nc r39,r40
88: 06 d6 55 4d 4d55d606 rlc.nc r42,r43
8c: 06 5c b7 4d 4db75c06 rlc.nc r45,r46
90: 07 e2 18 4e 4e18e207 rlc.v r48,r49
94: 07 64 39 4e 4e396407 rlc.v r49,r50
98: 08 ee 3b 4e 4e3bee08 rlc.nv r49,r55
9c: 08 74 3d 4e 4e3d7408 rlc.nv r49,r58
a0: 09 78 9e 4f 4f9e7809 rlc.gt lp_count,lp_count
a4: 0a 7c 1f 48 481f7c0a rlc.ge r0,0
a8: 00 00 00 00
ac: 0c 7c df 4f 4fdf7c0c rlc.le 0,2
b0: 02 00 00 00
b4: 0d 86 61 48 4861860d rlc.hi r3,r3
b8: 0e 08 82 48 4882080e rlc.ls r4,r4
bc: 0f 8a a2 48 48a28a0f rlc.pnz r5,r5
c0: 00 83 00 48 48008300 rlc.f r0,r1
c4: 01 fa 5e 48 485efa01 rlc.f r2,1
c8: 00 87 e1 4f 4fe18700 rlc.f 0,r3
cc: 00 09 e2 4f 4fe20900 rlc.f 0,r4
d0: 00 7d bf 48 48bf7d00 rlc.f r5,0x200
d4: 00 02 00 00
d8: 00 7d df 4f 4fdf7d00 rlc.f 0,0x200
dc: 00 02 00 00
e0: 01 83 00 48 48008301 rlc.z.f r0,r1
e4: 02 7d 3f 48 483f7d02 rlc.nz.f r1,0
e8: 00 00 00 00

58
gas/testsuite/gas/arc/rlc.s Normal file
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# rlc test
rlc r0,r1
rlc fp,sp
rlc r0,0
rlc r1,-1
rlc 0,r2
rlc -1,r3
rlc r4,255
rlc 255,r5
rlc r6,-256
rlc -256,r7
rlc r8,256
rlc r9,-257
rlc r11,0x42424242
rlc 255,256
rlc r0,foo
rlc.al r0,r1
rlc.ra r3,r4
rlc.eq r6,r7
rlc.z r9,r10
rlc.ne r12,r13
rlc.nz r15,r16
rlc.pl r18,r19
rlc.p r21,r22
rlc.mi r24,r25
rlc.n r27,r28
rlc.cs r30,r31
rlc.c r33,r34
rlc.lo r36,r37
rlc.cc r39,r40
rlc.nc r42,r43
rlc.hs r45,r46
rlc.vs r48,r49
rlc.v r49,r50
rlc.vc r49,r55
rlc.nv r49,r58
rlc.gt r60,r60
rlc.ge r0,0
rlc.le 2,2
rlc.hi r3,r3
rlc.ls r4,r4
rlc.pnz r5,r5
rlc.f r0,r1
rlc.f r2,1
rlc.f 1,r3
rlc.f 0,r4
rlc.f r5,512
rlc.f 512,512
rlc.eq.f r0,r1
rlc.ne.f r1,0

51
gas/testsuite/gas/arc/ror.d Normal file
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#as: -EL
#objdump: -dr -EL
.*: +file format elf32-.*arc
Disassembly of section .text:
00000000 <.text>:
0: 00 86 00 18 18008600 ror r0,r1
4: 00 06 6e 1b 1b6e0600 ror fp,sp
8: 00 86 1f 18 181f8600 ror r0,0
c: ff 87 3f 18 183f87ff ror r1,-1
10: 00 06 e1 1f 1fe10600 ror 0,r2
14: 00 86 e1 1f 1fe18600 ror 0,r3
18: ff 86 9f 18 189f86ff ror r4,255
1c: 00 86 e2 1f 1fe28600 ror 0,r5
20: 00 87 df 18 18df8700 ror r6,-256
24: 00 86 e3 1f 1fe38600 ror 0,r7
28: 00 06 1f 19 191f0600 ror r8,0x100
2c: 00 01 00 00
30: 00 06 3f 19 193f0600 ror r9,0xffff_feff
34: ff fe ff ff
38: 00 06 7f 19 197f0600 ror r11,0x4242_4242
3c: 42 42 42 42
40: 00 06 ff 1f 1fff0600 ror 0,0x100
44: 00 01 00 00
48: 00 06 1f 18 181f0600 ror r0,0
4c: 00 00 00 00
4c: R_ARC_32 foo
50: 01 86 45 19 19458601 ror.z r10,r11
54: 02 86 86 19 19868602 ror.nz r12,r13
58: 0b 06 df 19 19df060b ror.lt r14,0
5c: 00 00 00 00
60: 09 06 ff 19 19ff0609 ror.gt r15,0x200
64: 00 02 00 00
68: 00 87 00 18 18008700 ror.f r0,r1
6c: 01 86 5e 18 185e8601 ror.f r2,1
70: 00 07 e2 1f 1fe20700 ror.f 0,r4
74: 00 07 bf 18 18bf0700 ror.f r5,0x200
78: 00 02 00 00
7c: 00 07 df 1f 1fdf0700 ror.f 0,0x200
80: 00 02 00 00
84: 01 87 00 18 18008701 ror.z.f r0,r1
88: 02 07 3f 18 183f0702 ror.nz.f r1,0
8c: 00 00 00 00
90: 0b 07 c1 1f 1fc1070b ror.lt.f 0,r2
94: 00 00 00 00 00000000
98: 0c 07 1f 18 181f070c ror.le.f r0,0x200
9c: 00 02 00 00
a0: 04 07 df 1f 1fdf0704 ror.n.f 0,0x200
a4: 00 02 00 00

38
gas/testsuite/gas/arc/ror.s Normal file
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# ror test
ror r0,r1
ror fp,sp
ror r0,0
ror r1,-1
ror 0,r2
ror -1,r3
ror r4,255
ror 255,r5
ror r6,-256
ror -256,r7
ror r8,256
ror r9,-257
ror r11,0x42424242
ror 255,256
ror r0,foo
ror.eq r10,r11
ror.ne r12,r13
ror.lt r14,0
ror.gt r15,512
ror.f r0,r1
ror.f r2,1
ror.f 0,r4
ror.f r5,512
ror.f 512,512
ror.eq.f r0,r1
ror.ne.f r1,0
ror.lt.f 0,r2
ror.le.f r0,512
ror.n.f 512,512

51
gas/testsuite/gas/arc/rrc.d Normal file
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#as: -EL
#objdump: -dr -EL
.*: +file format elf32-.*arc
Disassembly of section .text:
00000000 <.text>:
0: 00 88 00 18 18008800 rrc r0,r1
4: 00 08 6e 1b 1b6e0800 rrc fp,sp
8: 00 88 1f 18 181f8800 rrc r0,0
c: ff 89 3f 18 183f89ff rrc r1,-1
10: 00 08 e1 1f 1fe10800 rrc 0,r2
14: 00 88 e1 1f 1fe18800 rrc 0,r3
18: ff 88 9f 18 189f88ff rrc r4,255
1c: 00 88 e2 1f 1fe28800 rrc 0,r5
20: 00 89 df 18 18df8900 rrc r6,-256
24: 00 88 e3 1f 1fe38800 rrc 0,r7
28: 00 08 1f 19 191f0800 rrc r8,0x100
2c: 00 01 00 00
30: 00 08 3f 19 193f0800 rrc r9,0xffff_feff
34: ff fe ff ff
38: 00 08 7f 19 197f0800 rrc r11,0x4242_4242
3c: 42 42 42 42
40: 00 08 ff 1f 1fff0800 rrc 0,0x100
44: 00 01 00 00
48: 00 08 1f 18 181f0800 rrc r0,0
4c: 00 00 00 00
4c: R_ARC_32 foo
50: 01 88 45 19 19458801 rrc.z r10,r11
54: 02 88 86 19 19868802 rrc.nz r12,r13
58: 0b 08 df 19 19df080b rrc.lt r14,0
5c: 00 00 00 00
60: 09 08 ff 19 19ff0809 rrc.gt r15,0x200
64: 00 02 00 00
68: 00 89 00 18 18008900 rrc.f r0,r1
6c: 01 88 5e 18 185e8801 rrc.f r2,1
70: 00 09 e2 1f 1fe20900 rrc.f 0,r4
74: 00 09 bf 18 18bf0900 rrc.f r5,0x200
78: 00 02 00 00
7c: 00 09 df 1f 1fdf0900 rrc.f 0,0x200
80: 00 02 00 00
84: 01 89 00 18 18008901 rrc.z.f r0,r1
88: 02 09 3f 18 183f0902 rrc.nz.f r1,0
8c: 00 00 00 00
90: 0b 09 c1 1f 1fc1090b rrc.lt.f 0,r2
94: 00 00 00 00 00000000
98: 0c 09 1f 18 181f090c rrc.le.f r0,0x200
9c: 00 02 00 00
a0: 04 09 df 1f 1fdf0904 rrc.n.f 0,0x200
a4: 00 02 00 00

38
gas/testsuite/gas/arc/rrc.s Normal file
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# rrc test
rrc r0,r1
rrc fp,sp
rrc r0,0
rrc r1,-1
rrc 0,r2
rrc -1,r3
rrc r4,255
rrc 255,r5
rrc r6,-256
rrc -256,r7
rrc r8,256
rrc r9,-257
rrc r11,0x42424242
rrc 255,256
rrc r0,foo
rrc.eq r10,r11
rrc.ne r12,r13
rrc.lt r14,0
rrc.gt r15,512
rrc.f r0,r1
rrc.f r2,1
rrc.f 0,r4
rrc.f r5,512
rrc.f 512,512
rrc.eq.f r0,r1
rrc.ne.f r1,0
rrc.lt.f 0,r2
rrc.le.f r0,512
rrc.n.f 512,512

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gas/testsuite/gas/arc/sbc.d Normal file
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#as: -EL
#objdump: -dr -EL
.*: +file format elf32-.*arc
Disassembly of section .text:
00000000 <.text>:
0: 00 84 00 58 58008400 sbc r0,r1,r2
4: 00 b8 4d 5b 5b4db800 sbc gp,fp,sp
8: 00 3e af 5b 5baf3e00 sbc ilink1,ilink2,blink
c: 00 f8 1d 5f 5f1df800 sbc r56,r59,lp_count
10: 00 fe 00 58 5800fe00 sbc r0,r1,0
14: 00 84 1f 58 581f8400 sbc r0,0,r2
18: 00 84 e0 5f 5fe08400 sbc 0,r1,r2
1c: ff ff 00 58 5800ffff sbc r0,r1,-1
20: ff 85 1f 58 581f85ff sbc r0,-1,r2
24: 00 84 e0 5f 5fe08400 sbc 0,r1,r2
28: ff fe 00 58 5800feff sbc r0,r1,255
2c: ff 84 1f 58 581f84ff sbc r0,255,r2
30: 00 84 e0 5f 5fe08400 sbc 0,r1,r2
34: 00 ff 00 58 5800ff00 sbc r0,r1,-256
38: 00 85 1f 58 581f8500 sbc r0,-256,r2
3c: 00 84 e0 5f 5fe08400 sbc 0,r1,r2
40: 00 fc 00 58 5800fc00 sbc r0,r1,0x100
44: 00 01 00 00
48: 00 04 1f 58 581f0400 sbc r0,0xffff_feff,r2
4c: ff fe ff ff
50: ff fc 1f 58 581ffcff sbc r0,255,0x100
54: 00 01 00 00
58: ff 7e 1f 58 581f7eff sbc r0,0x100,255
5c: 00 01 00 00
60: 00 fc 00 58 5800fc00 sbc r0,r1,0
64: 00 00 00 00
64: R_ARC_32 foo
68: 00 84 00 58 58008400 sbc r0,r1,r2
6c: 00 0a 62 58 58620a00 sbc r3,r4,r5
70: 01 90 c3 58 58c39001 sbc.z r6,r7,r8
74: 01 16 25 59 59251601 sbc.z r9,r10,r11
78: 02 9c 86 59 59869c02 sbc.nz r12,r13,r14
7c: 02 22 e8 59 59e82202 sbc.nz r15,r16,r17
80: 03 a8 49 5a 5a49a803 sbc.p r18,r19,r20
84: 03 2e ab 5a 5aab2e03 sbc.p r21,r22,r23
88: 04 b4 0c 5b 5b0cb404 sbc.n r24,r25,gp
8c: 04 3a 6e 5b 5b6e3a04 sbc.n fp,sp,ilink1
90: 05 c0 cf 5b 5bcfc005 sbc.c ilink2,blink,r32
94: 05 46 31 5c 5c314605 sbc.c r33,r34,r35
98: 05 cc 92 5c 5c92cc05 sbc.c r36,r37,r38
9c: 06 52 f4 5c 5cf45206 sbc.nc r39,r40,r41
a0: 06 d8 55 5d 5d55d806 sbc.nc r42,r43,r44
a4: 06 5e b7 5d 5db75e06 sbc.nc r45,r46,r47
a8: 07 e4 18 5e 5e18e407 sbc.v r48,r49,r50
ac: 07 6a 1a 5f 5f1a6a07 sbc.v r56,r52,r53
b0: 08 f0 1b 5f 5f1bf008 sbc.nv r56,r55,r56
b4: 08 76 1d 5f 5f1d7608 sbc.nv r56,r58,r59
b8: 09 00 9e 5f 5f9e0009 sbc.gt lp_count,lp_count,r0
bc: 0a 7c 00 58 58007c0a sbc.ge r0,r0,0
c0: 00 00 00 00
c4: 0b 02 3f 58 583f020b sbc.lt r1,1,r1
c8: 01 00 00 00
cc: 0d 06 7f 58 587f060d sbc.hi r3,3,r3
d0: 03 00 00 00
d4: 0e 08 df 5f 5fdf080e sbc.ls 0,4,r4
d8: 04 00 00 00
dc: 0f fc c2 5f 5fc2fc0f sbc.pnz 0,r5,5
e0: 05 00 00 00
e4: 00 85 00 58 58008500 sbc.f r0,r1,r2
e8: 01 fa 00 58 5800fa01 sbc.f r0,r1,1
ec: 01 84 1e 58 581e8401 sbc.f r0,1,r2
f0: 00 85 e0 5f 5fe08500 sbc.f 0,r1,r2
f4: 00 fd 00 58 5800fd00 sbc.f r0,r1,0x200
f8: 00 02 00 00
fc: 00 05 1f 58 581f0500 sbc.f r0,0x200,r2
100: 00 02 00 00
104: 01 85 00 58 58008501 sbc.z.f r0,r1,r2
108: 02 fd 00 58 5800fd02 sbc.nz.f r0,r1,0
10c: 00 00 00 00
110: 0b 05 1f 58 581f050b sbc.lt.f r0,0,r2
114: 00 00 00 00
118: 09 85 c0 5f 5fc08509 sbc.gt.f 0,r1,r2
11c: 00 00 00 00 00000000
120: 0c fd 00 58 5800fd0c sbc.le.f r0,r1,0x200
124: 00 02 00 00
128: 0a 05 1f 58 581f050a sbc.ge.f r0,0x200,r2
12c: 00 02 00 00

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gas/testsuite/gas/arc/sbc.s Normal file
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# sbc test
sbc r0,r1,r2
sbc r26,fp,sp
sbc ilink1,ilink2,blink
sbc r56,r59,lp_count
sbc r0,r1,0
sbc r0,0,r2
sbc 0,r1,r2
sbc r0,r1,-1
sbc r0,-1,r2
sbc -1,r1,r2
sbc r0,r1,255
sbc r0,255,r2
sbc 255,r1,r2
sbc r0,r1,-256
sbc r0,-256,r2
sbc -256,r1,r2
sbc r0,r1,256
sbc r0,-257,r2
sbc r0,255,256
sbc r0,256,255
sbc r0,r1,foo
sbc.al r0,r1,r2
sbc.ra r3,r4,r5
sbc.eq r6,r7,r8
sbc.z r9,r10,r11
sbc.ne r12,r13,r14
sbc.nz r15,r16,r17
sbc.pl r18,r19,r20
sbc.p r21,r22,r23
sbc.mi r24,r25,r26
sbc.n r27,r28,r29
sbc.cs r30,r31,r32
sbc.c r33,r34,r35
sbc.lo r36,r37,r38
sbc.cc r39,r40,r41
sbc.nc r42,r43,r44
sbc.hs r45,r46,r47
sbc.vs r48,r49,r50
sbc.v r56,r52,r53
sbc.vc r56,r55,r56
sbc.nv r56,r58,r59
sbc.gt r60,r60,r0
sbc.ge r0,r0,0
sbc.lt r1,1,r1
sbc.hi r3,3,r3
sbc.ls 4,4,r4
sbc.pnz 5,r5,5
sbc.f r0,r1,r2
sbc.f r0,r1,1
sbc.f r0,1,r2
sbc.f 0,r1,r2
sbc.f r0,r1,512
sbc.f r0,512,r2
sbc.eq.f r0,r1,r2
sbc.ne.f r0,r1,0
sbc.lt.f r0,0,r2
sbc.gt.f 0,r1,r2
sbc.le.f r0,r1,512
sbc.ge.f r0,512,r2

51
gas/testsuite/gas/arc/sexb.d Normal file
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#as: -EL
#objdump: -dr -EL
.*: +file format elf32-.*arc
Disassembly of section .text:
00000000 <.text>:
0: 00 8a 00 18 18008a00 sexb r0,r1
4: 00 0a 6e 1b 1b6e0a00 sexb fp,sp
8: 00 8a 1f 18 181f8a00 sexb r0,0
c: ff 8b 3f 18 183f8bff sexb r1,-1
10: 00 0a e1 1f 1fe10a00 sexb 0,r2
14: 00 8a e1 1f 1fe18a00 sexb 0,r3
18: ff 8a 9f 18 189f8aff sexb r4,255
1c: 00 8a e2 1f 1fe28a00 sexb 0,r5
20: 00 8b df 18 18df8b00 sexb r6,-256
24: 00 8a e3 1f 1fe38a00 sexb 0,r7
28: 00 0a 1f 19 191f0a00 sexb r8,0x100
2c: 00 01 00 00
30: 00 0a 3f 19 193f0a00 sexb r9,0xffff_feff
34: ff fe ff ff
38: 00 0a 7f 19 197f0a00 sexb r11,0x4242_4242
3c: 42 42 42 42
40: 00 0a ff 1f 1fff0a00 sexb 0,0x100
44: 00 01 00 00
48: 00 0a 1f 18 181f0a00 sexb r0,0
4c: 00 00 00 00
4c: R_ARC_32 foo
50: 01 8a 45 19 19458a01 sexb.z r10,r11
54: 02 8a 86 19 19868a02 sexb.nz r12,r13
58: 0b 0a df 19 19df0a0b sexb.lt r14,0
5c: 00 00 00 00
60: 09 0a ff 19 19ff0a09 sexb.gt r15,0x200
64: 00 02 00 00
68: 00 8b 00 18 18008b00 sexb.f r0,r1
6c: 01 8a 5e 18 185e8a01 sexb.f r2,1
70: 00 0b e2 1f 1fe20b00 sexb.f 0,r4
74: 00 0b bf 18 18bf0b00 sexb.f r5,0x200
78: 00 02 00 00
7c: 00 0b df 1f 1fdf0b00 sexb.f 0,0x200
80: 00 02 00 00
84: 01 8b 00 18 18008b01 sexb.z.f r0,r1
88: 02 0b 3f 18 183f0b02 sexb.nz.f r1,0
8c: 00 00 00 00
90: 0b 0b c1 1f 1fc10b0b sexb.lt.f 0,r2
94: 00 00 00 00 00000000
98: 0c 0b 1f 18 181f0b0c sexb.le.f r0,0x200
9c: 00 02 00 00
a0: 04 0b df 1f 1fdf0b04 sexb.n.f 0,0x200
a4: 00 02 00 00

38
gas/testsuite/gas/arc/sexb.s Normal file
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# sexb test
sexb r0,r1
sexb fp,sp
sexb r0,0
sexb r1,-1
sexb 0,r2
sexb -1,r3
sexb r4,255
sexb 255,r5
sexb r6,-256
sexb -256,r7
sexb r8,256
sexb r9,-257
sexb r11,0x42424242
sexb 255,256
sexb r0,foo
sexb.eq r10,r11
sexb.ne r12,r13
sexb.lt r14,0
sexb.gt r15,512
sexb.f r0,r1
sexb.f r2,1
sexb.f 0,r4
sexb.f r5,512
sexb.f 512,512
sexb.eq.f r0,r1
sexb.ne.f r1,0
sexb.lt.f 0,r2
sexb.le.f r0,512
sexb.n.f 512,512

51
gas/testsuite/gas/arc/sexw.d Normal file
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#as: -EL
#objdump: -dr -EL
.*: +file format elf32-.*arc
Disassembly of section .text:
00000000 <.text>:
0: 00 8c 00 18 18008c00 sexw r0,r1
4: 00 0c 6e 1b 1b6e0c00 sexw fp,sp
8: 00 8c 1f 18 181f8c00 sexw r0,0
c: ff 8d 3f 18 183f8dff sexw r1,-1
10: 00 0c e1 1f 1fe10c00 sexw 0,r2
14: 00 8c e1 1f 1fe18c00 sexw 0,r3
18: ff 8c 9f 18 189f8cff sexw r4,255
1c: 00 8c e2 1f 1fe28c00 sexw 0,r5
20: 00 8d df 18 18df8d00 sexw r6,-256
24: 00 8c e3 1f 1fe38c00 sexw 0,r7
28: 00 0c 1f 19 191f0c00 sexw r8,0x100
2c: 00 01 00 00
30: 00 0c 3f 19 193f0c00 sexw r9,0xffff_feff
34: ff fe ff ff
38: 00 0c 7f 19 197f0c00 sexw r11,0x4242_4242
3c: 42 42 42 42
40: 00 0c ff 1f 1fff0c00 sexw 0,0x100
44: 00 01 00 00
48: 00 0c 1f 18 181f0c00 sexw r0,0
4c: 00 00 00 00
4c: R_ARC_32 foo
50: 01 8c 45 19 19458c01 sexw.z r10,r11
54: 02 8c 86 19 19868c02 sexw.nz r12,r13
58: 0b 0c df 19 19df0c0b sexw.lt r14,0
5c: 00 00 00 00
60: 09 0c ff 19 19ff0c09 sexw.gt r15,0x200
64: 00 02 00 00
68: 00 8d 00 18 18008d00 sexw.f r0,r1
6c: 01 8c 5e 18 185e8c01 sexw.f r2,1
70: 00 0d e2 1f 1fe20d00 sexw.f 0,r4
74: 00 0d bf 18 18bf0d00 sexw.f r5,0x200
78: 00 02 00 00
7c: 00 0d df 1f 1fdf0d00 sexw.f 0,0x200
80: 00 02 00 00
84: 01 8d 00 18 18008d01 sexw.z.f r0,r1
88: 02 0d 3f 18 183f0d02 sexw.nz.f r1,0
8c: 00 00 00 00
90: 0b 0d c1 1f 1fc10d0b sexw.lt.f 0,r2
94: 00 00 00 00 00000000
98: 0c 0d 1f 18 181f0d0c sexw.le.f r0,0x200
9c: 00 02 00 00
a0: 04 0d df 1f 1fdf0d04 sexw.n.f 0,0x200
a4: 00 02 00 00

38
gas/testsuite/gas/arc/sexw.s Normal file
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# sexw test
sexw r0,r1
sexw fp,sp
sexw r0,0
sexw r1,-1
sexw 0,r2
sexw -1,r3
sexw r4,255
sexw 255,r5
sexw r6,-256
sexw -256,r7
sexw r8,256
sexw r9,-257
sexw r11,0x42424242
sexw 255,256
sexw r0,foo
sexw.eq r10,r11
sexw.ne r12,r13
sexw.lt r14,0
sexw.gt r15,512
sexw.f r0,r1
sexw.f r2,1
sexw.f 0,r4
sexw.f r5,512
sexw.f 512,512
sexw.eq.f r0,r1
sexw.ne.f r1,0
sexw.lt.f 0,r2
sexw.le.f r0,512
sexw.n.f 512,512

11
gas/testsuite/gas/arc/sleep.d Normal file
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#as: -EL -marc7
#objdump: -dr -EL
.*: +file format elf32-.*arc
Disassembly of section .text:
00000000 <main>:
0: 00 84 00 40 40008400 add r0,r1,r2
4: 01 fe ff 1f 1ffffe01 sleep
8: 00 0a 62 50 50620a00 sub r3,r4,r5

6
gas/testsuite/gas/arc/sleep.s Normal file
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# sleep test
main:
add r0,r1,r2
sleep
sub r3,r4,r5

44
gas/testsuite/gas/arc/st.d
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#objdump: -dr
#name: st/sr
# Test the st/sr insn.
#as: -EL
#objdump: -dr -EL
.*: +file format elf32-.*arc
Disassembly of section .text:
00000000 10008000 st r0,\[r1\]
00000004 10030a01 st r5,\[r6,1\]
00000008 10040fff st r7,\[r8,-1\]
0000000c 100512ff st r9,\[r10,255\]
00000010 10061700 st r11,\[r12,-256\]
00000014 101f2600 st r19,\[0\]
RELOC: 00000018 R_ARC_32 foo
0000001c 101f2800 st r20,\[4\]
RELOC: 00000020 R_ARC_32 foo
00000024 105f0000 stb r0,\[0\]
0000002c 109f0000 stw r0,\[0\]
00000034 111f0000 st.a r0,\[0\]
0000003c 141f0000 st.di r0,\[0\]
00000044 15400000 stb.a.di r0,\[r0\]
00000048 12008000 sr r0,\[r1\]
0000004c 121f8400 sr r2,\[status\]
00000050 121f0600 sr r3,\[305419896\]
00000000 <.text>:
0: 00 02 01 10 10010200 st r1,\[r2\]
4: 0e 02 01 10 1001020e st r1,\[r2,14\]
8: 00 02 41 10 10410200 stb r1,\[r2\]
c: 0e 82 01 11 1101820e st.a r1,\[r3,14\]
10: 02 02 81 11 11810202 stw.a r1,\[r2,2\]
14: 00 02 1f 10 101f0200 st r1,\[0x384\]
18: 84 03 00 00
1c: 00 7e 41 10 10417e00 stb 0,\[r2\]
20: f8 7f 01 10 10017ff8 st -8,\[r2,-8\]
24: 50 7e 1f 10 101f7e50 st 80,\[0x2ee\]
28: 9e 02 00 00
2c: 00 04 1f 10 101f0400 st r2,\[0\]
30: 00 00 00 00
30: R_ARC_32 foo
34: 02 02 01 14 14010202 st.di r1,\[r2,2\]
38: 03 02 01 15 15010203 st.a.di r1,\[r2,3\]
3c: 04 02 81 15 15810204 stw.a.di r1,\[r2,4\]
40: 00 02 01 12 12010200 sr r1,\[r2\]
44: 0e 82 1f 12 121f820e sr r1,\[0xe\]

35
gas/testsuite/gas/arc/st.s
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@ -1,19 +1,18 @@
# st/sr test
# st test
st r1,[r2]
st r1,[r2,14]
stb r1,[r2]
st.a r1,[r3,14]
stw.a r1,[r2,2]
st r1,[900]
stb 0,[r2]
st -8,[r2,-8]
st 80,[750]
st r2,[foo]
st.di r1,[r2,2]
st.a.di r1,[r2,3]
stw.a.di r1,[r2,4]
st r0,[r1]
st r5,[r6,1]
st r7,[r8,-1]
st r9,[r10,255]
st r11,[r12,-256]
st r19,[foo]
st r20,[foo+4]
stb r0,[0]
stw r0,[0]
st.a r0,[0]
st.di r0,[0]
stb.a.di r0,[r0]
sr r0,[r1]
sr r2,[status]
sr r3,[0x12345678]
sr r1,[r2]
sr r1,[14]

85
gas/testsuite/gas/arc/sub.d Normal file
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#as: -EL
#objdump: -dr -EL
.*: +file format elf32-.*arc
Disassembly of section .text:
00000000 <.text>:
0: 00 84 00 50 50008400 sub r0,r1,r2
4: 00 b8 4d 53 534db800 sub gp,fp,sp
8: 00 3e af 53 53af3e00 sub ilink1,ilink2,blink
c: 00 f8 1d 57 571df800 sub r56,r59,lp_count
10: 00 fe 00 50 5000fe00 sub r0,r1,0
14: 00 84 1f 50 501f8400 sub r0,0,r2
18: 00 84 e0 57 57e08400 sub 0,r1,r2
1c: ff ff 00 50 5000ffff sub r0,r1,-1
20: ff 85 1f 50 501f85ff sub r0,-1,r2
24: 00 84 e0 57 57e08400 sub 0,r1,r2
28: ff fe 00 50 5000feff sub r0,r1,255
2c: ff 84 1f 50 501f84ff sub r0,255,r2
30: 00 84 e0 57 57e08400 sub 0,r1,r2
34: 00 ff 00 50 5000ff00 sub r0,r1,-256
38: 00 85 1f 50 501f8500 sub r0,-256,r2
3c: 00 84 e0 57 57e08400 sub 0,r1,r2
40: 00 fc 00 50 5000fc00 sub r0,r1,0x100
44: 00 01 00 00
48: 00 04 1f 50 501f0400 sub r0,0xffff_feff,r2
4c: ff fe ff ff
50: ff fc 1f 50 501ffcff sub r0,255,0x100
54: 00 01 00 00
58: ff 7e 1f 50 501f7eff sub r0,0x100,255
5c: 00 01 00 00
60: 00 fc 00 50 5000fc00 sub r0,r1,0
64: 00 00 00 00
64: R_ARC_32 foo
68: 00 84 00 50 50008400 sub r0,r1,r2
6c: 00 0a 62 50 50620a00 sub r3,r4,r5
70: 01 90 c3 50 50c39001 sub.z r6,r7,r8
74: 01 16 25 51 51251601 sub.z r9,r10,r11
78: 02 9c 86 51 51869c02 sub.nz r12,r13,r14
7c: 02 22 e8 51 51e82202 sub.nz r15,r16,r17
80: 03 a8 49 52 5249a803 sub.p r18,r19,r20
84: 03 2e ab 52 52ab2e03 sub.p r21,r22,r23
88: 04 b4 0c 53 530cb404 sub.n r24,r25,gp
8c: 04 3a 6e 53 536e3a04 sub.n fp,sp,ilink1
90: 05 c0 cf 53 53cfc005 sub.c ilink2,blink,r32
94: 05 46 31 54 54314605 sub.c r33,r34,r35
98: 05 cc 92 54 5492cc05 sub.c r36,r37,r38
9c: 06 52 f4 54 54f45206 sub.nc r39,r40,r41
a0: 06 d8 55 55 5555d806 sub.nc r42,r43,r44
a4: 06 5e b7 55 55b75e06 sub.nc r45,r46,r47
a8: 07 e4 18 56 5618e407 sub.v r48,r49,r50
ac: 07 6a 1a 57 571a6a07 sub.v r56,r52,r53
b0: 08 f0 1b 57 571bf008 sub.nv r56,r55,r56
b4: 08 76 1d 57 571d7608 sub.nv r56,r58,r59
b8: 09 00 9e 57 579e0009 sub.gt lp_count,lp_count,r0
bc: 0a 7c 00 50 50007c0a sub.ge r0,r0,0
c0: 00 00 00 00
c4: 0b 02 3f 50 503f020b sub.lt r1,1,r1
c8: 01 00 00 00
cc: 0d 06 7f 50 507f060d sub.hi r3,3,r3
d0: 03 00 00 00
d4: 0e 08 df 57 57df080e sub.ls 0,4,r4
d8: 04 00 00 00
dc: 0f fc c2 57 57c2fc0f sub.pnz 0,r5,5
e0: 05 00 00 00
e4: 00 85 00 50 50008500 sub.f r0,r1,r2
e8: 01 fa 00 50 5000fa01 sub.f r0,r1,1
ec: 01 84 1e 50 501e8401 sub.f r0,1,r2
f0: 00 85 e0 57 57e08500 sub.f 0,r1,r2
f4: 00 fd 00 50 5000fd00 sub.f r0,r1,0x200
f8: 00 02 00 00
fc: 00 05 1f 50 501f0500 sub.f r0,0x200,r2
100: 00 02 00 00
104: 01 85 00 50 50008501 sub.z.f r0,r1,r2
108: 02 fd 00 50 5000fd02 sub.nz.f r0,r1,0
10c: 00 00 00 00
110: 0b 05 1f 50 501f050b sub.lt.f r0,0,r2
114: 00 00 00 00
118: 09 85 c0 57 57c08509 sub.gt.f 0,r1,r2
11c: 00 00 00 00 00000000
120: 0c fd 00 50 5000fd0c sub.le.f r0,r1,0x200
124: 00 02 00 00
128: 0a 05 1f 50 501f050a sub.ge.f r0,0x200,r2
12c: 00 02 00 00

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gas/testsuite/gas/arc/sub.s Normal file
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# sub test
sub r0,r1,r2
sub r26,fp,sp
sub ilink1,ilink2,blink
sub r56,r59,lp_count
sub r0,r1,0
sub r0,0,r2
sub 0,r1,r2
sub r0,r1,-1
sub r0,-1,r2
sub -1,r1,r2
sub r0,r1,255
sub r0,255,r2
sub 255,r1,r2
sub r0,r1,-256
sub r0,-256,r2
sub -256,r1,r2
sub r0,r1,256
sub r0,-257,r2
sub r0,255,256
sub r0,256,255
sub r0,r1,foo
sub.al r0,r1,r2
sub.ra r3,r4,r5
sub.eq r6,r7,r8
sub.z r9,r10,r11
sub.ne r12,r13,r14
sub.nz r15,r16,r17
sub.pl r18,r19,r20
sub.p r21,r22,r23
sub.mi r24,r25,r26
sub.n r27,r28,r29
sub.cs r30,r31,r32
sub.c r33,r34,r35
sub.lo r36,r37,r38
sub.cc r39,r40,r41
sub.nc r42,r43,r44
sub.hs r45,r46,r47
sub.vs r48,r49,r50
sub.v r56,r52,r53
sub.vc r56,r55,r56
sub.nv r56,r58,r59
sub.gt r60,r60,r0
sub.ge r0,r0,0
sub.lt r1,1,r1
sub.hi r3,3,r3
sub.ls 4,4,r4
sub.pnz 5,r5,5
sub.f r0,r1,r2
sub.f r0,r1,1
sub.f r0,1,r2
sub.f 0,r1,r2
sub.f r0,r1,512
sub.f r0,512,r2
sub.eq.f r0,r1,r2
sub.ne.f r0,r1,0
sub.lt.f r0,0,r2
sub.gt.f 0,r1,r2
sub.le.f r0,r1,512
sub.ge.f r0,512,r2

11
gas/testsuite/gas/arc/swi.d Normal file
View File

@ -0,0 +1,11 @@
#as: -EL -marc8
#objdump: -dr -EL
.*: +file format elf32-.*arc
Disassembly of section .text:
00000000 <main>:
0: 00 84 00 40 40008400 add r0,r1,r2
4: 02 fe ff 1f 1ffffe02 swi
8: 00 0a 62 50 50620a00 sub r3,r4,r5

6
gas/testsuite/gas/arc/swi.s Normal file
View File

@ -0,0 +1,6 @@
# swi test
main:
add r0,r1,r2
swi
sub r3,r4,r5

5
gas/testsuite/gas/arc/warn.exp
View File

@ -1,13 +1,8 @@
# Test assembler warnings.
if [istarget arc*-*-*] {
load_lib gas-dg.exp
dg-init
dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/warn*.s]] "" ""
dg-finish
}

7
gas/testsuite/gas/arc/warn.s
View File

@ -3,12 +3,9 @@
; { dg-do assemble { target arc-*-* } }
b.d foo
mov r0,256 ; { dg-warning "8 byte instruction in delay slot" "8 byte insn in delay slot" }
mov r0,256 ; { dg-warning "8 byte instruction in delay slot" "8 byte instruction in delay slot" }
j.d foo ; { dg-warning "8 byte jump instruction with delay slot" "8 byte jump with delay slot" }
j.d foo ; { dg-warning "8 byte jump instruction with delay slot" "8 byte jump instruction with delay slot" }
mov r0,r1
sub.f 0,r0,r2
beq foo ; { dg-warning "conditional branch follows set of flags" "cc set/branch nop test" }
foo:

85
gas/testsuite/gas/arc/xor.d Normal file
View File

@ -0,0 +1,85 @@
#as: -EL
#objdump: -dr -EL
.*: +file format elf32-.*arc
Disassembly of section .text:
00000000 <.text>:
0: 00 84 00 78 78008400 xor r0,r1,r2
4: 00 b8 4d 7b 7b4db800 xor gp,fp,sp
8: 00 3e af 7b 7baf3e00 xor ilink1,ilink2,blink
c: 00 f8 1d 7f 7f1df800 xor r56,r59,lp_count
10: 00 fe 00 78 7800fe00 xor r0,r1,0
14: 00 84 1f 78 781f8400 xor r0,0,r2
18: 00 84 e0 7f 7fe08400 xor 0,r1,r2
1c: ff ff 00 78 7800ffff xor r0,r1,-1
20: ff 85 1f 78 781f85ff xor r0,-1,r2
24: 00 84 e0 7f 7fe08400 xor 0,r1,r2
28: ff fe 00 78 7800feff xor r0,r1,255
2c: ff 84 1f 78 781f84ff xor r0,255,r2
30: 00 84 e0 7f 7fe08400 xor 0,r1,r2
34: 00 ff 00 78 7800ff00 xor r0,r1,-256
38: 00 85 1f 78 781f8500 xor r0,-256,r2
3c: 00 84 e0 7f 7fe08400 xor 0,r1,r2
40: 00 fc 00 78 7800fc00 xor r0,r1,0x100
44: 00 01 00 00
48: 00 04 1f 78 781f0400 xor r0,0xffff_feff,r2
4c: ff fe ff ff
50: ff fc 1f 78 781ffcff xor r0,255,0x100
54: 00 01 00 00
58: ff 7e 1f 78 781f7eff xor r0,0x100,255
5c: 00 01 00 00
60: 00 fc 00 78 7800fc00 xor r0,r1,0
64: 00 00 00 00
64: R_ARC_32 foo
68: 00 84 00 78 78008400 xor r0,r1,r2
6c: 00 0a 62 78 78620a00 xor r3,r4,r5
70: 01 90 c3 78 78c39001 xor.z r6,r7,r8
74: 01 16 25 79 79251601 xor.z r9,r10,r11
78: 02 9c 86 79 79869c02 xor.nz r12,r13,r14
7c: 02 22 e8 79 79e82202 xor.nz r15,r16,r17
80: 03 a8 49 7a 7a49a803 xor.p r18,r19,r20
84: 03 2e ab 7a 7aab2e03 xor.p r21,r22,r23
88: 04 b4 0c 7b 7b0cb404 xor.n r24,r25,gp
8c: 04 3a 6e 7b 7b6e3a04 xor.n fp,sp,ilink1
90: 05 c0 cf 7b 7bcfc005 xor.c ilink2,blink,r32
94: 05 46 31 7c 7c314605 xor.c r33,r34,r35
98: 05 cc 92 7c 7c92cc05 xor.c r36,r37,r38
9c: 06 52 f4 7c 7cf45206 xor.nc r39,r40,r41
a0: 06 d8 55 7d 7d55d806 xor.nc r42,r43,r44
a4: 06 5e b7 7d 7db75e06 xor.nc r45,r46,r47
a8: 07 e4 18 7e 7e18e407 xor.v r48,r49,r50
ac: 07 6a 1a 7f 7f1a6a07 xor.v r56,r52,r53
b0: 08 f0 1b 7f 7f1bf008 xor.nv r56,r55,r56
b4: 08 76 1d 7f 7f1d7608 xor.nv r56,r58,r59
b8: 09 00 9e 7f 7f9e0009 xor.gt lp_count,lp_count,r0
bc: 0a 7c 00 78 78007c0a xor.ge r0,r0,0
c0: 00 00 00 00
c4: 0b 02 3f 78 783f020b xor.lt r1,1,r1
c8: 01 00 00 00
cc: 0d 06 7f 78 787f060d xor.hi r3,3,r3
d0: 03 00 00 00
d4: 0e 08 df 7f 7fdf080e xor.ls 0,4,r4
d8: 04 00 00 00
dc: 0f fc c2 7f 7fc2fc0f xor.pnz 0,r5,5
e0: 05 00 00 00
e4: 00 85 00 78 78008500 xor.f r0,r1,r2
e8: 01 fa 00 78 7800fa01 xor.f r0,r1,1
ec: 01 84 1e 78 781e8401 xor.f r0,1,r2
f0: 00 85 e0 7f 7fe08500 xor.f 0,r1,r2
f4: 00 fd 00 78 7800fd00 xor.f r0,r1,0x200
f8: 00 02 00 00
fc: 00 05 1f 78 781f0500 xor.f r0,0x200,r2
100: 00 02 00 00
104: 01 85 00 78 78008501 xor.z.f r0,r1,r2
108: 02 fd 00 78 7800fd02 xor.nz.f r0,r1,0
10c: 00 00 00 00
110: 0b 05 1f 78 781f050b xor.lt.f r0,0,r2
114: 00 00 00 00
118: 09 85 c0 7f 7fc08509 xor.gt.f 0,r1,r2
11c: 00 00 00 00 00000000
120: 0c fd 00 78 7800fd0c xor.le.f r0,r1,0x200
124: 00 02 00 00
128: 0a 05 1f 78 781f050a xor.ge.f r0,0x200,r2
12c: 00 02 00 00

68
gas/testsuite/gas/arc/xor.s Normal file
View File

@ -0,0 +1,68 @@
# xor test
xor r0,r1,r2
xor r26,fp,sp
xor ilink1,ilink2,blink
xor r56,r59,lp_count
xor r0,r1,0
xor r0,0,r2
xor 0,r1,r2
xor r0,r1,-1
xor r0,-1,r2
xor -1,r1,r2
xor r0,r1,255
xor r0,255,r2
xor 255,r1,r2
xor r0,r1,-256
xor r0,-256,r2
xor -256,r1,r2
xor r0,r1,256
xor r0,-257,r2
xor r0,255,256
xor r0,256,255
xor r0,r1,foo
xor.al r0,r1,r2
xor.ra r3,r4,r5
xor.eq r6,r7,r8
xor.z r9,r10,r11
xor.ne r12,r13,r14
xor.nz r15,r16,r17
xor.pl r18,r19,r20
xor.p r21,r22,r23
xor.mi r24,r25,r26
xor.n r27,r28,r29
xor.cs r30,r31,r32
xor.c r33,r34,r35
xor.lo r36,r37,r38
xor.cc r39,r40,r41
xor.nc r42,r43,r44
xor.hs r45,r46,r47
xor.vs r48,r49,r50
xor.v r56,r52,r53
xor.vc r56,r55,r56
xor.nv r56,r58,r59
xor.gt r60,r60,r0
xor.ge r0,r0,0
xor.lt r1,1,r1
xor.hi r3,3,r3
xor.ls 4,4,r4
xor.pnz 5,r5,5
xor.f r0,r1,r2
xor.f r0,r1,1
xor.f r0,1,r2
xor.f 0,r1,r2
xor.f r0,r1,512
xor.f r0,512,r2
xor.eq.f r0,r1,r2
xor.ne.f r0,r1,0
xor.lt.f r0,0,r2
xor.gt.f 0,r1,r2
xor.le.f r0,r1,512
xor.ge.f r0,512,r2

2
gas/testsuite/gas/ieee-fp/x930509a.exp
View File

@ -23,6 +23,6 @@ proc dotest {} {
# float encoding is tested in c54x-specific tests.
# No floating point support in assembly code for CRIS.
if { ![istarget vax*-*-*] && ![istarget *c54x*-*-*]
&& ![istarget cris-*-*] } then {
&& ![istarget cris-*-*] && ![istarget arc*-*-*] } then {
dotest
}

5
gas/testsuite/gas/vtable/vtable.exp
View File

@ -29,6 +29,11 @@ if { ( [istarget "*-*-elf*"] || [istarget "*-*-linux*"])
return
}
# not yet supported by ARC
if {[istarget "arc*-*-*"]} {
return
}
run_dump_test "inherit0"
run_list_test "inherit1" "-al"

4
include/ChangeLog
View File

@ -1,3 +1,7 @@
2001-01-11 Peter Targett <peter.targett@arccores.com>
* dis-asm.h (arc_get_disassembler): Correct declaration.
2001-01-09 Philip Blundell <philb@gnu.org>
* bin-bugs.h (REPORT_BUGS_TO): Set to `bug-binutils@gnu.org'.

2
include/dis-asm.h
View File

@ -174,7 +174,7 @@ extern int print_insn_h8300h PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_h8300s PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_h8500 PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_alpha PARAMS ((bfd_vma, disassemble_info*));
extern disassembler_ftype arc_get_disassembler PARAMS ((int, int));
extern disassembler_ftype arc_get_disassembler PARAMS ((void *));
extern int print_insn_big_arm PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_little_arm PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_sparc PARAMS ((bfd_vma, disassemble_info*));

9
include/elf/ChangeLog
View File

@ -1,8 +1,15 @@
2001-01-11 Peter Targett <peter.targett@arccores.com>
* arc.h (E_ARC_MACH_ARC5, E_ARC_MACH_ARC6, E_ARC_MACH_ARC7,
E_ARC_MACH_ARC8): New definitions for cpu types.
* common.h (EM_ARC): Change comment.
2000-12-12 Nick Clifton <nickc@redhat.com>
* mips.h: Fix formatting.
Mon Dec 11 10:56:58 2000 Jeffrey A Law (law@cygnus.com)
2000-12-11 Jeffrey A Law (law@cygnus.com)
* hppa.h (DT_HP_*): Define relative to OLD_DT_LOOS for hpux
compatibility.

19
include/elf/arc.h
View File

@ -26,6 +26,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#include "elf/reloc-macros.h"
/* Relocations. */
START_RELOC_NUMBERS (elf_arc_reloc_type)
RELOC_NUMBER (R_ARC_NONE, 0)
RELOC_NUMBER (R_ARC_32, 1)
@ -36,18 +37,20 @@ END_RELOC_NUMBERS (R_ARC_max)
/* Processor specific flags for the ELF header e_flags field. */
/* Four bit ARC machine type field. */
#define EF_ARC_MACH 0x0000000f
#define EF_ARC_MACH 0x0000000f
/* Various CPU types. */
#define E_ARC_MACH_BASE 0x00000000
#define E_ARC_MACH_UNUSED1 0x00000001
#define E_ARC_MACH_UNUSED2 0x00000002
#define E_ARC_MACH_UNUSED4 0x00000003
/* Leave bits 0xf0 alone in case we ever have more than 16 cpu types.
Highly unlikely, but what the heck. */
#define E_ARC_MACH_ARC5 0
#define E_ARC_MACH_ARC6 1
#define E_ARC_MACH_ARC7 2
#define E_ARC_MACH_ARC8 3
/* Leave bits 0xf0 alone in case we ever have more than 16 cpu types. */
/* File contains position independent code. */
#define EF_ARC_PIC 0x00000100
#define EF_ARC_PIC 0x00000100
#endif /* _ELF_ARC_H */

2
include/elf/common.h
View File

@ -125,7 +125,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#define EM_SH 42 /* Hitachi SH */
#define EM_SPARCV9 43 /* SPARC v9 64-bit */
#define EM_TRICORE 44 /* Siemens Tricore embedded processor */
#define EM_ARC 45 /* Argonaut RISC Core, Argonaut Technologies Inc. */
#define EM_ARC 45 /* ARC Cores */
#define EM_H8_300 46 /* Hitachi H8/300 */
#define EM_H8_300H 47 /* Hitachi H8/300H */
#define EM_H8S 48 /* Hitachi H8S */

18
include/opcode/ChangeLog
View File

@ -1,4 +1,12 @@
Wed Jan 10 15:30:57 MET 2001 Jan Hubicka <jh@suse.cz>
2001-01-11 Peter Targett <peter.targett@arccores.com>
* arc.h (ARC_MACH_5, ARC_MACH_6, ARC_MACH_7, ARC_MACH_8): New
definitions for masking cpu type.
(arc_ext_operand_value) New structure for storing extended
operands.
(ARC_OPERAND_*) Flags for operand values.
2001-01-10 Jan Hubicka <jh@suse.cz>
* i386.h (pinsrw): Add.
(pshufw): Remove.
@ -17,16 +25,16 @@ Wed Jan 10 15:30:57 MET 2001 Jan Hubicka <jh@suse.cz>
(CGEN_SYNTAX): Changed to make array CGEN_SYNTAX_CHAR_TYPE.
(CGEN_SYNTAX_CHAR): Changed to cast to unsigned char.
Fri Jan 5 13:22:23 MET 2001 Jan Hubicka <jh@suse.cz>
2001-01-05 Jan Hubicka <jh@suse.cz>
* i386.h (i386_optab): Make [sml]fence template to use immext field.
Wed Jan 3 16:27:15 MET 2001 Jan Hubicka <jh@suse.cz>
2001-01-03 Jan Hubicka <jh@suse.cz>
* i386.h (i386_optab): Fix 64bit pushf template; Add instructions
introduced by Pentium4
Sat Dec 30 19:03:15 MET 2000 Jan Hubicka <jh@suse.cz>
2000-12-30 Jan Hubicka <jh@suse.cz>
* i386.h (i386_optab): Add "rex*" instructions;
add swapgs; disable jmp/call far direct instructions for
@ -37,7 +45,7 @@ Sat Dec 30 19:03:15 MET 2000 Jan Hubicka <jh@suse.cz>
(*Suf): Add No_qSuf.
(q_Suf, wlq_Suf, bwlq_Suf): New.
Wed Dec 20 14:22:03 MET 2000 Jan Hubicka <jh@suse.cz>
2000-12-20 Jan Hubicka <jh@suse.cz>
* i386.h (i386_optab): Replace "Imm" with "EncImm".
(i386_regtab): Add flags field.

229
include/opcode/arc.h
View File

@ -1,93 +1,110 @@
/* Opcode table for the ARC.
Copyright 1994, 1995, 1997 Free Software Foundation, Inc.
Copyright 1994, 1995, 1997, 2000 Free Software Foundation, Inc.
Contributed by Doug Evans (dje@cygnus.com).
This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
the GNU Binutils.
This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
the GNU Binutils.
GAS/GDB is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
GAS/GDB is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
GAS/GDB is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
GAS/GDB is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GAS or GDB; see the file COPYING. If not, write to
the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
You should have received a copy of the GNU General Public License
along with GAS or GDB; see the file COPYING. If not, write to
the Free Software Foundation, 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA. */
/* List of the various cpu types.
The tables currently use bit masks to say whether the instruction or
whatever is supported by a particular cpu. This lets us have one entry
apply to several cpus.
This duplicates bfd_mach_arc_xxx. For now I wish to isolate this from bfd
and bfd from this. Also note that these numbers are bit values as we want
to allow for things available on more than one ARC (but not necessarily all
ARCs). */
/* The `base' cpu must be 0 (table entries are omitted for the base cpu).
The cpu type is treated independently of endianness.
The complete `mach' number includes endianness.
The `base' cpu must be 0. The cpu type is treated independently of
endianness. The complete `mach' number includes endianness.
These values are internal to opcodes/bfd/binutils/gas. */
#define ARC_MACH_BASE 0
#define ARC_MACH_UNUSED1 1
#define ARC_MACH_UNUSED2 2
#define ARC_MACH_UNUSED4 4
#define ARC_MACH_5 0
#define ARC_MACH_6 1
#define ARC_MACH_7 2
#define ARC_MACH_8 4
/* Additional cpu values can be inserted here and ARC_MACH_BIG moved down. */
#define ARC_MACH_BIG 8
#define ARC_MACH_BIG 16
/* Mask of number of bits necessary to record cpu type. */
#define ARC_MACH_CPU_MASK 7
#define ARC_MACH_CPU_MASK (ARC_MACH_BIG - 1)
/* Mask of number of bits necessary to record cpu type + endianness. */
#define ARC_MACH_MASK 15
#define ARC_MACH_MASK ((ARC_MACH_BIG << 1) - 1)
/* Type to denote an ARC instruction (at least a 32 bit unsigned int). */
typedef unsigned int arc_insn;
struct arc_opcode {
char *syntax; /* syntax of insn */
unsigned long mask, value; /* recognize insn if (op&mask)==value */
int flags; /* various flag bits */
char *syntax; /* syntax of insn */
unsigned long mask, value; /* recognize insn if (op&mask) == value */
int flags; /* various flag bits */
/* Values for `flags'. */
/* Return CPU number, given flag bits. */
#define ARC_OPCODE_CPU(bits) ((bits) & ARC_MACH_CPU_MASK)
/* Return MACH number, given flag bits. */
#define ARC_OPCODE_MACH(bits) ((bits) & ARC_MACH_MASK)
/* First opcode flag bit available after machine mask. */
#define ARC_OPCODE_FLAG_START ((ARC_MACH_MASK + 1) << 0)
#define ARC_OPCODE_FLAG_START (ARC_MACH_MASK + 1)
/* This insn is a conditional branch. */
#define ARC_OPCODE_COND_BRANCH (ARC_OPCODE_FLAG_START)
#define SYNTAX_3OP (ARC_OPCODE_COND_BRANCH << 1)
#define SYNTAX_LENGTH (SYNTAX_3OP )
#define SYNTAX_2OP (SYNTAX_3OP << 1)
#define OP1_MUST_BE_IMM (SYNTAX_2OP << 1)
#define OP1_IMM_IMPLIED (OP1_MUST_BE_IMM << 1)
#define SYNTAX_VALID (OP1_IMM_IMPLIED << 1)
/* These values are used to optimize assembly and disassembly. Each insn is
on a list of related insns (same first letter for assembly, same insn code
for disassembly). */
struct arc_opcode *next_asm; /* Next instruction to try during assembly. */
struct arc_opcode *next_dis; /* Next instruction to try during disassembly. */
#define I(x) (((x) & 31) << 27)
#define A(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGA)
#define B(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGB)
#define C(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGC)
#define R(x,b,m) (((x) & (m)) << (b)) /* value X, mask M, at bit B */
/* Macros to create the hash values for the lists. */
/* These values are used to optimize assembly and disassembly. Each insn
is on a list of related insns (same first letter for assembly, same
insn code for disassembly). */
struct arc_opcode *next_asm; /* Next instr to try during assembly. */
struct arc_opcode *next_dis; /* Next instr to try during disassembly. */
/* Macros to create the hash values for the lists. */
#define ARC_HASH_OPCODE(string) \
((string)[0] >= 'a' && (string)[0] <= 'z' ? (string)[0] - 'a' : 26)
#define ARC_HASH_ICODE(insn) \
((unsigned int) (insn) >> 27)
/* Macros to access `next_asm', `next_dis' so users needn't care about the
underlying mechanism. */
/* Macros to access `next_asm', `next_dis' so users needn't care about the
underlying mechanism. */
#define ARC_OPCODE_NEXT_ASM(op) ((op)->next_asm)
#define ARC_OPCODE_NEXT_DIS(op) ((op)->next_dis)
};
/* this is an "insert at front" linked list per Metaware spec
that new definitions override older ones. */
struct arc_opcode *arc_ext_opcodes;
struct arc_operand_value {
char *name; /* eg: "eq" */
short value; /* eg: 1 */
unsigned char type; /* index into `arc_operands' */
unsigned char flags; /* various flag bits */
char *name; /* eg: "eq" */
short value; /* eg: 1 */
unsigned char type; /* index into `arc_operands' */
unsigned char flags; /* various flag bits */
/* Values for `flags'. */
@ -97,18 +114,23 @@ struct arc_operand_value {
#define ARC_OPVAL_MACH(bits) ((bits) & ARC_MACH_MASK)
};
struct arc_ext_operand_value {
struct arc_ext_operand_value *next;
struct arc_operand_value operand;
} *arc_ext_operands;
struct arc_operand {
/* One of the insn format chars. */
/* One of the insn format chars. */
unsigned char fmt;
/* The number of bits in the operand (may be unused for a modifier). */
/* The number of bits in the operand (may be unused for a modifier). */
unsigned char bits;
/* How far the operand is left shifted in the instruction, or
the modifier's flag bit (may be unused for a modifier. */
/* How far the operand is left shifted in the instruction, or
the modifier's flag bit (may be unused for a modifier. */
unsigned char shift;
/* Various flag bits. */
/* Various flag bits. */
int flags;
/* Values for `flags'. */
@ -150,6 +172,19 @@ struct arc_operand {
in special ways. */
#define ARC_OPERAND_FAKE 0x100
/* separate flags operand for j and jl instructions */
#define ARC_OPERAND_JUMPFLAGS 0x200
/* allow warnings and errors to be issued after call to insert_xxxxxx */
#define ARC_OPERAND_WARN 0x400
#define ARC_OPERAND_ERROR 0x800
/* this is a load operand */
#define ARC_OPERAND_LOAD 0x8000
/* this is a store operand */
#define ARC_OPERAND_STORE 0x10000
/* Modifier values. */
/* A dot is required before a suffix. Eg: .le */
#define ARC_MOD_DOT 0x1000
@ -166,52 +201,57 @@ struct arc_operand {
/* Non-zero if the operand type is really a modifier. */
#define ARC_MOD_P(X) ((X) & ARC_MOD_BITS)
/* Insertion function. This is used by the assembler. To insert an
operand value into an instruction, check this field.
/* enforce read/write only register restrictions */
#define ARC_REGISTER_READONLY 0x01
#define ARC_REGISTER_WRITEONLY 0x02
#define ARC_REGISTER_NOSHORT_CUT 0x04
If it is NULL, execute
i |= (p & ((1 << o->bits) - 1)) << o->shift;
(I is the instruction which we are filling in, O is a pointer to
this structure, and OP is the opcode value; this assumes twos
complement arithmetic).
/* Insertion function. This is used by the assembler. To insert an
operand value into an instruction, check this field.
If this field is not NULL, then simply call it with the
instruction and the operand value. It will return the new value
of the instruction. If the ERRMSG argument is not NULL, then if
the operand value is illegal, *ERRMSG will be set to a warning
string (the operand will be inserted in any case). If the
operand value is legal, *ERRMSG will be unchanged.
If it is NULL, execute
i |= (p & ((1 << o->bits) - 1)) << o->shift;
(I is the instruction which we are filling in, O is a pointer to
this structure, and OP is the opcode value; this assumes twos
complement arithmetic).
If this field is not NULL, then simply call it with the
instruction and the operand value. It will return the new value
of the instruction. If the ERRMSG argument is not NULL, then if
the operand value is illegal, *ERRMSG will be set to a warning
string (the operand will be inserted in any case). If the
operand value is legal, *ERRMSG will be unchanged.
REG is non-NULL when inserting a register value. */
REG is non-NULL when inserting a register value. */
arc_insn (*insert) PARAMS ((arc_insn insn,
const struct arc_operand *operand, int mods,
const struct arc_operand_value *reg, long value,
const char **errmsg));
/* Extraction function. This is used by the disassembler. To
extract this operand type from an instruction, check this field.
/* Extraction function. This is used by the disassembler. To
extract this operand type from an instruction, check this field.
If it is NULL, compute
op = ((i) >> o->shift) & ((1 << o->bits) - 1);
if ((o->flags & ARC_OPERAND_SIGNED) != 0
&& (op & (1 << (o->bits - 1))) != 0)
op -= 1 << o->bits;
(I is the instruction, O is a pointer to this structure, and OP
is the result; this assumes twos complement arithmetic).
If this field is not NULL, then simply call it with the
instruction value. It will return the value of the operand. If
the INVALID argument is not NULL, *INVALID will be set to
non-zero if this operand type can not actually be extracted from
this operand (i.e., the instruction does not match). If the
operand is valid, *INVALID will not be changed.
If it is NULL, compute
op = ((i) >> o->shift) & ((1 << o->bits) - 1);
if ((o->flags & ARC_OPERAND_SIGNED) != 0
&& (op & (1 << (o->bits - 1))) != 0)
op -= 1 << o->bits;
(I is the instruction, O is a pointer to this structure, and OP
is the result; this assumes twos complement arithmetic).
INSN is a pointer to an array of two `arc_insn's. The first element is
the insn, the second is the limm if present.
If this field is not NULL, then simply call it with the
instruction value. It will return the value of the operand. If
the INVALID argument is not NULL, *INVALID will be set to
non-zero if this operand type can not actually be extracted from
this operand (i.e., the instruction does not match). If the
operand is valid, *INVALID will not be changed.
INSN is a pointer to an array of two `arc_insn's. The first element is
the insn, the second is the limm if present.
Operands that have a printable form like registers and suffixes have
their struct arc_operand_value pointer stored in OPVAL. */
Operands that have a printable form like registers and suffixes have
their struct arc_operand_value pointer stored in OPVAL. */
long (*extract) PARAMS ((arc_insn *insn,
const struct arc_operand *operand,
@ -219,9 +259,8 @@ struct arc_operand {
int *invalid));
};
/* Bits that say what version of cpu we have.
These should be passed to arc_init_opcode_tables.
At present, all there is is the cpu type. */
/* Bits that say what version of cpu we have. These should be passed to
arc_init_opcode_tables. At present, all there is is the cpu type. */
/* CPU number, given value passed to `arc_init_opcode_tables'. */
#define ARC_HAVE_CPU(bits) ((bits) & ARC_MACH_CPU_MASK)
@ -243,16 +282,16 @@ struct arc_operand {
#define ARC_MASK_REG 63
/* Delay slot types. */
#define ARC_DELAY_NONE 0 /* no delay slot */
#define ARC_DELAY_NORMAL 1 /* delay slot in both cases */
#define ARC_DELAY_JUMP 2 /* delay slot only if branch taken */
#define ARC_DELAY_NONE 0 /* no delay slot */
#define ARC_DELAY_NORMAL 1 /* delay slot in both cases */
#define ARC_DELAY_JUMP 2 /* delay slot only if branch taken */
/* Non-zero if X will fit in a signed 9 bit field. */
#define ARC_SHIMM_CONST_P(x) ((long) (x) >= -256 && (long) (x) <= 255)
extern const struct arc_operand arc_operands[];
extern const int arc_operand_count;
extern /*const*/ struct arc_opcode arc_opcodes[];
extern struct arc_opcode arc_opcodes[];
extern const int arc_opcodes_count;
extern const struct arc_operand_value arc_suffixes[];
extern const int arc_suffixes_count;
@ -262,6 +301,7 @@ extern unsigned char arc_operand_map[];
/* Utility fns in arc-opc.c. */
int arc_get_opcode_mach PARAMS ((int, int));
/* `arc_opcode_init_tables' must be called before `arc_xxx_supported'. */
void arc_opcode_init_tables PARAMS ((int));
void arc_opcode_init_insert PARAMS ((void));
@ -269,6 +309,7 @@ void arc_opcode_init_extract PARAMS ((void));
const struct arc_opcode *arc_opcode_lookup_asm PARAMS ((const char *));
const struct arc_opcode *arc_opcode_lookup_dis PARAMS ((unsigned int));
int arc_opcode_limm_p PARAMS ((long *));
const struct arc_operand_value *arc_opcode_lookup_suffix PARAMS ((const struct arc_operand *type, int value));
const struct arc_operand_value *arc_opcode_lookup_suffix
PARAMS ((const struct arc_operand *type, int value));
int arc_opcode_supported PARAMS ((const struct arc_opcode *));
int arc_opval_supported PARAMS ((const struct arc_operand_value *));

117
opcodes/ChangeLog
View File

@ -1,4 +1,19 @@
Wed Jan 10 15:13:21 MET 2001 Jan Hubicka <jh@suse.cz>
2001-01-11 Peter Targett <peter.targett@arccores.com>
* configure.in: Add arc-ext.lo for bfd_arc_arch selection.
* Makefile.am (C_FILES): Add arc-ext.c.
(ALL_MACHINES) Add arc-ext.lo.
(INCLUDES) Add opcode directory to list.
New dependency entry for arc-ext.lo.
* disassemble.c (disassembler): Correct call to
arc_get_disassembler.
* arc-opc.c: New update for ARC, including full base
instructions for ARC variants.
* arc-dis.h, arc-dis.c: New update for ARC, including
extensibility functionality.
* arc-ext.h, arc-ext.c: New files for handling extensibility.
2001-01-10 Jan Hubicka <jh@suse.cz>
* i386-dis.c (PREGRP15 - PREGRP24): New.
(dis386_twobyt): Add SSE2 instructions.
@ -29,7 +44,7 @@ Wed Jan 10 15:13:21 MET 2001 Jan Hubicka <jh@suse.cz>
* cgen-dis.in (print_insn_normal): Ditto.
* cgen-ibld.in (insert_insn_normal, extract_insn_normal): Ditto.
Fri Jan 5 11:31:07 MET 2001 Jan Hubicka <jh@suse.cz>
2001-01-05 Jan Hubicka <jh@suse.cz>
* i386-dis.c: Add x86_64 support.
(rex): New static variable.
@ -249,7 +264,7 @@ Fri Jan 5 11:31:07 MET 2001 Jan Hubicka <jh@suse.cz>
* m32r-desc.h: Regenerate.
* m32r-ibld.c: Regenerate.
2000-10-05 Jim Wilson <wilson@cygnus.com>
2000-10-05 Jim Wilson <wilson@redhat.com>
* ia64-ic.tbl: Update from Intel.
* ia64-asmtab.c: Regenerate.
@ -273,7 +288,7 @@ Fri Jan 5 11:31:07 MET 2001 Jan Hubicka <jh@suse.cz>
New.
* disassemble.c (disassembler) [ARCH_cris]: Call cris_get_disassembler.
2000-09-22 Jim Wilson <wilson@cygnus.com>
2000-09-22 Jim Wilson <wilson@redhat.com>
* ia64-opc-f.c (ia64_opcodes_f): Add fpcmp pseudo-ops for
gt, ge, ngt, and nge.
@ -342,7 +357,7 @@ Fri Jan 5 11:31:07 MET 2001 Jan Hubicka <jh@suse.cz>
instructions. Added extended mnemonic mftbl as defined in the
405GP manual for all PPCs.
2000-08-28 Jim Wilson <wilson@cygnus.com>
2000-08-28 Jim Wilson <wilson@redhat.com>
* ia64-dis.c (print_insn_ia64): Add failed label after ia64_free_opcode
call. Change last goto to use failed instead of done.
@ -388,7 +403,7 @@ Fri Jan 5 11:31:07 MET 2001 Jan Hubicka <jh@suse.cz>
* z8k-dis.c: Fix formatting.
2000-08-16 Jim Wilson <wilson@cygnus.com>
2000-08-16 Jim Wilson <wilson@redhat.com>
* ia64-ic.tbl (pr-readers-nobr-nomovpr): Add addl, adds. Delete
break, mov-immediate, nop.
@ -398,16 +413,16 @@ Fri Jan 5 11:31:07 MET 2001 Jan Hubicka <jh@suse.cz>
* ia64-opc.h (POSTINC): Define.
* ia64-asmtab.c: Regenerate.
2000-08-15 Jim Wilson <wilson@cygnus.com>
2000-08-15 Jim Wilson <wilson@redhat.com>
* ia64-ic.tbl: Add missing entries.
2000-08-08 Jason Eckhardt <jle@cygnus.com>
2000-08-08 Jason Eckhardt <jle@redhat.com>
* i860-dis.c (print_br_address): Change third argument from int
to long.
2000-08-07 Richard Henderson <rth@cygnus.com>
2000-08-07 Richard Henderson <rth@redhat.com>
* ia64-dis.c (print_insn_ia64): Get byte skip count correct
for MLI templates. Handle IA64_OPND_TGT64.
@ -417,7 +432,7 @@ Fri Jan 5 11:31:07 MET 2001 Jan Hubicka <jh@suse.cz>
* cgen-dis.in, cgen-asm.in, cgen-ibld.in: New files.
* cgen.sh: Likewise.
2000-08-02 Jim Wilson <wilson@cygnus.com>
2000-08-02 Jim Wilson <wilson@redhat.com>
* ia64-dis.c (print_insn_ia64): Call ia64_free_opcode at end.
@ -454,7 +469,7 @@ Fri Jan 5 11:31:07 MET 2001 Jan Hubicka <jh@suse.cz>
ATTRIBUTE_UNUSED.
(cgen_parse_keyword): Ditto.
2000-07-22 Jason Eckhardt <jle@cygnus.com>
2000-07-22 Jason Eckhardt <jle@redhat.com>
* i860-dis.c: New file.
(print_insn_i860): New function.
@ -494,7 +509,7 @@ Fri Jan 5 11:31:07 MET 2001 Jan Hubicka <jh@suse.cz>
* sparc-opc.c (sparc_opcodes): popc has 0 in rs1, not rs2.
Reported by Bill Clarke <llib@computer.org>.
2000-07-09 Geoffrey Keating <geoffk@cygnus.com>
2000-07-09 Geoffrey Keating <geoffk@redhat.com>
* ppc-opc.c (powerpc_opcodes): Correct suffix for vslw.
Patch by Randall J Fisher <rfisher@ecn.purdue.edu>.
@ -574,11 +589,11 @@ Fri Jan 5 11:31:07 MET 2001 Jan Hubicka <jh@suse.cz>
(bfd_h8_disassemble): Distinguish adds/subs, inc/dec.[wl]
correctly.
Fri Jun 9 21:49:02 2000 Denis Chertykov <denisc@overta.ru>
2000-06-09 Denis Chertykov <denisc@overta.ru>
* avr-dis.c (avr_operand): Bugfix for jmp/call address.
Wed Jun 7 21:36:45 2000 Denis Chertykov <denisc@overta.ru>
2000-06-07 Denis Chertykov <denisc@overta.ru>
* avr-dis.c: completely rewritten.
@ -593,12 +608,12 @@ Wed Jun 7 21:36:45 2000 Denis Chertykov <denisc@overta.ru>
(bfd_h8_disassemble): Distinguish the operand size of inc/dev.[wl]
correctly. Fix a typo.
2000-05-31 Nick Clifton <nickc@cygnus.com>
2000-05-31 Nick Clifton <nickc@redhat.com>
* opintl.h (_(String)): Explain why dgettext is used instead of
gettext.
2000-05-30 Nick Clifton <nickc@cygnus.com>
2000-05-30 Nick Clifton <nickc@redhat.com>
* opintl.h (gettext, dgettext, dcgettext, textdomain,
bindtextdomain): Replace defines with those from intl/libgettext.h
@ -609,21 +624,21 @@ Wed Jun 7 21:36:45 2000 Denis Chertykov <denisc@overta.ru>
* Makefile.am: Update dependencies with "make dep-am"
* Makefile.in: Regenerate.
Thu May 25 22:53:20 2000 Alexandre Oliva <aoliva@cygnus.com>
2000-05-25 Alexandre Oliva <aoliva@redhat.com>
* m10300-dis.c (disassemble): Don't assume 32-bit longs when
sign-extending operands.
Mon May 15 15:18:07 2000 Donald Lindsay <dlindsay@cygnus.com>
2000-05-15 Donald Lindsay <dlindsay@redhat.com>
* d10v-opc.c (d10v_opcodes): add ALONE tag to all short branches
except brf's.
2000-05-21 Nick Clifton <nickc@cygnus.com>
2000-05-21 Nick Clifton <nickc@redhat.com>
* Makefile.am (LIBIBERTY): Define.
Fri May 19 12:29:27 EDT 2000 Diego Novillo <dnovillo@redhat.com>
2000-05-19 Diego Novillo <dnovillo@redhat.com>
* mips-dis.c (REGISTER_NAMES): Rename to STD_REGISTER_NAMES.
(STD_REGISTER_NAMES): New name for REGISTER_NAMES.
@ -639,7 +654,7 @@ Fri May 19 12:29:27 EDT 2000 Diego Novillo <dnovillo@redhat.com>
CGEN_MAX_* -> CGEN_ACTUAL_MAX_* macros.
* m32r-desc.h: Ditto.
2000-05-15 Nick Clifton <nickc@cygnus.com>
2000-05-15 Nick Clifton <nickc@redhat.com>
* arm-opc.h: Use upper case for flasg in MSR and MRS
instructions. Allow any bit to be set in the field_mask of
@ -658,7 +673,7 @@ Fri May 19 12:29:27 EDT 2000 Diego Novillo <dnovillo@redhat.com>
* mips-dis.c (print_insn_arg): Don't mask top 32 bits of 64-bit
target addresses for 'jal' and 'j'.
2000-05-10 Geoff Keating <geoffk@cygnus.com>
2000-05-10 Geoff Keating <geoffk@redhat.com>
* ppc-opc.c (powerpc_opcodes): Make the predicted-branch opcodes
also available in common mode when powerpc syntax is being used.
@ -668,7 +683,7 @@ Fri May 19 12:29:27 EDT 2000 Diego Novillo <dnovillo@redhat.com>
* m68k-dis.c (dummy_printer): Add ATTRIBUTE_UNUSED to args.
(dummy_print_address): Ditto.
2000-05-04 Timothy Wall <twall@cygnus.com>
2000-05-04 Timothy Wall <twall@redhat.com>
* tic54x-opc.c: New.
* tic54x-dis.c: New.
@ -692,18 +707,18 @@ Fri May 19 12:29:27 EDT 2000 Diego Novillo <dnovillo@redhat.com>
(print_insn_little_powerpc): Likewise.
(print_insn_powerpc): Prepend 'v' when printing vector registers.
Mon Apr 24 15:21:35 2000 Clinton Popetz <cpopetz@cygnus.com>
2000-04-24 Clinton Popetz <cpopetz@redhat.com>
* configure.in: Add bfd_powerpc_64_arch.
* disassemble.c (disassembler): Use print_insn_big_powerpc for
64 bit code.
2000-04-24 Nick Clifton <nickc@cygnus.com>
2000-04-24 Nick Clifton <nickc@redhat.com>
* fr30-desc.c (fr30_cgen_cpu_open): Initialise signed_overflow
field.
Sun Apr 23 17:54:14 2000 Denis Chertykov <denisc@overta.ru>
2000-04-23 Denis Chertykov <denisc@overta.ru>
* avr-dis.c (reg_fmul_d): New. Extract destination register from
FMUL instruction.
@ -715,7 +730,7 @@ Sun Apr 23 17:54:14 2000 Denis Chertykov <denisc@overta.ru>
(print_insn_avr): Handle MOVW, MULS, MULSU, FMUL, FMULS, FMULSU,
EICALL, EIJMP, LPM r,Z, ELPM r,Z, SPM, ESPM instructions.
2000-04-22 Timothy Wall <twall@cygnus.com>
2000-04-22 Timothy Wall <twall@redhat.com>
* ia64-gen.c (general): Add an ordered table of primary
opcode names, as well as priority fields to disassembly data
@ -732,17 +747,17 @@ Sun Apr 23 17:54:14 2000 Denis Chertykov <denisc@overta.ru>
* ia64-opc-b.c: Use more abbreviations.
* ia64-asmtab.c: Regenerate.
Fri Apr 21 16:03:39 2000 Jason Eckhardt <jle@cygnus.com>
2000-04-21 Jason Eckhardt <jle@redhat.com>
* hppa-dis.c (extract_16): New function.
(print_insn_hppa): Fix incorrect handling of 'fe'. Added handling of
new operand types l,y,&,fe,fE,fx.
Fri Apr 21 13:20:53 2000 Richard Henderson <rth@cygnus.com>
David Mosberger <davidm@hpl.hp.com>
Timothy Wall <twall@cygnus.com>
Bob Manson <manson@charmed.cygnus.com>
Jim Wilson <wilson@cygnus.com>
2000-04-21 Richard Henderson <rth@redhat.com>
David Mosberger <davidm@hpl.hp.com>
Timothy Wall <twall@redhat.com>
Bob Manson <manson@charmed.cygnus.com>
Jim Wilson <wilson@redhat.com>
* Makefile.am (HFILES): Add ia64-asmtab.h, ia64-opc.h.
(CFILES): Add ia64-dis.c, ia64-opc-a.c, ia64-opc-b.c, ia64-opc-f.c,
@ -761,7 +776,7 @@ Fri Apr 21 13:20:53 2000 Richard Henderson <rth@cygnus.com>
ia64-opc-m.c, ia64-opc-x.c, ia64-opc.c, ia64-opc.h, ia64-raw.tbl,
ia64-war.tbl, ia64-waw.tbl): New files.
2000-04-20 Alexandre Oliva <aoliva@cygnus.com>
2000-04-20 Alexandre Oliva <aoliva@redhat.com>
* m10300-dis.c (HAVE_AM30, HAVE_AM33): Define.
(disassemble): Use them.
@ -785,21 +800,21 @@ Fri Apr 21 13:20:53 2000 Richard Henderson <rth@cygnus.com>
w65-dis.c, z8k-dis.c, z8kgen.c: Include sysdep.h. Remove
ansidecl.h as sysdep.h includes it.
Fri Apr 7 15:56:57 2000 Andrew Cagney <cagney@b1.cygnus.com>
2000-04-7 Andrew Cagney <cagney@b1.redhat.com>
* configure.in (WARN_CFLAGS): Set to -W -Wall by default. Add
--enable-build-warnings option.
* Makefile.am (AM_CFLAGS, WARN_CFLAGS): Add definitions.
* Makefile.in, configure: Re-generate.
Wed Apr 5 22:28:18 2000 J"orn Rennecke <amylaar@cygnus.co.uk>
2000-04-05 J"orn Rennecke <amylaar@redhat.com>
* sh-opc.c (sh_table): Use A_DISP_PC / PCRELIMM_8BY2 for ldre & ldrs.
stc GBR,@-<REG_N> is available for arch_sh1_up.
Group parallel processing insn with identical mnemonics together.
Make three-operand psha / pshl come first.
Wed Apr 5 22:05:40 2000 J"orn Rennecke <amylaar@cygnus.co.uk>
2000-04-05 J"orn Rennecke <amylaar@redhat.co.uk>
* sh-opc.h (sh_nibble_type): Remove DISP_8 and DISP_4.
Split IMM_[48]{,BY[24]} into IMM[01]_[48]{,BY[24]}. Add REPEAT.
@ -832,7 +847,7 @@ Wed Apr 5 22:05:40 2000 J"orn Rennecke <amylaar@cygnus.co.uk>
the parameter ATTRIBUTE_UNUSED.
* ppc-opc.c: Add ATTRIBUTE_UNUSED as needed.
2000-04-01 Alexandre Oliva <aoliva@cygnus.com>
2000-04-01 Alexandre Oliva <aoliva@redhat.com>
* m10300-opc.c: SP-based offsets are always unsigned.
@ -841,7 +856,7 @@ Wed Apr 5 22:05:40 2000 J"orn Rennecke <amylaar@cygnus.co.uk>
* arm-opc.h (thumb_opcodes): Disassemble 0xde.. to "bal"
[branch always] instead of "undefined".
2000-03-27 Nick Clifton <nickc@cygnus.com>
2000-03-27 Nick Clifton <nickc@redhat.com>
* d30v-opc.c (d30v_format_table): Move SHORT_AR to end of list of
short instructions, from end of list of long instructions.
@ -868,11 +883,11 @@ Wed Apr 5 22:05:40 2000 J"orn Rennecke <amylaar@cygnus.co.uk>
* disassemble.c: Likewise.
* configure: Regenerate.
Mon Mar 6 19:52:05 2000 J"orn Rennecke <amylaar@cygnus.co.uk>
2000-03-06 J"oern Rennecke <amylaar@redhat.com>
* sh-opc.h (sh_table): ldre and ldrs have a *signed* displacement.
2000-03-02 J"orn Rennecke <amylaar@cygnus.co.uk>
2000-03-02 J"orn Rennecke <amylaar@redhat.co.uk>
* d30v-dis.c (print_insn): Remove d*i hacks. Use per-operand
flag to determine if operand is pc-relative.
@ -893,7 +908,7 @@ Mon Mar 6 19:52:05 2000 J"orn Rennecke <amylaar@cygnus.co.uk>
(SHORT_U, SHORT_A5S): Removed stray alternatives.
(d30v_opcode_table): Use new *r formats.
2000-02-28 Nick Clifton <nickc@cygnus.com>
2000-02-28 Nick Clifton <nickc@redhat.com>
* m32r-desc.c (m32r_cgen_cpu_open): Replace 'flags' with
'signed_overflow_ok_p'.
@ -904,13 +919,13 @@ Mon Mar 6 19:52:05 2000 J"orn Rennecke <amylaar@cygnus.co.uk>
name of the libtool directory.
* Makefile.in: Rebuild.
2000-02-24 Nick Clifton <nickc@cygnus.com>
2000-02-24 Nick Clifton <nickc@redhat.com>
* cgen-opc.c (cgen_set_signed_overflow_ok): New function.
(cgen_clear_signed_overflow_ok): New function.
(cgen_signed_overflow_ok_p): New function.
2000-02-23 Andrew Haley <aph@cygnus.com>
2000-02-23 Andrew Haley <aph@redhat.com>
* m32r-asm.c, m32r-desc.c, m32r-desc.h, m32r-dis.c,
m32r-ibld.c,m32r-opc.h: Rebuild.
@ -928,13 +943,13 @@ Mon Mar 6 19:52:05 2000 J"orn Rennecke <amylaar@cygnus.co.uk>
* Makefile.in: Regenerate.
* configure: Likewise.
2000-02-22 Chandra Chavva <cchavva@cygnus.com>
2000-02-22 Chandra Chavva <cchavva@redhat.com>
* d30v-opc.c (d30v_opcode_tab) : Added FLAG_NOT_WITH_ADDSUBppp to
ST2H, STB, STH, STHH, STW and ST2H opcodes to prohibit parallel
procedure.
2000-02-22 Andrew Haley <aph@cygnus.com>
2000-02-22 Andrew Haley <aph@redhat.com>
* mips-dis.c (_print_insn_mips): New arg for OPCODE_IS_MEMBER:
force gp32 to zero.
@ -951,7 +966,7 @@ Mon Mar 6 19:52:05 2000 J"orn Rennecke <amylaar@cygnus.co.uk>
* dis-buf.c (buffer_read_memory): Change `length' param and all int
vars to unsigned.
Thu Feb 17 00:18:12 2000 J"orn Rennecke <amylaar@cygnus.co.uk>
2000-02-17 J"orn Rennecke <amylaar@redhat.co.uk>
* sh-dis.c (print_movxy, print_insn_ddt, print_dsp_reg): New functions.
(print_insn_ppi): Likewise.
@ -968,7 +983,7 @@ Thu Feb 17 00:18:12 2000 J"orn Rennecke <amylaar@cygnus.co.uk>
(sh_table): Split up insn with FD_REG_N into ones with F_REG_N and
D_REG_N. Fill in arch field. Add sh-dsp insns.
2000-02-14 Fernando Nasser <fnasser@totem.to.cygnus.com>
2000-02-14 Fernando Nasser <fnasser@totem.to.redhat.com>
* arm-dis.c: Change flavor name from atpcs-special to
special-atpcs to prevent name conflict in gdb.
@ -978,7 +993,7 @@ Thu Feb 17 00:18:12 2000 J"orn Rennecke <amylaar@cygnus.co.uk>
(print_insn_thumb): Use the register name entry from the currently
selected flavor for LR and PC.
2000-02-10 Nick Clifton <nickc@cygnus.com>
2000-02-10 Nick Clifton <nickc@redhat.com>
* mcore-opc.h (enum mcore_opclass): Add MULSH and OPSR
classes.
@ -989,7 +1004,7 @@ Thu Feb 17 00:18:12 2000 J"orn Rennecke <amylaar@cygnus.co.uk>
(print_insn_mcore): Add support for little endian targets.
Add support for MULSH and OPSR classes.
2000-02-07 Nick Clifton <nickc@cygnus.com>
2000-02-07 Nick Clifton <nickc@redhat.com>
* arm-dis.c (parse_arm_diassembler_option): Rename again.
Previous delat did not take.
@ -1034,7 +1049,7 @@ Thu Feb 17 00:18:12 2000 J"orn Rennecke <amylaar@cygnus.co.uk>
* arm-dis.c (printf_insn_thumb): Prevent double dumping
of raw thumb instructions.
2000-01-20 Nick Clifton <nickc@cygnus.com>
2000-01-20 Nick Clifton <nickc@redhat.com>
* mcore-opc.h (mcore_table): Add "add" as an alias for "addu".

5
opcodes/Makefile.am
View File

@ -40,6 +40,7 @@ CFILES = \
alpha-opc.c \
arc-dis.c \
arc-opc.c \
arc-ext.c \
arm-dis.c \
avr-dis.c \
cgen-asm.c \
@ -121,6 +122,7 @@ ALL_MACHINES = \
alpha-opc.lo \
arc-dis.lo \
arc-opc.lo \
arc-ext.lo \
arm-dis.lo \
avr-dis.lo \
cgen-asm.lo \
@ -342,9 +344,10 @@ arc-dis.lo: arc-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
$(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/opcode/arc.h \
$(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
$(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(INCDIR)/elf/arc.h \
$(INCDIR)/elf/reloc-macros.h opintl.h
$(INCDIR)/elf/reloc-macros.h opintl.h arc-dis.h arc-ext.h
arc-opc.lo: arc-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
$(INCDIR)/opcode/arc.h opintl.h
arc-ext.lo: $(BFD_H) $(INCDIR)/libiberty.h arc-ext.h
arm-dis.lo: arm-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
$(INCDIR)/dis-asm.h $(BFD_H) arm-opc.h $(INCDIR)/coff/internal.h \
$(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h opintl.h $(BFDDIR)/elf-bfd.h \

5
opcodes/Makefile.in
View File

@ -151,6 +151,7 @@ CFILES = \
alpha-opc.c \
arc-dis.c \
arc-opc.c \
arc-ext.c \
arm-dis.c \
avr-dis.c \
cgen-asm.c \
@ -233,6 +234,7 @@ ALL_MACHINES = \
alpha-opc.lo \
arc-dis.lo \
arc-opc.lo \
arc-ext.lo \
arm-dis.lo \
avr-dis.lo \
cgen-asm.lo \
@ -852,9 +854,10 @@ arc-dis.lo: arc-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
$(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/opcode/arc.h \
$(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
$(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(INCDIR)/elf/arc.h \
$(INCDIR)/elf/reloc-macros.h opintl.h
$(INCDIR)/elf/reloc-macros.h opintl.h arc-dis.h arc-ext.h
arc-opc.lo: arc-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
$(INCDIR)/opcode/arc.h opintl.h
arc-ext.lo: $(BFD_H) $(INCDIR)/libiberty.h arc-ext.h
arm-dis.lo: arm-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
$(INCDIR)/dis-asm.h $(BFD_H) arm-opc.h $(INCDIR)/coff/internal.h \
$(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h opintl.h $(BFDDIR)/elf-bfd.h \

1418
opcodes/arc-dis.c
View File

File diff suppressed because it is too large Load Diff

80
opcodes/arc-dis.h Normal file
View File

@ -0,0 +1,80 @@
/* Disassembler structures definitions for the ARC.
Copyright (C) 1994, 1995, 1997, 1998 Free Software Foundation, Inc.
Contributed by Doug Evans (dje@cygnus.com).
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software Foundation,
Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#ifndef ARCDIS_H
#define ARCDIS_H
enum
{
BR_exec_when_no_jump,
BR_exec_always,
BR_exec_when_jump
};
enum Flow
{
noflow,
direct_jump,
direct_call,
indirect_jump,
indirect_call,
invalid_instr
};
enum { no_reg = 99 };
enum { allOperandsSize = 256 };
struct arcDisState
{
void *_this;
int instructionLen;
void (*err)(void*, const char*);
const char *(*coreRegName)(void*, int);
const char *(*auxRegName)(void*, int);
const char *(*condCodeName)(void*, int);
const char *(*instName)(void*, int, int, int*);
unsigned char* instruction;
unsigned index;
const char *comm[6]; /* instr name, cond, NOP, 3 operands */
int opWidth;
int targets[4];
int addresses[4];
/* Set as a side-effect of calling the disassembler.
Used only by the debugger. */
enum Flow flow;
int register_for_indirect_jump;
int ea_reg1, ea_reg2, _offset;
int _cond, _opcode;
unsigned long words[2];
char *commentBuffer;
char instrBuffer[40];
char operandBuffer[allOperandsSize];
char _ea_present;
char _mem_load;
char _load_len;
char nullifyMode;
unsigned char commNum;
unsigned char isBranch;
unsigned char tcnt;
unsigned char acnt;
};
#define __TRANSLATION_REQUIRED(state) ((state).acnt != 0)
#endif

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