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x86/APX: optimize {nf} forms of ADD/SUB with specific immediates
Unlike for the legacy forms, where there's a difference in the resulting EFLAGS, for the NF variants we can safely replace ones using 0x80 by the respectively other insn while negating the immediate, saving 3 immediate bytes (just 1 though for 16-bit operand size). Similarly we can replace ones using 1 / -1 by INC/DEC (eliminating the immediate).
This commit is contained in:
Jan Beulich
parent
f63d85cc78
commit
0868b8999b
@ -5327,6 +5327,84 @@ optimize_encoding (void)
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}
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}
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/* Try to shorten {nf} encodings, by shortening operand size or switching to
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functionally identical encodings. */
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static void
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optimize_nf_encoding (void)
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{
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if (i.tm.base_opcode == 0x80
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&& (i.tm.extension_opcode == 0 || i.tm.extension_opcode == 5)
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&& i.suffix != BYTE_MNEM_SUFFIX
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&& !i.types[1].bitfield.byte
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&& !i.types[2].bitfield.byte
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&& i.op[0].imms->X_op == O_constant
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&& i.op[0].imms->X_add_number == 0x80)
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{
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/* Optimize: -O:
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{nf} addw $0x80, ... -> {nf} subw $-0x80, ...
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{nf} addl $0x80, ... -> {nf} subl $-0x80, ...
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{nf} addq $0x80, ... -> {nf} subq $-0x80, ...
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{nf} subw $0x80, ... -> {nf} addw $-0x80, ...
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{nf} subl $0x80, ... -> {nf} addl $-0x80, ...
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{nf} subq $0x80, ... -> {nf} addq $-0x80, ...
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*/
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i.tm.base_opcode |= 3;
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i.tm.extension_opcode ^= 5;
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i.tm.opcode_modifier.w = 0;
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i.op[0].imms->X_add_number = -i.op[0].imms->X_add_number;
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i.tm.operand_types[0].bitfield.imm8 = 0;
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i.tm.operand_types[0].bitfield.imm8s = 1;
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i.tm.operand_types[0].bitfield.imm16 = 0;
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i.tm.operand_types[0].bitfield.imm32 = 0;
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i.tm.operand_types[0].bitfield.imm32s = 0;
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i.types[0] = i.tm.operand_types[0];
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}
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else if ((i.tm.base_opcode | 3) == 0x83
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&& (i.tm.extension_opcode == 0 || i.tm.extension_opcode == 5)
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&& i.op[0].imms->X_op == O_constant
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&& (i.op[0].imms->X_add_number == 1
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|| i.op[0].imms->X_add_number == -1
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/* While for wider than byte operations immediates were suitably
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adjusted earlier on, 0xff in the byte case needs covering
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explicitly. */
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|| (i.op[0].imms->X_add_number == 0xff
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&& (i.suffix == BYTE_MNEM_SUFFIX
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|| i.types[i.operands - 1].bitfield.byte))))
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{
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/* Optimize: -O:
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{nf} add $1, ... -> {nf} inc ...
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{nf} add $-1, ... -> {nf} dec ...
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{nf} add $0xf...f, ... -> {nf} dec ...
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{nf} sub $1, ... -> {nf} dec ...
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{nf} sub $-1, ... -> {nf} inc ...
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{nf} sub $0xf...f, ... -> {nf} inc ...
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*/
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i.tm.base_opcode = 0xfe;
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i.tm.extension_opcode
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= (i.op[0].imms->X_add_number == 1) != (i.tm.extension_opcode == 0);
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i.tm.opcode_modifier.w = 1;
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i.types[0] = i.types[1];
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i.types[1] = i.types[2];
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i.tm.operand_types[0] = i.tm.operand_types[1];
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i.tm.operand_types[1] = i.tm.operand_types[2];
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i.op[0] = i.op[1];
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i.op[1] = i.op[2];
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i.flags[0] = i.flags[1];
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i.flags[1] = i.flags[2];
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i.reloc[0] = i.reloc[1];
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i.reloc[1] = NO_RELOC;
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i.imm_operands = 0;
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--i.operands;
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}
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}
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static void
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s_noopt (int dummy ATTRIBUTE_UNUSED)
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{
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@ -7206,7 +7284,11 @@ md_assemble (char *line)
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}
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if (optimize && !i.no_optimize && i.tm.opcode_modifier.optimize)
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optimize_encoding ();
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{
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if (i.has_nf)
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optimize_nf_encoding ();
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optimize_encoding ();
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}
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/* Past optimization there's no need to distinguish encoding_evex,
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encoding_evex512, and encoding_egpr anymore. */
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@ -701,6 +701,8 @@ Disassembly of section \.text:
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\s*[a-f0-9]+:\s*62 d4 6c 1c 33 8c 80 23 01 00 00\s+\{nf\} xor edx,ecx,DWORD PTR \[r8\+rax\*4\+0x123\]
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\s*[a-f0-9]+:\s*62 54 fc 0c 33 8c 80 23 01 00 00\s+\{nf\} xor r9,QWORD PTR \[r8\+rax\*4\+0x123\]
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\s*[a-f0-9]+:\s*62 54 84 14 33 8c 80 23 01 00 00\s+\{nf\} xor r31,r9,QWORD PTR \[r8\+rax\*4\+0x123\]
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0[0-9a-f]+ <intel>:
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\s*[a-f0-9]+:\s*62 f4 7c 0c 80 c3 7b\s+\{nf\} add bl,0x7b
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\s*[a-f0-9]+:\s*62 f4 6c 1c 80 c3 7b\s+\{nf\} add dl,bl,0x7b
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\s*[a-f0-9]+:\s*62 f4 7d 0c 83 c2 7b\s+\{nf\} add dx,0x7b
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1483
gas/testsuite/gas/i386/x86-64-apx-nf-optimize.d
Normal file
1483
gas/testsuite/gas/i386/x86-64-apx-nf-optimize.d
Normal file
File diff suppressed because it is too large
Load Diff
@ -701,6 +701,8 @@ Disassembly of section \.text:
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\s*[a-f0-9]+:\s*62 d4 6c 1c 33 8c 80 23 01 00 00\s+\{nf\} xor 0x123\(%r8,%rax,4\),%ecx,%edx
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\s*[a-f0-9]+:\s*62 54 fc 0c 33 8c 80 23 01 00 00\s+\{nf\} xor 0x123\(%r8,%rax,4\),%r9
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\s*[a-f0-9]+:\s*62 54 84 14 33 8c 80 23 01 00 00\s+\{nf\} xor 0x123\(%r8,%rax,4\),%r9,%r31
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0[0-9a-f]+ <intel>:
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\s*[a-f0-9]+:\s*62 f4 7c 0c 80 c3 7b\s+\{nf\} add\s+\$0x7b,%bl
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\s*[a-f0-9]+:\s*62 f4 6c 1c 80 c3 7b\s+\{nf\} add\s+\$0x7b,%bl,%dl
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\s*[a-f0-9]+:\s*62 f4 7d 0c 83 c2 7b\s+\{nf\} add\s+\$0x7b,%dx
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@ -697,7 +697,8 @@ _start:
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{nf} xor 291(%r8, %rax, 4), %r9
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{nf} xor 291(%r8, %rax, 4), %r9, %r31
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.intel_syntax noprefix
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.intel_syntax noprefix
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intel:
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{nf} add bl, 123
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{nf} add dl, bl, 123
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{nf} add dx, 123
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@ -1377,3 +1378,58 @@ _start:
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{nf} xor edx, ecx, DWORD PTR [r8+rax*4+291]
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{nf} xor r9, QWORD PTR [r8+rax*4+291]
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{nf} xor r31, r9, QWORD PTR [r8+rax*4+291]
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.att_syntax prefix
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optimize:
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.irp op, add, sub
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{nf} \op $128, %bl
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{nf} \op $128, %bl, %dl
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{nf} \op $128, %dx
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{nf} \op $128, %dx, %ax
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{nf} \op $128, %ecx
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{nf} \op $128, %ecx, %edx
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{nf} \op $128, %r9
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{nf} \op $128, %r9, %r31
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{nf} \op\()b $128, (%rax)
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{nf} \op $128, (%rax), %bl
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{nf} \op\()w $128, (%rax)
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{nf} \op $128, (%rax), %dx
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{nf} \op\()l $128, (%rax)
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{nf} \op $128, (%rax), %ecx
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{nf} \op\()q $128, (%rax)
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{nf} \op $128, (%rax), %r9
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{nf} \op $1, %bl
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{nf} \op $1, %bl, %dl
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{nf} \op $1, %dx
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{nf} \op $1, %dx, %ax
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{nf} \op $1, %ecx
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{nf} \op $1, %ecx, %edx
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{nf} \op $1, %r9
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{nf} \op $1, %r9, %r31
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{nf} \op\()b $1, (%rax)
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{nf} \op $1, (%rax), %bl
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{nf} \op\()w $1, (%rax)
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{nf} \op $1, (%rax), %dx
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{nf} \op\()l $1, (%rax)
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{nf} \op $1, (%rax), %ecx
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{nf} \op\()q $1, (%rax)
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{nf} \op $1, (%rax), %r9
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{nf} \op $0xff, %bl
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{nf} \op $-1, %bl, %dl
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{nf} \op $0xffff, %dx
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{nf} \op $-1, %dx, %ax
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{nf} \op $0xffffffff, %ecx
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{nf} \op $-1, %ecx, %edx
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{nf} \op $-1, %r9
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{nf} \op $-1, %r9, %r31
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{nf} \op\()b $0xff, (%rax)
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{nf} \op $-1, (%rax), %bl
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{nf} \op\()w $0xffff, (%rax)
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{nf} \op $-1, (%rax), %dx
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{nf} \op\()l $0xffffffff, (%rax)
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{nf} \op $-1, (%rax), %ecx
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{nf} \op\()q $-1, (%rax)
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{nf} \op $-1, (%rax), %r9
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.endr
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@ -393,6 +393,7 @@ run_dump_test "x86-64-apx-jmpabs-intel"
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run_dump_test "x86-64-apx-jmpabs-inval"
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run_dump_test "x86-64-apx-nf"
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run_dump_test "x86-64-apx-nf-intel"
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run_dump_test "x86-64-apx-nf-optimize"
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run_dump_test "x86-64-apx-zu"
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run_dump_test "x86-64-apx-zu-intel"
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run_list_test "x86-64-apx-zu-inval"
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@ -312,25 +312,25 @@ sti, 0xfb, 0, NoSuf, {}
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// Arithmetic.
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<alu2:opc:c:optz:optt:opti:nf, +
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add:0:C::::NF, +
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or:1:C::Optimize::NF, +
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adc:2:C::::, +
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sbb:3:::::, +
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and:4:C::Optimize:Optimize:NF, +
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sub:5::Optimize:::NF, +
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xor:6:C:Optimize:::NF>
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<alu2:opc:c:optz:optt:opti:optiE:nf, +
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add:0:C::::Optimize:NF, +
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or:1:C::Optimize:::NF, +
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adc:2:C:::::, +
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sbb:3::::::, +
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and:4:C::Optimize:Optimize::NF, +
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sub:5::Optimize:::Optimize:NF, +
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xor:6:C:Optimize::::NF>
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<alu2>, <alu2:opc> << 3, APX_F, D|<alu2:c>|W|CheckOperandSize|Modrm|No_sSuf|DstVVVV|EVexMap4|<alu2:nf>|<alu2:optz>, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
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<alu2>, <alu2:opc> << 3, 0, D|W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixLock|<alu2:optz>|<alu2:optt>, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
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<alu2>, <alu2:opc> << 3, APX_F, D|W|CheckOperandSize|Modrm|No_sSuf|EVexMap4|<alu2:nf>, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
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<alu2>, 0x83/<alu2:opc>, APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|DstVVVV|EVexMap4|<alu2:nf>, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
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<alu2>, 0x83/<alu2:opc>, APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|DstVVVV|EVexMap4|<alu2:nf>|<alu2:optiE>, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
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<alu2>, 0x83/<alu2:opc>, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock|<alu2:opti>, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex }
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<alu2>, 0x83/<alu2:opc>, APX_F, Modrm|No_bSuf|No_sSuf|EVexMap4|<alu2:nf>, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex }
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<alu2>, 0x83/<alu2:opc>, APX_F, Modrm|No_bSuf|No_sSuf|EVexMap4|<alu2:nf>|<alu2:optiE>, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex }
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<alu2>, 0x04 | (<alu2:opc> << 3), 0, W|No_sSuf|<alu2:opti>, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
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<alu2>, 0x80/<alu2:opc>, APX_F, W|Modrm|CheckOperandSize|No_sSuf|DstVVVV|EVexMap4|<alu2:nf>, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
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<alu2>, 0x80/<alu2:opc>, APX_F, W|Modrm|CheckOperandSize|No_sSuf|DstVVVV|EVexMap4|<alu2:nf>|<alu2:optiE>, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
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<alu2>, 0x80/<alu2:opc>, 0, W|Modrm|No_sSuf|HLEPrefixLock|<alu2:opti>, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
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<alu2>, 0x80/<alu2:opc>, APX_F, W|Modrm|EVexMap4|No_sSuf|<alu2:nf>, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
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<alu2>, 0x80/<alu2:opc>, APX_F, W|Modrm|EVexMap4|No_sSuf|<alu2:nf>|<alu2:optiE>, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
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<alu2>
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@ -826,7 +826,7 @@ static const insn_template i386_optab[] =
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0, 0, 0, 0, 1, 0 } } } },
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{ MN_add, 0x83, 3, SPACE_EVEXMAP4, 0,
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{ 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 3, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 3, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0,
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1, 0 },
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{ { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0 } },
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
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@ -848,7 +848,7 @@ static const insn_template i386_optab[] =
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0, 0, 0, 0, 1, 0 } } } },
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{ MN_add, 0x83, 2, SPACE_EVEXMAP4, 0,
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{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0,
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1, 0 },
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{ { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0 } },
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
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@ -868,7 +868,7 @@ static const insn_template i386_optab[] =
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0, 0, 0, 0, 0, 0 } } } },
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{ MN_add, 0x80, 3, SPACE_EVEXMAP4, 0,
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{ 0, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 3, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 3, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0,
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1, 0 },
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{ { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0 } },
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
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@ -890,7 +890,7 @@ static const insn_template i386_optab[] =
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0, 0, 0, 0, 1, 0 } } } },
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{ MN_add, 0x80, 2, SPACE_EVEXMAP4, 0,
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{ 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0,
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1, 0 },
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{ { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0 } },
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
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@ -1356,7 +1356,7 @@ static const insn_template i386_optab[] =
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0, 0, 0, 0, 1, 0 } } } },
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{ MN_sub, 0x83, 3, SPACE_EVEXMAP4, 5,
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{ 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 3, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 3, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0,
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1, 0 },
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{ { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0 } },
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
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@ -1378,7 +1378,7 @@ static const insn_template i386_optab[] =
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0, 0, 0, 0, 1, 0 } } } },
|
||||
{ MN_sub, 0x83, 2, SPACE_EVEXMAP4, 5,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0,
|
||||
1, 0 },
|
||||
{ { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
@ -1398,7 +1398,7 @@ static const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0 } } } },
|
||||
{ MN_sub, 0x80, 3, SPACE_EVEXMAP4, 5,
|
||||
{ 0, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 3, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 3, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0,
|
||||
1, 0 },
|
||||
{ { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
@ -1420,7 +1420,7 @@ static const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 1, 0 } } } },
|
||||
{ MN_sub, 0x80, 2, SPACE_EVEXMAP4, 5,
|
||||
{ 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0,
|
||||
1, 0 },
|
||||
{ { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
|
||||
Loading…
Reference in New Issue
Block a user